3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
| 4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
|
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "cpu/timebuf.hh"
44#include "config/full_system.hh"
45#include "config/the_isa.hh"
46#include "config/use_checker.hh"
47#include "cpu/activity.hh"
48#include "cpu/base.hh"
49#include "cpu/simple_thread.hh"
50#include "cpu/o3/comm.hh"
51#include "cpu/o3/cpu_policy.hh"
52#include "cpu/o3/scoreboard.hh"
53#include "cpu/o3/thread_state.hh"
54//#include "cpu/o3/thread_context.hh"
55#include "sim/process.hh"
56
57#include "params/DerivO3CPU.hh"
58
59template <class>
60class Checker;
61class ThreadContext;
62template <class>
63class O3ThreadContext;
64
65class Checkpoint;
66class MemObject;
67class Process;
68
69class BaseCPUParams;
70
71class BaseO3CPU : public BaseCPU
72{
73 //Stuff that's pretty ISA independent will go here.
74 public:
75 BaseO3CPU(BaseCPUParams *params);
76
77 void regStats();
78};
79
80/**
81 * FullO3CPU class, has each of the stages (fetch through commit)
82 * within it, as well as all of the time buffers between stages. The
83 * tick() function for the CPU is defined here.
84 */
85template <class Impl>
86class FullO3CPU : public BaseO3CPU
87{
88 public:
89 // Typedefs from the Impl here.
90 typedef typename Impl::CPUPol CPUPolicy;
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef typename Impl::O3CPU O3CPU;
93
94 typedef O3ThreadState<Impl> ImplState;
95 typedef O3ThreadState<Impl> Thread;
96
97 typedef typename std::list<DynInstPtr>::iterator ListIt;
98
99 friend class O3ThreadContext<Impl>;
100
101 public:
102 enum Status {
103 Running,
104 Idle,
105 Halted,
106 Blocked,
107 SwitchedOut
108 };
109
110 TheISA::TLB * itb;
111 TheISA::TLB * dtb;
112
113 /** Overall CPU status. */
114 Status _status;
115
116 /** Per-thread status in CPU, used for SMT. */
117 Status _threadStatus[Impl::MaxThreads];
118
119 private:
120 class TickEvent : public Event
121 {
122 private:
123 /** Pointer to the CPU. */
124 FullO3CPU<Impl> *cpu;
125
126 public:
127 /** Constructs a tick event. */
128 TickEvent(FullO3CPU<Impl> *c);
129
130 /** Processes a tick event, calling tick() on the CPU. */
131 void process();
132 /** Returns the description of the tick event. */
133 const char *description() const;
134 };
135
136 /** The tick event used for scheduling CPU ticks. */
137 TickEvent tickEvent;
138
139 /** Schedule tick event, regardless of its current state. */
140 void scheduleTickEvent(int delay)
141 {
142 if (tickEvent.squashed())
143 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
144 else if (!tickEvent.scheduled())
145 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
146 }
147
148 /** Unschedule tick event, regardless of its current state. */
149 void unscheduleTickEvent()
150 {
151 if (tickEvent.scheduled())
152 tickEvent.squash();
153 }
154
155 class ActivateThreadEvent : public Event
156 {
157 private:
158 /** Number of Thread to Activate */
159 ThreadID tid;
160
161 /** Pointer to the CPU. */
162 FullO3CPU<Impl> *cpu;
163
164 public:
165 /** Constructs the event. */
166 ActivateThreadEvent();
167
168 /** Initialize Event */
169 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
170
171 /** Processes the event, calling activateThread() on the CPU. */
172 void process();
173
174 /** Returns the description of the event. */
175 const char *description() const;
176 };
177
178 /** Schedule thread to activate , regardless of its current state. */
179 void
180 scheduleActivateThreadEvent(ThreadID tid, int delay)
181 {
182 // Schedule thread to activate, regardless of its current state.
183 if (activateThreadEvent[tid].squashed())
184 reschedule(activateThreadEvent[tid],
185 nextCycle(curTick() + ticks(delay)));
186 else if (!activateThreadEvent[tid].scheduled())
187 schedule(activateThreadEvent[tid],
188 nextCycle(curTick() + ticks(delay)));
189 }
190
191 /** Unschedule actiavte thread event, regardless of its current state. */
192 void
193 unscheduleActivateThreadEvent(ThreadID tid)
194 {
195 if (activateThreadEvent[tid].scheduled())
196 activateThreadEvent[tid].squash();
197 }
198
199 /** The tick event used for scheduling CPU ticks. */
200 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
201
202 class DeallocateContextEvent : public Event
203 {
204 private:
205 /** Number of Thread to deactivate */
206 ThreadID tid;
207
208 /** Should the thread be removed from the CPU? */
209 bool remove;
210
211 /** Pointer to the CPU. */
212 FullO3CPU<Impl> *cpu;
213
214 public:
215 /** Constructs the event. */
216 DeallocateContextEvent();
217
218 /** Initialize Event */
219 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
220
221 /** Processes the event, calling activateThread() on the CPU. */
222 void process();
223
224 /** Sets whether the thread should also be removed from the CPU. */
225 void setRemove(bool _remove) { remove = _remove; }
226
227 /** Returns the description of the event. */
228 const char *description() const;
229 };
230
231 /** Schedule cpu to deallocate thread context.*/
232 void
233 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
234 {
235 // Schedule thread to activate, regardless of its current state.
236 if (deallocateContextEvent[tid].squashed())
237 reschedule(deallocateContextEvent[tid],
238 nextCycle(curTick() + ticks(delay)));
239 else if (!deallocateContextEvent[tid].scheduled())
240 schedule(deallocateContextEvent[tid],
241 nextCycle(curTick() + ticks(delay)));
242 }
243
244 /** Unschedule thread deallocation in CPU */
245 void
246 unscheduleDeallocateContextEvent(ThreadID tid)
247 {
248 if (deallocateContextEvent[tid].scheduled())
249 deallocateContextEvent[tid].squash();
250 }
251
252 /** The tick event used for scheduling CPU ticks. */
253 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
254
255 public:
256 /** Constructs a CPU with the given parameters. */
257 FullO3CPU(DerivO3CPUParams *params);
258 /** Destructor. */
259 ~FullO3CPU();
260
261 /** Registers statistics. */
262 void regStats();
263
264 void demapPage(Addr vaddr, uint64_t asn)
265 {
266 this->itb->demapPage(vaddr, asn);
267 this->dtb->demapPage(vaddr, asn);
268 }
269
270 void demapInstPage(Addr vaddr, uint64_t asn)
271 {
272 this->itb->demapPage(vaddr, asn);
273 }
274
275 void demapDataPage(Addr vaddr, uint64_t asn)
276 {
277 this->dtb->demapPage(vaddr, asn);
278 }
279
280 /** Returns a specific port. */
281 Port *getPort(const std::string &if_name, int idx);
282
283 /** Ticks CPU, calling tick() on each stage, and checking the overall
284 * activity to see if the CPU should deschedule itself.
285 */
286 void tick();
287
288 /** Initialize the CPU */
289 void init();
290
291 /** Returns the Number of Active Threads in the CPU */
292 int numActiveThreads()
293 { return activeThreads.size(); }
294
295 /** Add Thread to Active Threads List */
296 void activateThread(ThreadID tid);
297
298 /** Remove Thread from Active Threads List */
299 void deactivateThread(ThreadID tid);
300
301 /** Setup CPU to insert a thread's context */
302 void insertThread(ThreadID tid);
303
304 /** Remove all of a thread's context from CPU */
305 void removeThread(ThreadID tid);
306
307 /** Count the Total Instructions Committed in the CPU. */
308 virtual Counter totalInstructions() const;
309
310 /** Add Thread to Active Threads List. */
311 void activateContext(ThreadID tid, int delay);
312
313 /** Remove Thread from Active Threads List */
314 void suspendContext(ThreadID tid);
315
316 /** Remove Thread from Active Threads List &&
317 * Possibly Remove Thread Context from CPU.
318 */
319 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
320
321 /** Remove Thread from Active Threads List &&
322 * Remove Thread Context from CPU.
323 */
324 void haltContext(ThreadID tid);
325
326 /** Activate a Thread When CPU Resources are Available. */
327 void activateWhenReady(ThreadID tid);
328
329 /** Add or Remove a Thread Context in the CPU. */
330 void doContextSwitch();
331
332 /** Update The Order In Which We Process Threads. */
333 void updateThreadPriority();
334
335 /** Serialize state. */
336 virtual void serialize(std::ostream &os);
337
338 /** Unserialize from a checkpoint. */
339 virtual void unserialize(Checkpoint *cp, const std::string §ion);
340
341 public:
342#if !FULL_SYSTEM
343 /** Executes a syscall.
344 * @todo: Determine if this needs to be virtual.
345 */
346 void syscall(int64_t callnum, ThreadID tid);
347#endif
348
349 /** Starts draining the CPU's pipeline of all instructions in
350 * order to stop all memory accesses. */
351 virtual unsigned int drain(Event *drain_event);
352
353 /** Resumes execution after a drain. */
354 virtual void resume();
355
356 /** Signals to this CPU that a stage has completed switching out. */
357 void signalDrained();
358
359 /** Switches out this CPU. */
360 virtual void switchOut();
361
362 /** Takes over from another CPU. */
363 virtual void takeOverFrom(BaseCPU *oldCPU);
364
365 /** Get the current instruction sequence number, and increment it. */
366 InstSeqNum getAndIncrementInstSeq()
367 { return globalSeqNum++; }
368
369 /** Traps to handle given fault. */
370 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
371
372#if FULL_SYSTEM
373 /** HW return from error interrupt. */
374 Fault hwrei(ThreadID tid);
375
376 bool simPalCheck(int palFunc, ThreadID tid);
377
378 /** Returns the Fault for any valid interrupt. */
379 Fault getInterrupts();
380
381 /** Processes any an interrupt fault. */
382 void processInterrupts(Fault interrupt);
383
384 /** Halts the CPU. */
385 void halt() { panic("Halt not implemented!\n"); }
386
387 /** Update the Virt and Phys ports of all ThreadContexts to
388 * reflect change in memory connections. */
389 void updateMemPorts();
390
391 /** Check if this address is a valid instruction address. */
392 bool validInstAddr(Addr addr) { return true; }
393
394 /** Check if this address is a valid data address. */
395 bool validDataAddr(Addr addr) { return true; }
396#endif
397
398 /** Register accessors. Index refers to the physical register index. */
399
400 /** Reads a miscellaneous register. */
401 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
402
403 /** Reads a misc. register, including any side effects the read
404 * might have as defined by the architecture.
405 */
406 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
407
408 /** Sets a miscellaneous register. */
409 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
410 ThreadID tid);
411
412 /** Sets a misc. register, including any side effects the write
413 * might have as defined by the architecture.
414 */
415 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
416 ThreadID tid);
417
418 uint64_t readIntReg(int reg_idx);
419
420 TheISA::FloatReg readFloatReg(int reg_idx);
421
422 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
423
424 void setIntReg(int reg_idx, uint64_t val);
425
426 void setFloatReg(int reg_idx, TheISA::FloatReg val);
427
428 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
429
430 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
431
432 float readArchFloatReg(int reg_idx, ThreadID tid);
433
434 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
435
436 /** Architectural register accessors. Looks up in the commit
437 * rename table to obtain the true physical index of the
438 * architected register first, then accesses that physical
439 * register.
440 */
441 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
442
443 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
444
445 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
446
447 /** Sets the commit PC state of a specific thread. */
448 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
449
450 /** Reads the commit PC state of a specific thread. */
451 TheISA::PCState pcState(ThreadID tid);
452
453 /** Reads the commit PC of a specific thread. */
454 Addr instAddr(ThreadID tid);
455
456 /** Reads the commit micro PC of a specific thread. */
457 MicroPC microPC(ThreadID tid);
458
459 /** Reads the next PC of a specific thread. */
460 Addr nextInstAddr(ThreadID tid);
461
462 /** Initiates a squash of all in-flight instructions for a given
463 * thread. The source of the squash is an external update of
464 * state through the TC.
465 */
466 void squashFromTC(ThreadID tid);
467
468 /** Function to add instruction onto the head of the list of the
469 * instructions. Used when new instructions are fetched.
470 */
471 ListIt addInst(DynInstPtr &inst);
472
473 /** Function to tell the CPU that an instruction has completed. */
474 void instDone(ThreadID tid);
475
476 /** Add Instructions to the CPU Remove List*/
477 void addToRemoveList(DynInstPtr &inst);
478
479 /** Remove an instruction from the front end of the list. There's
480 * no restriction on location of the instruction.
481 */
482 void removeFrontInst(DynInstPtr &inst);
483
484 /** Remove all instructions that are not currently in the ROB.
485 * There's also an option to not squash delay slot instructions.*/
486 void removeInstsNotInROB(ThreadID tid);
487
488 /** Remove all instructions younger than the given sequence number. */
489 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
490
491 /** Removes the instruction pointed to by the iterator. */
492 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
493
494 /** Cleans up all instructions on the remove list. */
495 void cleanUpRemovedInsts();
496
497 /** Debug function to print all instructions on the list. */
498 void dumpInsts();
499
500 public:
501#ifndef NDEBUG
502 /** Count of total number of dynamic instructions in flight. */
503 int instcount;
504#endif
505
506 /** List of all the instructions in flight. */
507 std::list<DynInstPtr> instList;
508
509 /** List of all the instructions that will be removed at the end of this
510 * cycle.
511 */
512 std::queue<ListIt> removeList;
513
514#ifdef DEBUG
515 /** Debug structure to keep track of the sequence numbers still in
516 * flight.
517 */
518 std::set<InstSeqNum> snList;
519#endif
520
521 /** Records if instructions need to be removed this cycle due to
522 * being retired or squashed.
523 */
524 bool removeInstsThisCycle;
525
526 protected:
527 /** The fetch stage. */
528 typename CPUPolicy::Fetch fetch;
529
530 /** The decode stage. */
531 typename CPUPolicy::Decode decode;
532
533 /** The dispatch stage. */
534 typename CPUPolicy::Rename rename;
535
536 /** The issue/execute/writeback stages. */
537 typename CPUPolicy::IEW iew;
538
539 /** The commit stage. */
540 typename CPUPolicy::Commit commit;
541
542 /** The register file. */
543 typename CPUPolicy::RegFile regFile;
544
545 /** The free list. */
546 typename CPUPolicy::FreeList freeList;
547
548 /** The rename map. */
549 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
550
551 /** The commit rename map. */
552 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
553
554 /** The re-order buffer. */
555 typename CPUPolicy::ROB rob;
556
557 /** Active Threads List */
558 std::list<ThreadID> activeThreads;
559
560 /** Integer Register Scoreboard */
561 Scoreboard scoreboard;
562
563 TheISA::ISA isa[Impl::MaxThreads];
564
565 public:
566 /** Enum to give each stage a specific index, so when calling
567 * activateStage() or deactivateStage(), they can specify which stage
568 * is being activated/deactivated.
569 */
570 enum StageIdx {
571 FetchIdx,
572 DecodeIdx,
573 RenameIdx,
574 IEWIdx,
575 CommitIdx,
576 NumStages };
577
578 /** Typedefs from the Impl to get the structs that each of the
579 * time buffers should use.
580 */
581 typedef typename CPUPolicy::TimeStruct TimeStruct;
582
583 typedef typename CPUPolicy::FetchStruct FetchStruct;
584
585 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
586
587 typedef typename CPUPolicy::RenameStruct RenameStruct;
588
589 typedef typename CPUPolicy::IEWStruct IEWStruct;
590
591 /** The main time buffer to do backwards communication. */
592 TimeBuffer<TimeStruct> timeBuffer;
593
594 /** The fetch stage's instruction queue. */
595 TimeBuffer<FetchStruct> fetchQueue;
596
597 /** The decode stage's instruction queue. */
598 TimeBuffer<DecodeStruct> decodeQueue;
599
600 /** The rename stage's instruction queue. */
601 TimeBuffer<RenameStruct> renameQueue;
602
603 /** The IEW stage's instruction queue. */
604 TimeBuffer<IEWStruct> iewQueue;
605
606 private:
607 /** The activity recorder; used to tell if the CPU has any
608 * activity remaining or if it can go to idle and deschedule
609 * itself.
610 */
611 ActivityRecorder activityRec;
612
613 public:
614 /** Records that there was time buffer activity this cycle. */
615 void activityThisCycle() { activityRec.activity(); }
616
617 /** Changes a stage's status to active within the activity recorder. */
618 void activateStage(const StageIdx idx)
619 { activityRec.activateStage(idx); }
620
621 /** Changes a stage's status to inactive within the activity recorder. */
622 void deactivateStage(const StageIdx idx)
623 { activityRec.deactivateStage(idx); }
624
625 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
626 void wakeCPU();
627
628#if FULL_SYSTEM
629 virtual void wakeup();
630#endif
631
632 /** Gets a free thread id. Use if thread ids change across system. */
633 ThreadID getFreeTid();
634
635 public:
636 /** Returns a pointer to a thread context. */
637 ThreadContext *
638 tcBase(ThreadID tid)
639 {
640 return thread[tid]->getTC();
641 }
642
643 /** The global sequence number counter. */
644 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
645
646#if USE_CHECKER
647 /** Pointer to the checker, which can dynamically verify
648 * instruction results at run time. This can be set to NULL if it
649 * is not being used.
650 */
651 Checker<DynInstPtr> *checker;
652#endif
653
654#if FULL_SYSTEM
655 /** Pointer to the system. */
656 System *system;
657#endif
658
659 /** Event to call process() on once draining has completed. */
660 Event *drainEvent;
661
662 /** Counter of how many stages have completed draining. */
663 int drainCount;
664
665 /** Pointers to all of the threads in the CPU. */
666 std::vector<Thread *> thread;
667
668 /** Whether or not the CPU should defer its registration. */
669 bool deferRegistration;
670
671 /** Is there a context switch pending? */
672 bool contextSwitch;
673
674 /** Threads Scheduled to Enter CPU */
675 std::list<int> cpuWaitList;
676
677 /** The cycle that the CPU was last running, used for statistics. */
678 Tick lastRunningCycle;
679
680 /** The cycle that the CPU was last activated by a new thread*/
681 Tick lastActivatedCycle;
682
683 /** Mapping for system thread id to cpu id */
684 std::map<ThreadID, unsigned> threadMap;
685
686 /** Available thread ids in the cpu*/
687 std::vector<ThreadID> tids;
688
689 /** CPU read function, forwards read to LSQ. */
690 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
691 uint8_t *data, int load_idx)
692 {
693 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
694 data, load_idx);
695 }
696
697 /** CPU write function, forwards write to LSQ. */
698 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
699 uint8_t *data, int store_idx)
700 {
701 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
702 data, store_idx);
703 }
704
705 /** Get the dcache port (used to find block size for translations). */
706 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
707
708 Addr lockAddr;
709
710 /** Temporary fix for the lock flag, works in the UP case. */
711 bool lockFlag;
712
713 /** Stat for total number of times the CPU is descheduled. */
714 Stats::Scalar timesIdled;
715 /** Stat for total number of cycles the CPU spends descheduled. */
716 Stats::Scalar idleCycles;
717 /** Stat for the number of committed instructions per thread. */
718 Stats::Vector committedInsts;
719 /** Stat for the total number of committed instructions. */
720 Stats::Scalar totalCommittedInsts;
721 /** Stat for the CPI per thread. */
722 Stats::Formula cpi;
723 /** Stat for the total CPI. */
724 Stats::Formula totalCpi;
725 /** Stat for the IPC per thread. */
726 Stats::Formula ipc;
727 /** Stat for the total IPC. */
728 Stats::Formula totalIpc;
| 32 */
33
34#ifndef __CPU_O3_CPU_HH__
35#define __CPU_O3_CPU_HH__
36
37#include <iostream>
38#include <list>
39#include <queue>
40#include <set>
41#include <vector>
42
43#include "arch/types.hh"
44#include "base/statistics.hh"
45#include "cpu/timebuf.hh"
46#include "config/full_system.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
49#include "cpu/activity.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/o3/comm.hh"
53#include "cpu/o3/cpu_policy.hh"
54#include "cpu/o3/scoreboard.hh"
55#include "cpu/o3/thread_state.hh"
56//#include "cpu/o3/thread_context.hh"
57#include "sim/process.hh"
58
59#include "params/DerivO3CPU.hh"
60
61template <class>
62class Checker;
63class ThreadContext;
64template <class>
65class O3ThreadContext;
66
67class Checkpoint;
68class MemObject;
69class Process;
70
71class BaseCPUParams;
72
73class BaseO3CPU : public BaseCPU
74{
75 //Stuff that's pretty ISA independent will go here.
76 public:
77 BaseO3CPU(BaseCPUParams *params);
78
79 void regStats();
80};
81
82/**
83 * FullO3CPU class, has each of the stages (fetch through commit)
84 * within it, as well as all of the time buffers between stages. The
85 * tick() function for the CPU is defined here.
86 */
87template <class Impl>
88class FullO3CPU : public BaseO3CPU
89{
90 public:
91 // Typedefs from the Impl here.
92 typedef typename Impl::CPUPol CPUPolicy;
93 typedef typename Impl::DynInstPtr DynInstPtr;
94 typedef typename Impl::O3CPU O3CPU;
95
96 typedef O3ThreadState<Impl> ImplState;
97 typedef O3ThreadState<Impl> Thread;
98
99 typedef typename std::list<DynInstPtr>::iterator ListIt;
100
101 friend class O3ThreadContext<Impl>;
102
103 public:
104 enum Status {
105 Running,
106 Idle,
107 Halted,
108 Blocked,
109 SwitchedOut
110 };
111
112 TheISA::TLB * itb;
113 TheISA::TLB * dtb;
114
115 /** Overall CPU status. */
116 Status _status;
117
118 /** Per-thread status in CPU, used for SMT. */
119 Status _threadStatus[Impl::MaxThreads];
120
121 private:
122 class TickEvent : public Event
123 {
124 private:
125 /** Pointer to the CPU. */
126 FullO3CPU<Impl> *cpu;
127
128 public:
129 /** Constructs a tick event. */
130 TickEvent(FullO3CPU<Impl> *c);
131
132 /** Processes a tick event, calling tick() on the CPU. */
133 void process();
134 /** Returns the description of the tick event. */
135 const char *description() const;
136 };
137
138 /** The tick event used for scheduling CPU ticks. */
139 TickEvent tickEvent;
140
141 /** Schedule tick event, regardless of its current state. */
142 void scheduleTickEvent(int delay)
143 {
144 if (tickEvent.squashed())
145 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
146 else if (!tickEvent.scheduled())
147 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
148 }
149
150 /** Unschedule tick event, regardless of its current state. */
151 void unscheduleTickEvent()
152 {
153 if (tickEvent.scheduled())
154 tickEvent.squash();
155 }
156
157 class ActivateThreadEvent : public Event
158 {
159 private:
160 /** Number of Thread to Activate */
161 ThreadID tid;
162
163 /** Pointer to the CPU. */
164 FullO3CPU<Impl> *cpu;
165
166 public:
167 /** Constructs the event. */
168 ActivateThreadEvent();
169
170 /** Initialize Event */
171 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
172
173 /** Processes the event, calling activateThread() on the CPU. */
174 void process();
175
176 /** Returns the description of the event. */
177 const char *description() const;
178 };
179
180 /** Schedule thread to activate , regardless of its current state. */
181 void
182 scheduleActivateThreadEvent(ThreadID tid, int delay)
183 {
184 // Schedule thread to activate, regardless of its current state.
185 if (activateThreadEvent[tid].squashed())
186 reschedule(activateThreadEvent[tid],
187 nextCycle(curTick() + ticks(delay)));
188 else if (!activateThreadEvent[tid].scheduled())
189 schedule(activateThreadEvent[tid],
190 nextCycle(curTick() + ticks(delay)));
191 }
192
193 /** Unschedule actiavte thread event, regardless of its current state. */
194 void
195 unscheduleActivateThreadEvent(ThreadID tid)
196 {
197 if (activateThreadEvent[tid].scheduled())
198 activateThreadEvent[tid].squash();
199 }
200
201 /** The tick event used for scheduling CPU ticks. */
202 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
203
204 class DeallocateContextEvent : public Event
205 {
206 private:
207 /** Number of Thread to deactivate */
208 ThreadID tid;
209
210 /** Should the thread be removed from the CPU? */
211 bool remove;
212
213 /** Pointer to the CPU. */
214 FullO3CPU<Impl> *cpu;
215
216 public:
217 /** Constructs the event. */
218 DeallocateContextEvent();
219
220 /** Initialize Event */
221 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
222
223 /** Processes the event, calling activateThread() on the CPU. */
224 void process();
225
226 /** Sets whether the thread should also be removed from the CPU. */
227 void setRemove(bool _remove) { remove = _remove; }
228
229 /** Returns the description of the event. */
230 const char *description() const;
231 };
232
233 /** Schedule cpu to deallocate thread context.*/
234 void
235 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
236 {
237 // Schedule thread to activate, regardless of its current state.
238 if (deallocateContextEvent[tid].squashed())
239 reschedule(deallocateContextEvent[tid],
240 nextCycle(curTick() + ticks(delay)));
241 else if (!deallocateContextEvent[tid].scheduled())
242 schedule(deallocateContextEvent[tid],
243 nextCycle(curTick() + ticks(delay)));
244 }
245
246 /** Unschedule thread deallocation in CPU */
247 void
248 unscheduleDeallocateContextEvent(ThreadID tid)
249 {
250 if (deallocateContextEvent[tid].scheduled())
251 deallocateContextEvent[tid].squash();
252 }
253
254 /** The tick event used for scheduling CPU ticks. */
255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
256
257 public:
258 /** Constructs a CPU with the given parameters. */
259 FullO3CPU(DerivO3CPUParams *params);
260 /** Destructor. */
261 ~FullO3CPU();
262
263 /** Registers statistics. */
264 void regStats();
265
266 void demapPage(Addr vaddr, uint64_t asn)
267 {
268 this->itb->demapPage(vaddr, asn);
269 this->dtb->demapPage(vaddr, asn);
270 }
271
272 void demapInstPage(Addr vaddr, uint64_t asn)
273 {
274 this->itb->demapPage(vaddr, asn);
275 }
276
277 void demapDataPage(Addr vaddr, uint64_t asn)
278 {
279 this->dtb->demapPage(vaddr, asn);
280 }
281
282 /** Returns a specific port. */
283 Port *getPort(const std::string &if_name, int idx);
284
285 /** Ticks CPU, calling tick() on each stage, and checking the overall
286 * activity to see if the CPU should deschedule itself.
287 */
288 void tick();
289
290 /** Initialize the CPU */
291 void init();
292
293 /** Returns the Number of Active Threads in the CPU */
294 int numActiveThreads()
295 { return activeThreads.size(); }
296
297 /** Add Thread to Active Threads List */
298 void activateThread(ThreadID tid);
299
300 /** Remove Thread from Active Threads List */
301 void deactivateThread(ThreadID tid);
302
303 /** Setup CPU to insert a thread's context */
304 void insertThread(ThreadID tid);
305
306 /** Remove all of a thread's context from CPU */
307 void removeThread(ThreadID tid);
308
309 /** Count the Total Instructions Committed in the CPU. */
310 virtual Counter totalInstructions() const;
311
312 /** Add Thread to Active Threads List. */
313 void activateContext(ThreadID tid, int delay);
314
315 /** Remove Thread from Active Threads List */
316 void suspendContext(ThreadID tid);
317
318 /** Remove Thread from Active Threads List &&
319 * Possibly Remove Thread Context from CPU.
320 */
321 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
322
323 /** Remove Thread from Active Threads List &&
324 * Remove Thread Context from CPU.
325 */
326 void haltContext(ThreadID tid);
327
328 /** Activate a Thread When CPU Resources are Available. */
329 void activateWhenReady(ThreadID tid);
330
331 /** Add or Remove a Thread Context in the CPU. */
332 void doContextSwitch();
333
334 /** Update The Order In Which We Process Threads. */
335 void updateThreadPriority();
336
337 /** Serialize state. */
338 virtual void serialize(std::ostream &os);
339
340 /** Unserialize from a checkpoint. */
341 virtual void unserialize(Checkpoint *cp, const std::string §ion);
342
343 public:
344#if !FULL_SYSTEM
345 /** Executes a syscall.
346 * @todo: Determine if this needs to be virtual.
347 */
348 void syscall(int64_t callnum, ThreadID tid);
349#endif
350
351 /** Starts draining the CPU's pipeline of all instructions in
352 * order to stop all memory accesses. */
353 virtual unsigned int drain(Event *drain_event);
354
355 /** Resumes execution after a drain. */
356 virtual void resume();
357
358 /** Signals to this CPU that a stage has completed switching out. */
359 void signalDrained();
360
361 /** Switches out this CPU. */
362 virtual void switchOut();
363
364 /** Takes over from another CPU. */
365 virtual void takeOverFrom(BaseCPU *oldCPU);
366
367 /** Get the current instruction sequence number, and increment it. */
368 InstSeqNum getAndIncrementInstSeq()
369 { return globalSeqNum++; }
370
371 /** Traps to handle given fault. */
372 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
373
374#if FULL_SYSTEM
375 /** HW return from error interrupt. */
376 Fault hwrei(ThreadID tid);
377
378 bool simPalCheck(int palFunc, ThreadID tid);
379
380 /** Returns the Fault for any valid interrupt. */
381 Fault getInterrupts();
382
383 /** Processes any an interrupt fault. */
384 void processInterrupts(Fault interrupt);
385
386 /** Halts the CPU. */
387 void halt() { panic("Halt not implemented!\n"); }
388
389 /** Update the Virt and Phys ports of all ThreadContexts to
390 * reflect change in memory connections. */
391 void updateMemPorts();
392
393 /** Check if this address is a valid instruction address. */
394 bool validInstAddr(Addr addr) { return true; }
395
396 /** Check if this address is a valid data address. */
397 bool validDataAddr(Addr addr) { return true; }
398#endif
399
400 /** Register accessors. Index refers to the physical register index. */
401
402 /** Reads a miscellaneous register. */
403 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
404
405 /** Reads a misc. register, including any side effects the read
406 * might have as defined by the architecture.
407 */
408 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
409
410 /** Sets a miscellaneous register. */
411 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
412 ThreadID tid);
413
414 /** Sets a misc. register, including any side effects the write
415 * might have as defined by the architecture.
416 */
417 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
418 ThreadID tid);
419
420 uint64_t readIntReg(int reg_idx);
421
422 TheISA::FloatReg readFloatReg(int reg_idx);
423
424 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
425
426 void setIntReg(int reg_idx, uint64_t val);
427
428 void setFloatReg(int reg_idx, TheISA::FloatReg val);
429
430 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
431
432 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
433
434 float readArchFloatReg(int reg_idx, ThreadID tid);
435
436 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
437
438 /** Architectural register accessors. Looks up in the commit
439 * rename table to obtain the true physical index of the
440 * architected register first, then accesses that physical
441 * register.
442 */
443 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
444
445 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
446
447 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
448
449 /** Sets the commit PC state of a specific thread. */
450 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
451
452 /** Reads the commit PC state of a specific thread. */
453 TheISA::PCState pcState(ThreadID tid);
454
455 /** Reads the commit PC of a specific thread. */
456 Addr instAddr(ThreadID tid);
457
458 /** Reads the commit micro PC of a specific thread. */
459 MicroPC microPC(ThreadID tid);
460
461 /** Reads the next PC of a specific thread. */
462 Addr nextInstAddr(ThreadID tid);
463
464 /** Initiates a squash of all in-flight instructions for a given
465 * thread. The source of the squash is an external update of
466 * state through the TC.
467 */
468 void squashFromTC(ThreadID tid);
469
470 /** Function to add instruction onto the head of the list of the
471 * instructions. Used when new instructions are fetched.
472 */
473 ListIt addInst(DynInstPtr &inst);
474
475 /** Function to tell the CPU that an instruction has completed. */
476 void instDone(ThreadID tid);
477
478 /** Add Instructions to the CPU Remove List*/
479 void addToRemoveList(DynInstPtr &inst);
480
481 /** Remove an instruction from the front end of the list. There's
482 * no restriction on location of the instruction.
483 */
484 void removeFrontInst(DynInstPtr &inst);
485
486 /** Remove all instructions that are not currently in the ROB.
487 * There's also an option to not squash delay slot instructions.*/
488 void removeInstsNotInROB(ThreadID tid);
489
490 /** Remove all instructions younger than the given sequence number. */
491 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
492
493 /** Removes the instruction pointed to by the iterator. */
494 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
495
496 /** Cleans up all instructions on the remove list. */
497 void cleanUpRemovedInsts();
498
499 /** Debug function to print all instructions on the list. */
500 void dumpInsts();
501
502 public:
503#ifndef NDEBUG
504 /** Count of total number of dynamic instructions in flight. */
505 int instcount;
506#endif
507
508 /** List of all the instructions in flight. */
509 std::list<DynInstPtr> instList;
510
511 /** List of all the instructions that will be removed at the end of this
512 * cycle.
513 */
514 std::queue<ListIt> removeList;
515
516#ifdef DEBUG
517 /** Debug structure to keep track of the sequence numbers still in
518 * flight.
519 */
520 std::set<InstSeqNum> snList;
521#endif
522
523 /** Records if instructions need to be removed this cycle due to
524 * being retired or squashed.
525 */
526 bool removeInstsThisCycle;
527
528 protected:
529 /** The fetch stage. */
530 typename CPUPolicy::Fetch fetch;
531
532 /** The decode stage. */
533 typename CPUPolicy::Decode decode;
534
535 /** The dispatch stage. */
536 typename CPUPolicy::Rename rename;
537
538 /** The issue/execute/writeback stages. */
539 typename CPUPolicy::IEW iew;
540
541 /** The commit stage. */
542 typename CPUPolicy::Commit commit;
543
544 /** The register file. */
545 typename CPUPolicy::RegFile regFile;
546
547 /** The free list. */
548 typename CPUPolicy::FreeList freeList;
549
550 /** The rename map. */
551 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
552
553 /** The commit rename map. */
554 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
555
556 /** The re-order buffer. */
557 typename CPUPolicy::ROB rob;
558
559 /** Active Threads List */
560 std::list<ThreadID> activeThreads;
561
562 /** Integer Register Scoreboard */
563 Scoreboard scoreboard;
564
565 TheISA::ISA isa[Impl::MaxThreads];
566
567 public:
568 /** Enum to give each stage a specific index, so when calling
569 * activateStage() or deactivateStage(), they can specify which stage
570 * is being activated/deactivated.
571 */
572 enum StageIdx {
573 FetchIdx,
574 DecodeIdx,
575 RenameIdx,
576 IEWIdx,
577 CommitIdx,
578 NumStages };
579
580 /** Typedefs from the Impl to get the structs that each of the
581 * time buffers should use.
582 */
583 typedef typename CPUPolicy::TimeStruct TimeStruct;
584
585 typedef typename CPUPolicy::FetchStruct FetchStruct;
586
587 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
588
589 typedef typename CPUPolicy::RenameStruct RenameStruct;
590
591 typedef typename CPUPolicy::IEWStruct IEWStruct;
592
593 /** The main time buffer to do backwards communication. */
594 TimeBuffer<TimeStruct> timeBuffer;
595
596 /** The fetch stage's instruction queue. */
597 TimeBuffer<FetchStruct> fetchQueue;
598
599 /** The decode stage's instruction queue. */
600 TimeBuffer<DecodeStruct> decodeQueue;
601
602 /** The rename stage's instruction queue. */
603 TimeBuffer<RenameStruct> renameQueue;
604
605 /** The IEW stage's instruction queue. */
606 TimeBuffer<IEWStruct> iewQueue;
607
608 private:
609 /** The activity recorder; used to tell if the CPU has any
610 * activity remaining or if it can go to idle and deschedule
611 * itself.
612 */
613 ActivityRecorder activityRec;
614
615 public:
616 /** Records that there was time buffer activity this cycle. */
617 void activityThisCycle() { activityRec.activity(); }
618
619 /** Changes a stage's status to active within the activity recorder. */
620 void activateStage(const StageIdx idx)
621 { activityRec.activateStage(idx); }
622
623 /** Changes a stage's status to inactive within the activity recorder. */
624 void deactivateStage(const StageIdx idx)
625 { activityRec.deactivateStage(idx); }
626
627 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
628 void wakeCPU();
629
630#if FULL_SYSTEM
631 virtual void wakeup();
632#endif
633
634 /** Gets a free thread id. Use if thread ids change across system. */
635 ThreadID getFreeTid();
636
637 public:
638 /** Returns a pointer to a thread context. */
639 ThreadContext *
640 tcBase(ThreadID tid)
641 {
642 return thread[tid]->getTC();
643 }
644
645 /** The global sequence number counter. */
646 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
647
648#if USE_CHECKER
649 /** Pointer to the checker, which can dynamically verify
650 * instruction results at run time. This can be set to NULL if it
651 * is not being used.
652 */
653 Checker<DynInstPtr> *checker;
654#endif
655
656#if FULL_SYSTEM
657 /** Pointer to the system. */
658 System *system;
659#endif
660
661 /** Event to call process() on once draining has completed. */
662 Event *drainEvent;
663
664 /** Counter of how many stages have completed draining. */
665 int drainCount;
666
667 /** Pointers to all of the threads in the CPU. */
668 std::vector<Thread *> thread;
669
670 /** Whether or not the CPU should defer its registration. */
671 bool deferRegistration;
672
673 /** Is there a context switch pending? */
674 bool contextSwitch;
675
676 /** Threads Scheduled to Enter CPU */
677 std::list<int> cpuWaitList;
678
679 /** The cycle that the CPU was last running, used for statistics. */
680 Tick lastRunningCycle;
681
682 /** The cycle that the CPU was last activated by a new thread*/
683 Tick lastActivatedCycle;
684
685 /** Mapping for system thread id to cpu id */
686 std::map<ThreadID, unsigned> threadMap;
687
688 /** Available thread ids in the cpu*/
689 std::vector<ThreadID> tids;
690
691 /** CPU read function, forwards read to LSQ. */
692 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
693 uint8_t *data, int load_idx)
694 {
695 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
696 data, load_idx);
697 }
698
699 /** CPU write function, forwards write to LSQ. */
700 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
701 uint8_t *data, int store_idx)
702 {
703 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
704 data, store_idx);
705 }
706
707 /** Get the dcache port (used to find block size for translations). */
708 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
709
710 Addr lockAddr;
711
712 /** Temporary fix for the lock flag, works in the UP case. */
713 bool lockFlag;
714
715 /** Stat for total number of times the CPU is descheduled. */
716 Stats::Scalar timesIdled;
717 /** Stat for total number of cycles the CPU spends descheduled. */
718 Stats::Scalar idleCycles;
719 /** Stat for the number of committed instructions per thread. */
720 Stats::Vector committedInsts;
721 /** Stat for the total number of committed instructions. */
722 Stats::Scalar totalCommittedInsts;
723 /** Stat for the CPI per thread. */
724 Stats::Formula cpi;
725 /** Stat for the total CPI. */
726 Stats::Formula totalCpi;
727 /** Stat for the IPC per thread. */
728 Stats::Formula ipc;
729 /** Stat for the total IPC. */
730 Stats::Formula totalIpc;
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