cpu.hh (5807:57f9f8b8e62f) cpu.hh (5890:bdef71accd68)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "config/use_checker.hh"
46#include "cpu/activity.hh"
47#include "cpu/base.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/o3/comm.hh"
50#include "cpu/o3/cpu_policy.hh"
51#include "cpu/o3/scoreboard.hh"
52#include "cpu/o3/thread_state.hh"
53//#include "cpu/o3/thread_context.hh"
54#include "sim/process.hh"
55
56#include "params/DerivO3CPU.hh"
57
58template <class>
59class Checker;
60class ThreadContext;
61template <class>
62class O3ThreadContext;
63
64class Checkpoint;
65class MemObject;
66class Process;
67
68class BaseCPUParams;
69
70class BaseO3CPU : public BaseCPU
71{
72 //Stuff that's pretty ISA independent will go here.
73 public:
74 BaseO3CPU(BaseCPUParams *params);
75
76 void regStats();
77};
78
79/**
80 * FullO3CPU class, has each of the stages (fetch through commit)
81 * within it, as well as all of the time buffers between stages. The
82 * tick() function for the CPU is defined here.
83 */
84template <class Impl>
85class FullO3CPU : public BaseO3CPU
86{
87 public:
88 // Typedefs from the Impl here.
89 typedef typename Impl::CPUPol CPUPolicy;
90 typedef typename Impl::DynInstPtr DynInstPtr;
91 typedef typename Impl::O3CPU O3CPU;
92
93 typedef O3ThreadState<Impl> ImplState;
94 typedef O3ThreadState<Impl> Thread;
95
96 typedef typename std::list<DynInstPtr>::iterator ListIt;
97
98 friend class O3ThreadContext<Impl>;
99
100 public:
101 enum Status {
102 Running,
103 Idle,
104 Halted,
105 Blocked,
106 SwitchedOut
107 };
108
109 TheISA::ITB * itb;
110 TheISA::DTB * dtb;
111
112 /** Overall CPU status. */
113 Status _status;
114
115 /** Per-thread status in CPU, used for SMT. */
116 Status _threadStatus[Impl::MaxThreads];
117
118 private:
119 class TickEvent : public Event
120 {
121 private:
122 /** Pointer to the CPU. */
123 FullO3CPU<Impl> *cpu;
124
125 public:
126 /** Constructs a tick event. */
127 TickEvent(FullO3CPU<Impl> *c);
128
129 /** Processes a tick event, calling tick() on the CPU. */
130 void process();
131 /** Returns the description of the tick event. */
132 const char *description() const;
133 };
134
135 /** The tick event used for scheduling CPU ticks. */
136 TickEvent tickEvent;
137
138 /** Schedule tick event, regardless of its current state. */
139 void scheduleTickEvent(int delay)
140 {
141 if (tickEvent.squashed())
142 reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
143 else if (!tickEvent.scheduled())
144 schedule(tickEvent, nextCycle(curTick + ticks(delay)));
145 }
146
147 /** Unschedule tick event, regardless of its current state. */
148 void unscheduleTickEvent()
149 {
150 if (tickEvent.scheduled())
151 tickEvent.squash();
152 }
153
154 class ActivateThreadEvent : public Event
155 {
156 private:
157 /** Number of Thread to Activate */
158 int tid;
159
160 /** Pointer to the CPU. */
161 FullO3CPU<Impl> *cpu;
162
163 public:
164 /** Constructs the event. */
165 ActivateThreadEvent();
166
167 /** Initialize Event */
168 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
169
170 /** Processes the event, calling activateThread() on the CPU. */
171 void process();
172
173 /** Returns the description of the event. */
174 const char *description() const;
175 };
176
177 /** Schedule thread to activate , regardless of its current state. */
178 void scheduleActivateThreadEvent(int tid, int delay)
179 {
180 // Schedule thread to activate, regardless of its current state.
181 if (activateThreadEvent[tid].squashed())
182 reschedule(activateThreadEvent[tid],
183 nextCycle(curTick + ticks(delay)));
184 else if (!activateThreadEvent[tid].scheduled())
185 schedule(activateThreadEvent[tid],
186 nextCycle(curTick + ticks(delay)));
187 }
188
189 /** Unschedule actiavte thread event, regardless of its current state. */
190 void unscheduleActivateThreadEvent(int tid)
191 {
192 if (activateThreadEvent[tid].scheduled())
193 activateThreadEvent[tid].squash();
194 }
195
196#if !FULL_SYSTEM
197 TheISA::IntReg getSyscallArg(int i, int tid);
198
199 /** Used to shift args for indirect syscall. */
200 void setSyscallArg(int i, TheISA::IntReg val, int tid);
201#endif
202
203 /** The tick event used for scheduling CPU ticks. */
204 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
205
206 class DeallocateContextEvent : public Event
207 {
208 private:
209 /** Number of Thread to deactivate */
210 int tid;
211
212 /** Should the thread be removed from the CPU? */
213 bool remove;
214
215 /** Pointer to the CPU. */
216 FullO3CPU<Impl> *cpu;
217
218 public:
219 /** Constructs the event. */
220 DeallocateContextEvent();
221
222 /** Initialize Event */
223 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
224
225 /** Processes the event, calling activateThread() on the CPU. */
226 void process();
227
228 /** Sets whether the thread should also be removed from the CPU. */
229 void setRemove(bool _remove) { remove = _remove; }
230
231 /** Returns the description of the event. */
232 const char *description() const;
233 };
234
235 /** Schedule cpu to deallocate thread context.*/
236 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
237 {
238 // Schedule thread to activate, regardless of its current state.
239 if (deallocateContextEvent[tid].squashed())
240 reschedule(deallocateContextEvent[tid],
241 nextCycle(curTick + ticks(delay)));
242 else if (!deallocateContextEvent[tid].scheduled())
243 schedule(deallocateContextEvent[tid],
244 nextCycle(curTick + ticks(delay)));
245 }
246
247 /** Unschedule thread deallocation in CPU */
248 void unscheduleDeallocateContextEvent(int tid)
249 {
250 if (deallocateContextEvent[tid].scheduled())
251 deallocateContextEvent[tid].squash();
252 }
253
254 /** The tick event used for scheduling CPU ticks. */
255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
256
257 public:
258 /** Constructs a CPU with the given parameters. */
259 FullO3CPU(DerivO3CPUParams *params);
260 /** Destructor. */
261 ~FullO3CPU();
262
263 /** Registers statistics. */
264 void regStats();
265
266 void demapPage(Addr vaddr, uint64_t asn)
267 {
268 this->itb->demapPage(vaddr, asn);
269 this->dtb->demapPage(vaddr, asn);
270 }
271
272 void demapInstPage(Addr vaddr, uint64_t asn)
273 {
274 this->itb->demapPage(vaddr, asn);
275 }
276
277 void demapDataPage(Addr vaddr, uint64_t asn)
278 {
279 this->dtb->demapPage(vaddr, asn);
280 }
281
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "config/use_checker.hh"
46#include "cpu/activity.hh"
47#include "cpu/base.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/o3/comm.hh"
50#include "cpu/o3/cpu_policy.hh"
51#include "cpu/o3/scoreboard.hh"
52#include "cpu/o3/thread_state.hh"
53//#include "cpu/o3/thread_context.hh"
54#include "sim/process.hh"
55
56#include "params/DerivO3CPU.hh"
57
58template <class>
59class Checker;
60class ThreadContext;
61template <class>
62class O3ThreadContext;
63
64class Checkpoint;
65class MemObject;
66class Process;
67
68class BaseCPUParams;
69
70class BaseO3CPU : public BaseCPU
71{
72 //Stuff that's pretty ISA independent will go here.
73 public:
74 BaseO3CPU(BaseCPUParams *params);
75
76 void regStats();
77};
78
79/**
80 * FullO3CPU class, has each of the stages (fetch through commit)
81 * within it, as well as all of the time buffers between stages. The
82 * tick() function for the CPU is defined here.
83 */
84template <class Impl>
85class FullO3CPU : public BaseO3CPU
86{
87 public:
88 // Typedefs from the Impl here.
89 typedef typename Impl::CPUPol CPUPolicy;
90 typedef typename Impl::DynInstPtr DynInstPtr;
91 typedef typename Impl::O3CPU O3CPU;
92
93 typedef O3ThreadState<Impl> ImplState;
94 typedef O3ThreadState<Impl> Thread;
95
96 typedef typename std::list<DynInstPtr>::iterator ListIt;
97
98 friend class O3ThreadContext<Impl>;
99
100 public:
101 enum Status {
102 Running,
103 Idle,
104 Halted,
105 Blocked,
106 SwitchedOut
107 };
108
109 TheISA::ITB * itb;
110 TheISA::DTB * dtb;
111
112 /** Overall CPU status. */
113 Status _status;
114
115 /** Per-thread status in CPU, used for SMT. */
116 Status _threadStatus[Impl::MaxThreads];
117
118 private:
119 class TickEvent : public Event
120 {
121 private:
122 /** Pointer to the CPU. */
123 FullO3CPU<Impl> *cpu;
124
125 public:
126 /** Constructs a tick event. */
127 TickEvent(FullO3CPU<Impl> *c);
128
129 /** Processes a tick event, calling tick() on the CPU. */
130 void process();
131 /** Returns the description of the tick event. */
132 const char *description() const;
133 };
134
135 /** The tick event used for scheduling CPU ticks. */
136 TickEvent tickEvent;
137
138 /** Schedule tick event, regardless of its current state. */
139 void scheduleTickEvent(int delay)
140 {
141 if (tickEvent.squashed())
142 reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
143 else if (!tickEvent.scheduled())
144 schedule(tickEvent, nextCycle(curTick + ticks(delay)));
145 }
146
147 /** Unschedule tick event, regardless of its current state. */
148 void unscheduleTickEvent()
149 {
150 if (tickEvent.scheduled())
151 tickEvent.squash();
152 }
153
154 class ActivateThreadEvent : public Event
155 {
156 private:
157 /** Number of Thread to Activate */
158 int tid;
159
160 /** Pointer to the CPU. */
161 FullO3CPU<Impl> *cpu;
162
163 public:
164 /** Constructs the event. */
165 ActivateThreadEvent();
166
167 /** Initialize Event */
168 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
169
170 /** Processes the event, calling activateThread() on the CPU. */
171 void process();
172
173 /** Returns the description of the event. */
174 const char *description() const;
175 };
176
177 /** Schedule thread to activate , regardless of its current state. */
178 void scheduleActivateThreadEvent(int tid, int delay)
179 {
180 // Schedule thread to activate, regardless of its current state.
181 if (activateThreadEvent[tid].squashed())
182 reschedule(activateThreadEvent[tid],
183 nextCycle(curTick + ticks(delay)));
184 else if (!activateThreadEvent[tid].scheduled())
185 schedule(activateThreadEvent[tid],
186 nextCycle(curTick + ticks(delay)));
187 }
188
189 /** Unschedule actiavte thread event, regardless of its current state. */
190 void unscheduleActivateThreadEvent(int tid)
191 {
192 if (activateThreadEvent[tid].scheduled())
193 activateThreadEvent[tid].squash();
194 }
195
196#if !FULL_SYSTEM
197 TheISA::IntReg getSyscallArg(int i, int tid);
198
199 /** Used to shift args for indirect syscall. */
200 void setSyscallArg(int i, TheISA::IntReg val, int tid);
201#endif
202
203 /** The tick event used for scheduling CPU ticks. */
204 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
205
206 class DeallocateContextEvent : public Event
207 {
208 private:
209 /** Number of Thread to deactivate */
210 int tid;
211
212 /** Should the thread be removed from the CPU? */
213 bool remove;
214
215 /** Pointer to the CPU. */
216 FullO3CPU<Impl> *cpu;
217
218 public:
219 /** Constructs the event. */
220 DeallocateContextEvent();
221
222 /** Initialize Event */
223 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
224
225 /** Processes the event, calling activateThread() on the CPU. */
226 void process();
227
228 /** Sets whether the thread should also be removed from the CPU. */
229 void setRemove(bool _remove) { remove = _remove; }
230
231 /** Returns the description of the event. */
232 const char *description() const;
233 };
234
235 /** Schedule cpu to deallocate thread context.*/
236 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
237 {
238 // Schedule thread to activate, regardless of its current state.
239 if (deallocateContextEvent[tid].squashed())
240 reschedule(deallocateContextEvent[tid],
241 nextCycle(curTick + ticks(delay)));
242 else if (!deallocateContextEvent[tid].scheduled())
243 schedule(deallocateContextEvent[tid],
244 nextCycle(curTick + ticks(delay)));
245 }
246
247 /** Unschedule thread deallocation in CPU */
248 void unscheduleDeallocateContextEvent(int tid)
249 {
250 if (deallocateContextEvent[tid].scheduled())
251 deallocateContextEvent[tid].squash();
252 }
253
254 /** The tick event used for scheduling CPU ticks. */
255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
256
257 public:
258 /** Constructs a CPU with the given parameters. */
259 FullO3CPU(DerivO3CPUParams *params);
260 /** Destructor. */
261 ~FullO3CPU();
262
263 /** Registers statistics. */
264 void regStats();
265
266 void demapPage(Addr vaddr, uint64_t asn)
267 {
268 this->itb->demapPage(vaddr, asn);
269 this->dtb->demapPage(vaddr, asn);
270 }
271
272 void demapInstPage(Addr vaddr, uint64_t asn)
273 {
274 this->itb->demapPage(vaddr, asn);
275 }
276
277 void demapDataPage(Addr vaddr, uint64_t asn)
278 {
279 this->dtb->demapPage(vaddr, asn);
280 }
281
282 /** Translates instruction requestion. */
283 Fault translateInstReq(RequestPtr &req, Thread *thread)
284 {
285 return this->itb->translate(req, thread->getTC());
286 }
287
288 /** Translates data read request. */
289 Fault translateDataReadReq(RequestPtr &req, Thread *thread)
290 {
291 return this->dtb->translate(req, thread->getTC(), false);
292 }
293
294 /** Translates data write request. */
295 Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
296 {
297 return this->dtb->translate(req, thread->getTC(), true);
298 }
299
300 /** Returns a specific port. */
301 Port *getPort(const std::string &if_name, int idx);
302
303 /** Ticks CPU, calling tick() on each stage, and checking the overall
304 * activity to see if the CPU should deschedule itself.
305 */
306 void tick();
307
308 /** Initialize the CPU */
309 void init();
310
311 /** Returns the Number of Active Threads in the CPU */
312 int numActiveThreads()
313 { return activeThreads.size(); }
314
315 /** Add Thread to Active Threads List */
316 void activateThread(unsigned tid);
317
318 /** Remove Thread from Active Threads List */
319 void deactivateThread(unsigned tid);
320
321 /** Setup CPU to insert a thread's context */
322 void insertThread(unsigned tid);
323
324 /** Remove all of a thread's context from CPU */
325 void removeThread(unsigned tid);
326
327 /** Count the Total Instructions Committed in the CPU. */
328 virtual Counter totalInstructions() const
329 {
330 Counter total(0);
331
332 for (int i=0; i < thread.size(); i++)
333 total += thread[i]->numInst;
334
335 return total;
336 }
337
338 /** Add Thread to Active Threads List. */
339 void activateContext(int tid, int delay);
340
341 /** Remove Thread from Active Threads List */
342 void suspendContext(int tid);
343
344 /** Remove Thread from Active Threads List &&
345 * Possibly Remove Thread Context from CPU.
346 */
347 bool deallocateContext(int tid, bool remove, int delay = 1);
348
349 /** Remove Thread from Active Threads List &&
350 * Remove Thread Context from CPU.
351 */
352 void haltContext(int tid);
353
354 /** Activate a Thread When CPU Resources are Available. */
355 void activateWhenReady(int tid);
356
357 /** Add or Remove a Thread Context in the CPU. */
358 void doContextSwitch();
359
360 /** Update The Order In Which We Process Threads. */
361 void updateThreadPriority();
362
363 /** Serialize state. */
364 virtual void serialize(std::ostream &os);
365
366 /** Unserialize from a checkpoint. */
367 virtual void unserialize(Checkpoint *cp, const std::string &section);
368
369 public:
370#if !FULL_SYSTEM
371 /** Executes a syscall.
372 * @todo: Determine if this needs to be virtual.
373 */
374 void syscall(int64_t callnum, int tid);
375
376 /** Sets the return value of a syscall. */
377 void setSyscallReturn(SyscallReturn return_value, int tid);
378
379#endif
380
381 /** Starts draining the CPU's pipeline of all instructions in
382 * order to stop all memory accesses. */
383 virtual unsigned int drain(Event *drain_event);
384
385 /** Resumes execution after a drain. */
386 virtual void resume();
387
388 /** Signals to this CPU that a stage has completed switching out. */
389 void signalDrained();
390
391 /** Switches out this CPU. */
392 virtual void switchOut();
393
394 /** Takes over from another CPU. */
395 virtual void takeOverFrom(BaseCPU *oldCPU);
396
397 /** Get the current instruction sequence number, and increment it. */
398 InstSeqNum getAndIncrementInstSeq()
399 { return globalSeqNum++; }
400
401 /** Traps to handle given fault. */
402 void trap(Fault fault, unsigned tid);
403
404#if FULL_SYSTEM
405 /** HW return from error interrupt. */
406 Fault hwrei(unsigned tid);
407
408 bool simPalCheck(int palFunc, unsigned tid);
409
410 /** Returns the Fault for any valid interrupt. */
411 Fault getInterrupts();
412
413 /** Processes any an interrupt fault. */
414 void processInterrupts(Fault interrupt);
415
416 /** Halts the CPU. */
417 void halt() { panic("Halt not implemented!\n"); }
418
419 /** Update the Virt and Phys ports of all ThreadContexts to
420 * reflect change in memory connections. */
421 void updateMemPorts();
422
423 /** Check if this address is a valid instruction address. */
424 bool validInstAddr(Addr addr) { return true; }
425
426 /** Check if this address is a valid data address. */
427 bool validDataAddr(Addr addr) { return true; }
428
429 /** Get instruction asid. */
430 int getInstAsid(unsigned tid)
431 { return regFile.miscRegs[tid].getInstAsid(); }
432
433 /** Get data asid. */
434 int getDataAsid(unsigned tid)
435 { return regFile.miscRegs[tid].getDataAsid(); }
436#else
437 /** Get instruction asid. */
438 int getInstAsid(unsigned tid)
439 { return thread[tid]->getInstAsid(); }
440
441 /** Get data asid. */
442 int getDataAsid(unsigned tid)
443 { return thread[tid]->getDataAsid(); }
444
445#endif
446
447 /** Register accessors. Index refers to the physical register index. */
448
449 /** Reads a miscellaneous register. */
450 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
451
452 /** Reads a misc. register, including any side effects the read
453 * might have as defined by the architecture.
454 */
455 TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
456
457 /** Sets a miscellaneous register. */
458 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
459
460 /** Sets a misc. register, including any side effects the write
461 * might have as defined by the architecture.
462 */
463 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
464 unsigned tid);
465
466 uint64_t readIntReg(int reg_idx);
467
468 TheISA::FloatReg readFloatReg(int reg_idx);
469
470 TheISA::FloatReg readFloatReg(int reg_idx, int width);
471
472 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
473
474 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
475
476 void setIntReg(int reg_idx, uint64_t val);
477
478 void setFloatReg(int reg_idx, TheISA::FloatReg val);
479
480 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
481
482 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
483
484 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
485
486 uint64_t readArchIntReg(int reg_idx, unsigned tid);
487
488 float readArchFloatRegSingle(int reg_idx, unsigned tid);
489
490 double readArchFloatRegDouble(int reg_idx, unsigned tid);
491
492 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
493
494 /** Architectural register accessors. Looks up in the commit
495 * rename table to obtain the true physical index of the
496 * architected register first, then accesses that physical
497 * register.
498 */
499 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
500
501 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
502
503 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
504
505 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
506
507 /** Reads the commit PC of a specific thread. */
508 Addr readPC(unsigned tid);
509
510 /** Sets the commit PC of a specific thread. */
511 void setPC(Addr new_PC, unsigned tid);
512
513 /** Reads the commit micro PC of a specific thread. */
514 Addr readMicroPC(unsigned tid);
515
516 /** Sets the commmit micro PC of a specific thread. */
517 void setMicroPC(Addr new_microPC, unsigned tid);
518
519 /** Reads the next PC of a specific thread. */
520 Addr readNextPC(unsigned tid);
521
522 /** Sets the next PC of a specific thread. */
523 void setNextPC(Addr val, unsigned tid);
524
525 /** Reads the next NPC of a specific thread. */
526 Addr readNextNPC(unsigned tid);
527
528 /** Sets the next NPC of a specific thread. */
529 void setNextNPC(Addr val, unsigned tid);
530
531 /** Reads the commit next micro PC of a specific thread. */
532 Addr readNextMicroPC(unsigned tid);
533
534 /** Sets the commit next micro PC of a specific thread. */
535 void setNextMicroPC(Addr val, unsigned tid);
536
537 /** Initiates a squash of all in-flight instructions for a given
538 * thread. The source of the squash is an external update of
539 * state through the TC.
540 */
541 void squashFromTC(unsigned tid);
542
543 /** Function to add instruction onto the head of the list of the
544 * instructions. Used when new instructions are fetched.
545 */
546 ListIt addInst(DynInstPtr &inst);
547
548 /** Function to tell the CPU that an instruction has completed. */
549 void instDone(unsigned tid);
550
551 /** Add Instructions to the CPU Remove List*/
552 void addToRemoveList(DynInstPtr &inst);
553
554 /** Remove an instruction from the front end of the list. There's
555 * no restriction on location of the instruction.
556 */
557 void removeFrontInst(DynInstPtr &inst);
558
559 /** Remove all instructions that are not currently in the ROB.
560 * There's also an option to not squash delay slot instructions.*/
561 void removeInstsNotInROB(unsigned tid);
562
563 /** Remove all instructions younger than the given sequence number. */
564 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
565
566 /** Removes the instruction pointed to by the iterator. */
567 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
568
569 /** Cleans up all instructions on the remove list. */
570 void cleanUpRemovedInsts();
571
572 /** Debug function to print all instructions on the list. */
573 void dumpInsts();
574
575 public:
576#ifndef NDEBUG
577 /** Count of total number of dynamic instructions in flight. */
578 int instcount;
579#endif
580
581 /** List of all the instructions in flight. */
582 std::list<DynInstPtr> instList;
583
584 /** List of all the instructions that will be removed at the end of this
585 * cycle.
586 */
587 std::queue<ListIt> removeList;
588
589#ifdef DEBUG
590 /** Debug structure to keep track of the sequence numbers still in
591 * flight.
592 */
593 std::set<InstSeqNum> snList;
594#endif
595
596 /** Records if instructions need to be removed this cycle due to
597 * being retired or squashed.
598 */
599 bool removeInstsThisCycle;
600
601 protected:
602 /** The fetch stage. */
603 typename CPUPolicy::Fetch fetch;
604
605 /** The decode stage. */
606 typename CPUPolicy::Decode decode;
607
608 /** The dispatch stage. */
609 typename CPUPolicy::Rename rename;
610
611 /** The issue/execute/writeback stages. */
612 typename CPUPolicy::IEW iew;
613
614 /** The commit stage. */
615 typename CPUPolicy::Commit commit;
616
617 /** The register file. */
618 typename CPUPolicy::RegFile regFile;
619
620 /** The free list. */
621 typename CPUPolicy::FreeList freeList;
622
623 /** The rename map. */
624 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
625
626 /** The commit rename map. */
627 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
628
629 /** The re-order buffer. */
630 typename CPUPolicy::ROB rob;
631
632 /** Active Threads List */
633 std::list<unsigned> activeThreads;
634
635 /** Integer Register Scoreboard */
636 Scoreboard scoreboard;
637
638 public:
639 /** Enum to give each stage a specific index, so when calling
640 * activateStage() or deactivateStage(), they can specify which stage
641 * is being activated/deactivated.
642 */
643 enum StageIdx {
644 FetchIdx,
645 DecodeIdx,
646 RenameIdx,
647 IEWIdx,
648 CommitIdx,
649 NumStages };
650
651 /** Typedefs from the Impl to get the structs that each of the
652 * time buffers should use.
653 */
654 typedef typename CPUPolicy::TimeStruct TimeStruct;
655
656 typedef typename CPUPolicy::FetchStruct FetchStruct;
657
658 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
659
660 typedef typename CPUPolicy::RenameStruct RenameStruct;
661
662 typedef typename CPUPolicy::IEWStruct IEWStruct;
663
664 /** The main time buffer to do backwards communication. */
665 TimeBuffer<TimeStruct> timeBuffer;
666
667 /** The fetch stage's instruction queue. */
668 TimeBuffer<FetchStruct> fetchQueue;
669
670 /** The decode stage's instruction queue. */
671 TimeBuffer<DecodeStruct> decodeQueue;
672
673 /** The rename stage's instruction queue. */
674 TimeBuffer<RenameStruct> renameQueue;
675
676 /** The IEW stage's instruction queue. */
677 TimeBuffer<IEWStruct> iewQueue;
678
679 private:
680 /** The activity recorder; used to tell if the CPU has any
681 * activity remaining or if it can go to idle and deschedule
682 * itself.
683 */
684 ActivityRecorder activityRec;
685
686 public:
687 /** Records that there was time buffer activity this cycle. */
688 void activityThisCycle() { activityRec.activity(); }
689
690 /** Changes a stage's status to active within the activity recorder. */
691 void activateStage(const StageIdx idx)
692 { activityRec.activateStage(idx); }
693
694 /** Changes a stage's status to inactive within the activity recorder. */
695 void deactivateStage(const StageIdx idx)
696 { activityRec.deactivateStage(idx); }
697
698 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
699 void wakeCPU();
700
701#if FULL_SYSTEM
702 virtual void wakeup();
703#endif
704
705 /** Gets a free thread id. Use if thread ids change across system. */
706 int getFreeTid();
707
708 public:
709 /** Returns a pointer to a thread context. */
710 ThreadContext *tcBase(unsigned tid)
711 {
712 return thread[tid]->getTC();
713 }
714
715 /** The global sequence number counter. */
716 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
717
718#if USE_CHECKER
719 /** Pointer to the checker, which can dynamically verify
720 * instruction results at run time. This can be set to NULL if it
721 * is not being used.
722 */
723 Checker<DynInstPtr> *checker;
724#endif
725
726#if FULL_SYSTEM
727 /** Pointer to the system. */
728 System *system;
729
730 /** Pointer to physical memory. */
731 PhysicalMemory *physmem;
732#endif
733
734 /** Event to call process() on once draining has completed. */
735 Event *drainEvent;
736
737 /** Counter of how many stages have completed draining. */
738 int drainCount;
739
740 /** Pointers to all of the threads in the CPU. */
741 std::vector<Thread *> thread;
742
743 /** Whether or not the CPU should defer its registration. */
744 bool deferRegistration;
745
746 /** Is there a context switch pending? */
747 bool contextSwitch;
748
749 /** Threads Scheduled to Enter CPU */
750 std::list<int> cpuWaitList;
751
752 /** The cycle that the CPU was last running, used for statistics. */
753 Tick lastRunningCycle;
754
755 /** The cycle that the CPU was last activated by a new thread*/
756 Tick lastActivatedCycle;
757
758 /** Number of Threads CPU can process */
759 unsigned numThreads;
760
761 /** Mapping for system thread id to cpu id */
762 std::map<unsigned,unsigned> threadMap;
763
764 /** Available thread ids in the cpu*/
765 std::vector<unsigned> tids;
766
767 /** CPU read function, forwards read to LSQ. */
768 template <class T>
769 Fault read(RequestPtr &req, T &data, int load_idx)
770 {
771 return this->iew.ldstQueue.read(req, data, load_idx);
772 }
773
774 /** CPU write function, forwards write to LSQ. */
775 template <class T>
776 Fault write(RequestPtr &req, T &data, int store_idx)
777 {
778 return this->iew.ldstQueue.write(req, data, store_idx);
779 }
780
781 Addr lockAddr;
782
783 /** Temporary fix for the lock flag, works in the UP case. */
784 bool lockFlag;
785
786 /** Stat for total number of times the CPU is descheduled. */
787 Stats::Scalar<> timesIdled;
788 /** Stat for total number of cycles the CPU spends descheduled. */
789 Stats::Scalar<> idleCycles;
790 /** Stat for the number of committed instructions per thread. */
791 Stats::Vector<> committedInsts;
792 /** Stat for the total number of committed instructions. */
793 Stats::Scalar<> totalCommittedInsts;
794 /** Stat for the CPI per thread. */
795 Stats::Formula cpi;
796 /** Stat for the total CPI. */
797 Stats::Formula totalCpi;
798 /** Stat for the IPC per thread. */
799 Stats::Formula ipc;
800 /** Stat for the total IPC. */
801 Stats::Formula totalIpc;
802};
803
804#endif // __CPU_O3_CPU_HH__
282 /** Returns a specific port. */
283 Port *getPort(const std::string &if_name, int idx);
284
285 /** Ticks CPU, calling tick() on each stage, and checking the overall
286 * activity to see if the CPU should deschedule itself.
287 */
288 void tick();
289
290 /** Initialize the CPU */
291 void init();
292
293 /** Returns the Number of Active Threads in the CPU */
294 int numActiveThreads()
295 { return activeThreads.size(); }
296
297 /** Add Thread to Active Threads List */
298 void activateThread(unsigned tid);
299
300 /** Remove Thread from Active Threads List */
301 void deactivateThread(unsigned tid);
302
303 /** Setup CPU to insert a thread's context */
304 void insertThread(unsigned tid);
305
306 /** Remove all of a thread's context from CPU */
307 void removeThread(unsigned tid);
308
309 /** Count the Total Instructions Committed in the CPU. */
310 virtual Counter totalInstructions() const
311 {
312 Counter total(0);
313
314 for (int i=0; i < thread.size(); i++)
315 total += thread[i]->numInst;
316
317 return total;
318 }
319
320 /** Add Thread to Active Threads List. */
321 void activateContext(int tid, int delay);
322
323 /** Remove Thread from Active Threads List */
324 void suspendContext(int tid);
325
326 /** Remove Thread from Active Threads List &&
327 * Possibly Remove Thread Context from CPU.
328 */
329 bool deallocateContext(int tid, bool remove, int delay = 1);
330
331 /** Remove Thread from Active Threads List &&
332 * Remove Thread Context from CPU.
333 */
334 void haltContext(int tid);
335
336 /** Activate a Thread When CPU Resources are Available. */
337 void activateWhenReady(int tid);
338
339 /** Add or Remove a Thread Context in the CPU. */
340 void doContextSwitch();
341
342 /** Update The Order In Which We Process Threads. */
343 void updateThreadPriority();
344
345 /** Serialize state. */
346 virtual void serialize(std::ostream &os);
347
348 /** Unserialize from a checkpoint. */
349 virtual void unserialize(Checkpoint *cp, const std::string &section);
350
351 public:
352#if !FULL_SYSTEM
353 /** Executes a syscall.
354 * @todo: Determine if this needs to be virtual.
355 */
356 void syscall(int64_t callnum, int tid);
357
358 /** Sets the return value of a syscall. */
359 void setSyscallReturn(SyscallReturn return_value, int tid);
360
361#endif
362
363 /** Starts draining the CPU's pipeline of all instructions in
364 * order to stop all memory accesses. */
365 virtual unsigned int drain(Event *drain_event);
366
367 /** Resumes execution after a drain. */
368 virtual void resume();
369
370 /** Signals to this CPU that a stage has completed switching out. */
371 void signalDrained();
372
373 /** Switches out this CPU. */
374 virtual void switchOut();
375
376 /** Takes over from another CPU. */
377 virtual void takeOverFrom(BaseCPU *oldCPU);
378
379 /** Get the current instruction sequence number, and increment it. */
380 InstSeqNum getAndIncrementInstSeq()
381 { return globalSeqNum++; }
382
383 /** Traps to handle given fault. */
384 void trap(Fault fault, unsigned tid);
385
386#if FULL_SYSTEM
387 /** HW return from error interrupt. */
388 Fault hwrei(unsigned tid);
389
390 bool simPalCheck(int palFunc, unsigned tid);
391
392 /** Returns the Fault for any valid interrupt. */
393 Fault getInterrupts();
394
395 /** Processes any an interrupt fault. */
396 void processInterrupts(Fault interrupt);
397
398 /** Halts the CPU. */
399 void halt() { panic("Halt not implemented!\n"); }
400
401 /** Update the Virt and Phys ports of all ThreadContexts to
402 * reflect change in memory connections. */
403 void updateMemPorts();
404
405 /** Check if this address is a valid instruction address. */
406 bool validInstAddr(Addr addr) { return true; }
407
408 /** Check if this address is a valid data address. */
409 bool validDataAddr(Addr addr) { return true; }
410
411 /** Get instruction asid. */
412 int getInstAsid(unsigned tid)
413 { return regFile.miscRegs[tid].getInstAsid(); }
414
415 /** Get data asid. */
416 int getDataAsid(unsigned tid)
417 { return regFile.miscRegs[tid].getDataAsid(); }
418#else
419 /** Get instruction asid. */
420 int getInstAsid(unsigned tid)
421 { return thread[tid]->getInstAsid(); }
422
423 /** Get data asid. */
424 int getDataAsid(unsigned tid)
425 { return thread[tid]->getDataAsid(); }
426
427#endif
428
429 /** Register accessors. Index refers to the physical register index. */
430
431 /** Reads a miscellaneous register. */
432 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
433
434 /** Reads a misc. register, including any side effects the read
435 * might have as defined by the architecture.
436 */
437 TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
438
439 /** Sets a miscellaneous register. */
440 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
441
442 /** Sets a misc. register, including any side effects the write
443 * might have as defined by the architecture.
444 */
445 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
446 unsigned tid);
447
448 uint64_t readIntReg(int reg_idx);
449
450 TheISA::FloatReg readFloatReg(int reg_idx);
451
452 TheISA::FloatReg readFloatReg(int reg_idx, int width);
453
454 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
455
456 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
457
458 void setIntReg(int reg_idx, uint64_t val);
459
460 void setFloatReg(int reg_idx, TheISA::FloatReg val);
461
462 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
463
464 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
465
466 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
467
468 uint64_t readArchIntReg(int reg_idx, unsigned tid);
469
470 float readArchFloatRegSingle(int reg_idx, unsigned tid);
471
472 double readArchFloatRegDouble(int reg_idx, unsigned tid);
473
474 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
475
476 /** Architectural register accessors. Looks up in the commit
477 * rename table to obtain the true physical index of the
478 * architected register first, then accesses that physical
479 * register.
480 */
481 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
482
483 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
484
485 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
486
487 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
488
489 /** Reads the commit PC of a specific thread. */
490 Addr readPC(unsigned tid);
491
492 /** Sets the commit PC of a specific thread. */
493 void setPC(Addr new_PC, unsigned tid);
494
495 /** Reads the commit micro PC of a specific thread. */
496 Addr readMicroPC(unsigned tid);
497
498 /** Sets the commmit micro PC of a specific thread. */
499 void setMicroPC(Addr new_microPC, unsigned tid);
500
501 /** Reads the next PC of a specific thread. */
502 Addr readNextPC(unsigned tid);
503
504 /** Sets the next PC of a specific thread. */
505 void setNextPC(Addr val, unsigned tid);
506
507 /** Reads the next NPC of a specific thread. */
508 Addr readNextNPC(unsigned tid);
509
510 /** Sets the next NPC of a specific thread. */
511 void setNextNPC(Addr val, unsigned tid);
512
513 /** Reads the commit next micro PC of a specific thread. */
514 Addr readNextMicroPC(unsigned tid);
515
516 /** Sets the commit next micro PC of a specific thread. */
517 void setNextMicroPC(Addr val, unsigned tid);
518
519 /** Initiates a squash of all in-flight instructions for a given
520 * thread. The source of the squash is an external update of
521 * state through the TC.
522 */
523 void squashFromTC(unsigned tid);
524
525 /** Function to add instruction onto the head of the list of the
526 * instructions. Used when new instructions are fetched.
527 */
528 ListIt addInst(DynInstPtr &inst);
529
530 /** Function to tell the CPU that an instruction has completed. */
531 void instDone(unsigned tid);
532
533 /** Add Instructions to the CPU Remove List*/
534 void addToRemoveList(DynInstPtr &inst);
535
536 /** Remove an instruction from the front end of the list. There's
537 * no restriction on location of the instruction.
538 */
539 void removeFrontInst(DynInstPtr &inst);
540
541 /** Remove all instructions that are not currently in the ROB.
542 * There's also an option to not squash delay slot instructions.*/
543 void removeInstsNotInROB(unsigned tid);
544
545 /** Remove all instructions younger than the given sequence number. */
546 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
547
548 /** Removes the instruction pointed to by the iterator. */
549 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
550
551 /** Cleans up all instructions on the remove list. */
552 void cleanUpRemovedInsts();
553
554 /** Debug function to print all instructions on the list. */
555 void dumpInsts();
556
557 public:
558#ifndef NDEBUG
559 /** Count of total number of dynamic instructions in flight. */
560 int instcount;
561#endif
562
563 /** List of all the instructions in flight. */
564 std::list<DynInstPtr> instList;
565
566 /** List of all the instructions that will be removed at the end of this
567 * cycle.
568 */
569 std::queue<ListIt> removeList;
570
571#ifdef DEBUG
572 /** Debug structure to keep track of the sequence numbers still in
573 * flight.
574 */
575 std::set<InstSeqNum> snList;
576#endif
577
578 /** Records if instructions need to be removed this cycle due to
579 * being retired or squashed.
580 */
581 bool removeInstsThisCycle;
582
583 protected:
584 /** The fetch stage. */
585 typename CPUPolicy::Fetch fetch;
586
587 /** The decode stage. */
588 typename CPUPolicy::Decode decode;
589
590 /** The dispatch stage. */
591 typename CPUPolicy::Rename rename;
592
593 /** The issue/execute/writeback stages. */
594 typename CPUPolicy::IEW iew;
595
596 /** The commit stage. */
597 typename CPUPolicy::Commit commit;
598
599 /** The register file. */
600 typename CPUPolicy::RegFile regFile;
601
602 /** The free list. */
603 typename CPUPolicy::FreeList freeList;
604
605 /** The rename map. */
606 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
607
608 /** The commit rename map. */
609 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
610
611 /** The re-order buffer. */
612 typename CPUPolicy::ROB rob;
613
614 /** Active Threads List */
615 std::list<unsigned> activeThreads;
616
617 /** Integer Register Scoreboard */
618 Scoreboard scoreboard;
619
620 public:
621 /** Enum to give each stage a specific index, so when calling
622 * activateStage() or deactivateStage(), they can specify which stage
623 * is being activated/deactivated.
624 */
625 enum StageIdx {
626 FetchIdx,
627 DecodeIdx,
628 RenameIdx,
629 IEWIdx,
630 CommitIdx,
631 NumStages };
632
633 /** Typedefs from the Impl to get the structs that each of the
634 * time buffers should use.
635 */
636 typedef typename CPUPolicy::TimeStruct TimeStruct;
637
638 typedef typename CPUPolicy::FetchStruct FetchStruct;
639
640 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
641
642 typedef typename CPUPolicy::RenameStruct RenameStruct;
643
644 typedef typename CPUPolicy::IEWStruct IEWStruct;
645
646 /** The main time buffer to do backwards communication. */
647 TimeBuffer<TimeStruct> timeBuffer;
648
649 /** The fetch stage's instruction queue. */
650 TimeBuffer<FetchStruct> fetchQueue;
651
652 /** The decode stage's instruction queue. */
653 TimeBuffer<DecodeStruct> decodeQueue;
654
655 /** The rename stage's instruction queue. */
656 TimeBuffer<RenameStruct> renameQueue;
657
658 /** The IEW stage's instruction queue. */
659 TimeBuffer<IEWStruct> iewQueue;
660
661 private:
662 /** The activity recorder; used to tell if the CPU has any
663 * activity remaining or if it can go to idle and deschedule
664 * itself.
665 */
666 ActivityRecorder activityRec;
667
668 public:
669 /** Records that there was time buffer activity this cycle. */
670 void activityThisCycle() { activityRec.activity(); }
671
672 /** Changes a stage's status to active within the activity recorder. */
673 void activateStage(const StageIdx idx)
674 { activityRec.activateStage(idx); }
675
676 /** Changes a stage's status to inactive within the activity recorder. */
677 void deactivateStage(const StageIdx idx)
678 { activityRec.deactivateStage(idx); }
679
680 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
681 void wakeCPU();
682
683#if FULL_SYSTEM
684 virtual void wakeup();
685#endif
686
687 /** Gets a free thread id. Use if thread ids change across system. */
688 int getFreeTid();
689
690 public:
691 /** Returns a pointer to a thread context. */
692 ThreadContext *tcBase(unsigned tid)
693 {
694 return thread[tid]->getTC();
695 }
696
697 /** The global sequence number counter. */
698 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
699
700#if USE_CHECKER
701 /** Pointer to the checker, which can dynamically verify
702 * instruction results at run time. This can be set to NULL if it
703 * is not being used.
704 */
705 Checker<DynInstPtr> *checker;
706#endif
707
708#if FULL_SYSTEM
709 /** Pointer to the system. */
710 System *system;
711
712 /** Pointer to physical memory. */
713 PhysicalMemory *physmem;
714#endif
715
716 /** Event to call process() on once draining has completed. */
717 Event *drainEvent;
718
719 /** Counter of how many stages have completed draining. */
720 int drainCount;
721
722 /** Pointers to all of the threads in the CPU. */
723 std::vector<Thread *> thread;
724
725 /** Whether or not the CPU should defer its registration. */
726 bool deferRegistration;
727
728 /** Is there a context switch pending? */
729 bool contextSwitch;
730
731 /** Threads Scheduled to Enter CPU */
732 std::list<int> cpuWaitList;
733
734 /** The cycle that the CPU was last running, used for statistics. */
735 Tick lastRunningCycle;
736
737 /** The cycle that the CPU was last activated by a new thread*/
738 Tick lastActivatedCycle;
739
740 /** Number of Threads CPU can process */
741 unsigned numThreads;
742
743 /** Mapping for system thread id to cpu id */
744 std::map<unsigned,unsigned> threadMap;
745
746 /** Available thread ids in the cpu*/
747 std::vector<unsigned> tids;
748
749 /** CPU read function, forwards read to LSQ. */
750 template <class T>
751 Fault read(RequestPtr &req, T &data, int load_idx)
752 {
753 return this->iew.ldstQueue.read(req, data, load_idx);
754 }
755
756 /** CPU write function, forwards write to LSQ. */
757 template <class T>
758 Fault write(RequestPtr &req, T &data, int store_idx)
759 {
760 return this->iew.ldstQueue.write(req, data, store_idx);
761 }
762
763 Addr lockAddr;
764
765 /** Temporary fix for the lock flag, works in the UP case. */
766 bool lockFlag;
767
768 /** Stat for total number of times the CPU is descheduled. */
769 Stats::Scalar<> timesIdled;
770 /** Stat for total number of cycles the CPU spends descheduled. */
771 Stats::Scalar<> idleCycles;
772 /** Stat for the number of committed instructions per thread. */
773 Stats::Vector<> committedInsts;
774 /** Stat for the total number of committed instructions. */
775 Stats::Scalar<> totalCommittedInsts;
776 /** Stat for the CPI per thread. */
777 Stats::Formula cpi;
778 /** Stat for the total CPI. */
779 Stats::Formula totalCpi;
780 /** Stat for the IPC per thread. */
781 Stats::Formula ipc;
782 /** Stat for the total IPC. */
783 Stats::Formula totalIpc;
784};
785
786#endif // __CPU_O3_CPU_HH__