1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "config/use_checker.hh"
46#include "cpu/activity.hh"
47#include "cpu/base.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/o3/comm.hh"
50#include "cpu/o3/cpu_policy.hh"
51#include "cpu/o3/scoreboard.hh"
52#include "cpu/o3/thread_state.hh"
53//#include "cpu/o3/thread_context.hh"
54#include "sim/process.hh"
55
56template <class>
57class Checker;
58class ThreadContext;
59template <class>
60class O3ThreadContext;
61
62class Checkpoint;
63class MemObject;
64class Process;
65
66class BaseO3CPU : public BaseCPU
67{
68 //Stuff that's pretty ISA independent will go here.
69 public:
70 typedef BaseCPU::Params Params;
71
72 BaseO3CPU(Params *params);
73
74 void regStats();
75
76 /** Sets this CPU's ID. */
77 void setCpuId(int id) { cpu_id = id; }
78
79 /** Reads this CPU's ID. */
80 int readCpuId() { return cpu_id; }
81
82 protected:
83 int cpu_id;
84};
85
86/**
87 * FullO3CPU class, has each of the stages (fetch through commit)
88 * within it, as well as all of the time buffers between stages. The
89 * tick() function for the CPU is defined here.
90 */
91template <class Impl>
92class FullO3CPU : public BaseO3CPU
93{
94 public:
95 // Typedefs from the Impl here.
96 typedef typename Impl::CPUPol CPUPolicy;
97 typedef typename Impl::DynInstPtr DynInstPtr;
98 typedef typename Impl::O3CPU O3CPU;
99 typedef typename Impl::Params Params;
100
101 typedef O3ThreadState<Impl> Thread;
102
103 typedef typename std::list<DynInstPtr>::iterator ListIt;
104
105 friend class O3ThreadContext<Impl>;
106
107 public:
108 enum Status {
109 Running,
110 Idle,
111 Halted,
112 Blocked,
113 SwitchedOut
114 };
115
116 TheISA::ITB * itb;
117 TheISA::DTB * dtb;
118
119 /** Overall CPU status. */
120 Status _status;
121
122 /** Per-thread status in CPU, used for SMT. */
123 Status _threadStatus[Impl::MaxThreads];
124
125 private:
126 class TickEvent : public Event
127 {
128 private:
129 /** Pointer to the CPU. */
130 FullO3CPU<Impl> *cpu;
131
132 public:
133 /** Constructs a tick event. */
134 TickEvent(FullO3CPU<Impl> *c);
135
136 /** Processes a tick event, calling tick() on the CPU. */
137 void process();
138 /** Returns the description of the tick event. */
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "config/use_checker.hh"
46#include "cpu/activity.hh"
47#include "cpu/base.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/o3/comm.hh"
50#include "cpu/o3/cpu_policy.hh"
51#include "cpu/o3/scoreboard.hh"
52#include "cpu/o3/thread_state.hh"
53//#include "cpu/o3/thread_context.hh"
54#include "sim/process.hh"
55
56template <class>
57class Checker;
58class ThreadContext;
59template <class>
60class O3ThreadContext;
61
62class Checkpoint;
63class MemObject;
64class Process;
65
66class BaseO3CPU : public BaseCPU
67{
68 //Stuff that's pretty ISA independent will go here.
69 public:
70 typedef BaseCPU::Params Params;
71
72 BaseO3CPU(Params *params);
73
74 void regStats();
75
76 /** Sets this CPU's ID. */
77 void setCpuId(int id) { cpu_id = id; }
78
79 /** Reads this CPU's ID. */
80 int readCpuId() { return cpu_id; }
81
82 protected:
83 int cpu_id;
84};
85
86/**
87 * FullO3CPU class, has each of the stages (fetch through commit)
88 * within it, as well as all of the time buffers between stages. The
89 * tick() function for the CPU is defined here.
90 */
91template <class Impl>
92class FullO3CPU : public BaseO3CPU
93{
94 public:
95 // Typedefs from the Impl here.
96 typedef typename Impl::CPUPol CPUPolicy;
97 typedef typename Impl::DynInstPtr DynInstPtr;
98 typedef typename Impl::O3CPU O3CPU;
99 typedef typename Impl::Params Params;
100
101 typedef O3ThreadState<Impl> Thread;
102
103 typedef typename std::list<DynInstPtr>::iterator ListIt;
104
105 friend class O3ThreadContext<Impl>;
106
107 public:
108 enum Status {
109 Running,
110 Idle,
111 Halted,
112 Blocked,
113 SwitchedOut
114 };
115
116 TheISA::ITB * itb;
117 TheISA::DTB * dtb;
118
119 /** Overall CPU status. */
120 Status _status;
121
122 /** Per-thread status in CPU, used for SMT. */
123 Status _threadStatus[Impl::MaxThreads];
124
125 private:
126 class TickEvent : public Event
127 {
128 private:
129 /** Pointer to the CPU. */
130 FullO3CPU<Impl> *cpu;
131
132 public:
133 /** Constructs a tick event. */
134 TickEvent(FullO3CPU<Impl> *c);
135
136 /** Processes a tick event, calling tick() on the CPU. */
137 void process();
138 /** Returns the description of the tick event. */
|
233 };
234
235 /** Schedule cpu to deallocate thread context.*/
236 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
237 {
238 // Schedule thread to activate, regardless of its current state.
239 if (deallocateContextEvent[tid].squashed())
240 deallocateContextEvent[tid].
241 reschedule(nextCycle(curTick + ticks(delay)));
242 else if (!deallocateContextEvent[tid].scheduled())
243 deallocateContextEvent[tid].
244 schedule(nextCycle(curTick + ticks(delay)));
245 }
246
247 /** Unschedule thread deallocation in CPU */
248 void unscheduleDeallocateContextEvent(int tid)
249 {
250 if (deallocateContextEvent[tid].scheduled())
251 deallocateContextEvent[tid].squash();
252 }
253
254 /** The tick event used for scheduling CPU ticks. */
255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
256
257 public:
258 /** Constructs a CPU with the given parameters. */
259 FullO3CPU(O3CPU *o3_cpu, Params *params);
260 /** Destructor. */
261 ~FullO3CPU();
262
263 /** Registers statistics. */
264 void fullCPURegStats();
265
266 /** Translates instruction requestion. */
267 Fault translateInstReq(RequestPtr &req, Thread *thread)
268 {
269 return this->itb->translate(req, thread->getTC());
270 }
271
272 /** Translates data read request. */
273 Fault translateDataReadReq(RequestPtr &req, Thread *thread)
274 {
275 return this->dtb->translate(req, thread->getTC(), false);
276 }
277
278 /** Translates data write request. */
279 Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
280 {
281 return this->dtb->translate(req, thread->getTC(), true);
282 }
283
284 /** Returns a specific port. */
285 Port *getPort(const std::string &if_name, int idx);
286
287 /** Ticks CPU, calling tick() on each stage, and checking the overall
288 * activity to see if the CPU should deschedule itself.
289 */
290 void tick();
291
292 /** Initialize the CPU */
293 void init();
294
295 /** Returns the Number of Active Threads in the CPU */
296 int numActiveThreads()
297 { return activeThreads.size(); }
298
299 /** Add Thread to Active Threads List */
300 void activateThread(unsigned tid);
301
302 /** Remove Thread from Active Threads List */
303 void deactivateThread(unsigned tid);
304
305 /** Setup CPU to insert a thread's context */
306 void insertThread(unsigned tid);
307
308 /** Remove all of a thread's context from CPU */
309 void removeThread(unsigned tid);
310
311 /** Count the Total Instructions Committed in the CPU. */
312 virtual Counter totalInstructions() const
313 {
314 Counter total(0);
315
316 for (int i=0; i < thread.size(); i++)
317 total += thread[i]->numInst;
318
319 return total;
320 }
321
322 /** Add Thread to Active Threads List. */
323 void activateContext(int tid, int delay);
324
325 /** Remove Thread from Active Threads List */
326 void suspendContext(int tid);
327
328 /** Remove Thread from Active Threads List &&
329 * Possibly Remove Thread Context from CPU.
330 */
331 bool deallocateContext(int tid, bool remove, int delay = 1);
332
333 /** Remove Thread from Active Threads List &&
334 * Remove Thread Context from CPU.
335 */
336 void haltContext(int tid);
337
338 /** Activate a Thread When CPU Resources are Available. */
339 void activateWhenReady(int tid);
340
341 /** Add or Remove a Thread Context in the CPU. */
342 void doContextSwitch();
343
344 /** Update The Order In Which We Process Threads. */
345 void updateThreadPriority();
346
347 /** Serialize state. */
348 virtual void serialize(std::ostream &os);
349
350 /** Unserialize from a checkpoint. */
351 virtual void unserialize(Checkpoint *cp, const std::string §ion);
352
353 public:
354 /** Executes a syscall on this cycle.
355 * ---------------------------------------
356 * Note: this is a virtual function. CPU-Specific
357 * functionality defined in derived classes
358 */
359 virtual void syscall(int tid) { panic("Unimplemented!"); }
360
361 /** Starts draining the CPU's pipeline of all instructions in
362 * order to stop all memory accesses. */
363 virtual unsigned int drain(Event *drain_event);
364
365 /** Resumes execution after a drain. */
366 virtual void resume();
367
368 /** Signals to this CPU that a stage has completed switching out. */
369 void signalDrained();
370
371 /** Switches out this CPU. */
372 virtual void switchOut();
373
374 /** Takes over from another CPU. */
375 virtual void takeOverFrom(BaseCPU *oldCPU);
376
377 /** Get the current instruction sequence number, and increment it. */
378 InstSeqNum getAndIncrementInstSeq()
379 { return globalSeqNum++; }
380
381#if FULL_SYSTEM
382 /** Update the Virt and Phys ports of all ThreadContexts to
383 * reflect change in memory connections. */
384 void updateMemPorts();
385
386 /** Check if this address is a valid instruction address. */
387 bool validInstAddr(Addr addr) { return true; }
388
389 /** Check if this address is a valid data address. */
390 bool validDataAddr(Addr addr) { return true; }
391
392 /** Get instruction asid. */
393 int getInstAsid(unsigned tid)
394 { return regFile.miscRegs[tid].getInstAsid(); }
395
396 /** Get data asid. */
397 int getDataAsid(unsigned tid)
398 { return regFile.miscRegs[tid].getDataAsid(); }
399#else
400 /** Get instruction asid. */
401 int getInstAsid(unsigned tid)
402 { return thread[tid]->getInstAsid(); }
403
404 /** Get data asid. */
405 int getDataAsid(unsigned tid)
406 { return thread[tid]->getDataAsid(); }
407
408#endif
409
410 /** Register accessors. Index refers to the physical register index. */
411 uint64_t readIntReg(int reg_idx);
412
413 TheISA::FloatReg readFloatReg(int reg_idx);
414
415 TheISA::FloatReg readFloatReg(int reg_idx, int width);
416
417 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
418
419 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
420
421 void setIntReg(int reg_idx, uint64_t val);
422
423 void setFloatReg(int reg_idx, TheISA::FloatReg val);
424
425 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
426
427 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
428
429 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
430
431 uint64_t readArchIntReg(int reg_idx, unsigned tid);
432
433 float readArchFloatRegSingle(int reg_idx, unsigned tid);
434
435 double readArchFloatRegDouble(int reg_idx, unsigned tid);
436
437 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
438
439 /** Architectural register accessors. Looks up in the commit
440 * rename table to obtain the true physical index of the
441 * architected register first, then accesses that physical
442 * register.
443 */
444 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
445
446 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
447
448 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
449
450 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
451
452 /** Reads the commit PC of a specific thread. */
453 Addr readPC(unsigned tid);
454
455 /** Sets the commit PC of a specific thread. */
456 void setPC(Addr new_PC, unsigned tid);
457
458 /** Reads the commit micro PC of a specific thread. */
459 Addr readMicroPC(unsigned tid);
460
461 /** Sets the commmit micro PC of a specific thread. */
462 void setMicroPC(Addr new_microPC, unsigned tid);
463
464 /** Reads the next PC of a specific thread. */
465 Addr readNextPC(unsigned tid);
466
467 /** Sets the next PC of a specific thread. */
468 void setNextPC(Addr val, unsigned tid);
469
470 /** Reads the next NPC of a specific thread. */
471 Addr readNextNPC(unsigned tid);
472
473 /** Sets the next NPC of a specific thread. */
474 void setNextNPC(Addr val, unsigned tid);
475
476 /** Reads the commit next micro PC of a specific thread. */
477 Addr readNextMicroPC(unsigned tid);
478
479 /** Sets the commit next micro PC of a specific thread. */
480 void setNextMicroPC(Addr val, unsigned tid);
481
482 /** Function to add instruction onto the head of the list of the
483 * instructions. Used when new instructions are fetched.
484 */
485 ListIt addInst(DynInstPtr &inst);
486
487 /** Function to tell the CPU that an instruction has completed. */
488 void instDone(unsigned tid);
489
490 /** Add Instructions to the CPU Remove List*/
491 void addToRemoveList(DynInstPtr &inst);
492
493 /** Remove an instruction from the front end of the list. There's
494 * no restriction on location of the instruction.
495 */
496 void removeFrontInst(DynInstPtr &inst);
497
498 /** Remove all instructions that are not currently in the ROB.
499 * There's also an option to not squash delay slot instructions.*/
500 void removeInstsNotInROB(unsigned tid);
501
502 /** Remove all instructions younger than the given sequence number. */
503 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
504
505 /** Removes the instruction pointed to by the iterator. */
506 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
507
508 /** Cleans up all instructions on the remove list. */
509 void cleanUpRemovedInsts();
510
511 /** Debug function to print all instructions on the list. */
512 void dumpInsts();
513
514 public:
515 /** List of all the instructions in flight. */
516 std::list<DynInstPtr> instList;
517
518 /** List of all the instructions that will be removed at the end of this
519 * cycle.
520 */
521 std::queue<ListIt> removeList;
522
523#ifdef DEBUG
524 /** Debug structure to keep track of the sequence numbers still in
525 * flight.
526 */
527 std::set<InstSeqNum> snList;
528#endif
529
530 /** Records if instructions need to be removed this cycle due to
531 * being retired or squashed.
532 */
533 bool removeInstsThisCycle;
534
535 protected:
536 /** The fetch stage. */
537 typename CPUPolicy::Fetch fetch;
538
539 /** The decode stage. */
540 typename CPUPolicy::Decode decode;
541
542 /** The dispatch stage. */
543 typename CPUPolicy::Rename rename;
544
545 /** The issue/execute/writeback stages. */
546 typename CPUPolicy::IEW iew;
547
548 /** The commit stage. */
549 typename CPUPolicy::Commit commit;
550
551 /** The register file. */
552 typename CPUPolicy::RegFile regFile;
553
554 /** The free list. */
555 typename CPUPolicy::FreeList freeList;
556
557 /** The rename map. */
558 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
559
560 /** The commit rename map. */
561 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
562
563 /** The re-order buffer. */
564 typename CPUPolicy::ROB rob;
565
566 /** Active Threads List */
567 std::list<unsigned> activeThreads;
568
569 /** Integer Register Scoreboard */
570 Scoreboard scoreboard;
571
572 public:
573 /** Enum to give each stage a specific index, so when calling
574 * activateStage() or deactivateStage(), they can specify which stage
575 * is being activated/deactivated.
576 */
577 enum StageIdx {
578 FetchIdx,
579 DecodeIdx,
580 RenameIdx,
581 IEWIdx,
582 CommitIdx,
583 NumStages };
584
585 /** Typedefs from the Impl to get the structs that each of the
586 * time buffers should use.
587 */
588 typedef typename CPUPolicy::TimeStruct TimeStruct;
589
590 typedef typename CPUPolicy::FetchStruct FetchStruct;
591
592 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
593
594 typedef typename CPUPolicy::RenameStruct RenameStruct;
595
596 typedef typename CPUPolicy::IEWStruct IEWStruct;
597
598 /** The main time buffer to do backwards communication. */
599 TimeBuffer<TimeStruct> timeBuffer;
600
601 /** The fetch stage's instruction queue. */
602 TimeBuffer<FetchStruct> fetchQueue;
603
604 /** The decode stage's instruction queue. */
605 TimeBuffer<DecodeStruct> decodeQueue;
606
607 /** The rename stage's instruction queue. */
608 TimeBuffer<RenameStruct> renameQueue;
609
610 /** The IEW stage's instruction queue. */
611 TimeBuffer<IEWStruct> iewQueue;
612
613 private:
614 /** The activity recorder; used to tell if the CPU has any
615 * activity remaining or if it can go to idle and deschedule
616 * itself.
617 */
618 ActivityRecorder activityRec;
619
620 public:
621 /** Records that there was time buffer activity this cycle. */
622 void activityThisCycle() { activityRec.activity(); }
623
624 /** Changes a stage's status to active within the activity recorder. */
625 void activateStage(const StageIdx idx)
626 { activityRec.activateStage(idx); }
627
628 /** Changes a stage's status to inactive within the activity recorder. */
629 void deactivateStage(const StageIdx idx)
630 { activityRec.deactivateStage(idx); }
631
632 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
633 void wakeCPU();
634
635 /** Gets a free thread id. Use if thread ids change across system. */
636 int getFreeTid();
637
638 public:
639 /** Returns a pointer to a thread context. */
640 ThreadContext *tcBase(unsigned tid)
641 {
642 return thread[tid]->getTC();
643 }
644
645 /** The global sequence number counter. */
646 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
647
648#if USE_CHECKER
649 /** Pointer to the checker, which can dynamically verify
650 * instruction results at run time. This can be set to NULL if it
651 * is not being used.
652 */
653 Checker<DynInstPtr> *checker;
654#endif
655
656#if FULL_SYSTEM
657 /** Pointer to the system. */
658 System *system;
659
660 /** Pointer to physical memory. */
661 PhysicalMemory *physmem;
662#endif
663
664 /** Event to call process() on once draining has completed. */
665 Event *drainEvent;
666
667 /** Counter of how many stages have completed draining. */
668 int drainCount;
669
670 /** Pointers to all of the threads in the CPU. */
671 std::vector<Thread *> thread;
672
673 /** Whether or not the CPU should defer its registration. */
674 bool deferRegistration;
675
676 /** Is there a context switch pending? */
677 bool contextSwitch;
678
679 /** Threads Scheduled to Enter CPU */
680 std::list<int> cpuWaitList;
681
682 /** The cycle that the CPU was last running, used for statistics. */
683 Tick lastRunningCycle;
684
685 /** The cycle that the CPU was last activated by a new thread*/
686 Tick lastActivatedCycle;
687
688 /** Number of Threads CPU can process */
689 unsigned numThreads;
690
691 /** Mapping for system thread id to cpu id */
692 std::map<unsigned,unsigned> threadMap;
693
694 /** Available thread ids in the cpu*/
695 std::vector<unsigned> tids;
696
697 /** Stat for total number of times the CPU is descheduled. */
698 Stats::Scalar<> timesIdled;
699 /** Stat for total number of cycles the CPU spends descheduled. */
700 Stats::Scalar<> idleCycles;
701 /** Stat for the number of committed instructions per thread. */
702 Stats::Vector<> committedInsts;
703 /** Stat for the total number of committed instructions. */
704 Stats::Scalar<> totalCommittedInsts;
705 /** Stat for the CPI per thread. */
706 Stats::Formula cpi;
707 /** Stat for the total CPI. */
708 Stats::Formula totalCpi;
709 /** Stat for the IPC per thread. */
710 Stats::Formula ipc;
711 /** Stat for the total IPC. */
712 Stats::Formula totalIpc;
713};
714
715#endif // __CPU_O3_CPU_HH__
| 233 };
234
235 /** Schedule cpu to deallocate thread context.*/
236 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
237 {
238 // Schedule thread to activate, regardless of its current state.
239 if (deallocateContextEvent[tid].squashed())
240 deallocateContextEvent[tid].
241 reschedule(nextCycle(curTick + ticks(delay)));
242 else if (!deallocateContextEvent[tid].scheduled())
243 deallocateContextEvent[tid].
244 schedule(nextCycle(curTick + ticks(delay)));
245 }
246
247 /** Unschedule thread deallocation in CPU */
248 void unscheduleDeallocateContextEvent(int tid)
249 {
250 if (deallocateContextEvent[tid].scheduled())
251 deallocateContextEvent[tid].squash();
252 }
253
254 /** The tick event used for scheduling CPU ticks. */
255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
256
257 public:
258 /** Constructs a CPU with the given parameters. */
259 FullO3CPU(O3CPU *o3_cpu, Params *params);
260 /** Destructor. */
261 ~FullO3CPU();
262
263 /** Registers statistics. */
264 void fullCPURegStats();
265
266 /** Translates instruction requestion. */
267 Fault translateInstReq(RequestPtr &req, Thread *thread)
268 {
269 return this->itb->translate(req, thread->getTC());
270 }
271
272 /** Translates data read request. */
273 Fault translateDataReadReq(RequestPtr &req, Thread *thread)
274 {
275 return this->dtb->translate(req, thread->getTC(), false);
276 }
277
278 /** Translates data write request. */
279 Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
280 {
281 return this->dtb->translate(req, thread->getTC(), true);
282 }
283
284 /** Returns a specific port. */
285 Port *getPort(const std::string &if_name, int idx);
286
287 /** Ticks CPU, calling tick() on each stage, and checking the overall
288 * activity to see if the CPU should deschedule itself.
289 */
290 void tick();
291
292 /** Initialize the CPU */
293 void init();
294
295 /** Returns the Number of Active Threads in the CPU */
296 int numActiveThreads()
297 { return activeThreads.size(); }
298
299 /** Add Thread to Active Threads List */
300 void activateThread(unsigned tid);
301
302 /** Remove Thread from Active Threads List */
303 void deactivateThread(unsigned tid);
304
305 /** Setup CPU to insert a thread's context */
306 void insertThread(unsigned tid);
307
308 /** Remove all of a thread's context from CPU */
309 void removeThread(unsigned tid);
310
311 /** Count the Total Instructions Committed in the CPU. */
312 virtual Counter totalInstructions() const
313 {
314 Counter total(0);
315
316 for (int i=0; i < thread.size(); i++)
317 total += thread[i]->numInst;
318
319 return total;
320 }
321
322 /** Add Thread to Active Threads List. */
323 void activateContext(int tid, int delay);
324
325 /** Remove Thread from Active Threads List */
326 void suspendContext(int tid);
327
328 /** Remove Thread from Active Threads List &&
329 * Possibly Remove Thread Context from CPU.
330 */
331 bool deallocateContext(int tid, bool remove, int delay = 1);
332
333 /** Remove Thread from Active Threads List &&
334 * Remove Thread Context from CPU.
335 */
336 void haltContext(int tid);
337
338 /** Activate a Thread When CPU Resources are Available. */
339 void activateWhenReady(int tid);
340
341 /** Add or Remove a Thread Context in the CPU. */
342 void doContextSwitch();
343
344 /** Update The Order In Which We Process Threads. */
345 void updateThreadPriority();
346
347 /** Serialize state. */
348 virtual void serialize(std::ostream &os);
349
350 /** Unserialize from a checkpoint. */
351 virtual void unserialize(Checkpoint *cp, const std::string §ion);
352
353 public:
354 /** Executes a syscall on this cycle.
355 * ---------------------------------------
356 * Note: this is a virtual function. CPU-Specific
357 * functionality defined in derived classes
358 */
359 virtual void syscall(int tid) { panic("Unimplemented!"); }
360
361 /** Starts draining the CPU's pipeline of all instructions in
362 * order to stop all memory accesses. */
363 virtual unsigned int drain(Event *drain_event);
364
365 /** Resumes execution after a drain. */
366 virtual void resume();
367
368 /** Signals to this CPU that a stage has completed switching out. */
369 void signalDrained();
370
371 /** Switches out this CPU. */
372 virtual void switchOut();
373
374 /** Takes over from another CPU. */
375 virtual void takeOverFrom(BaseCPU *oldCPU);
376
377 /** Get the current instruction sequence number, and increment it. */
378 InstSeqNum getAndIncrementInstSeq()
379 { return globalSeqNum++; }
380
381#if FULL_SYSTEM
382 /** Update the Virt and Phys ports of all ThreadContexts to
383 * reflect change in memory connections. */
384 void updateMemPorts();
385
386 /** Check if this address is a valid instruction address. */
387 bool validInstAddr(Addr addr) { return true; }
388
389 /** Check if this address is a valid data address. */
390 bool validDataAddr(Addr addr) { return true; }
391
392 /** Get instruction asid. */
393 int getInstAsid(unsigned tid)
394 { return regFile.miscRegs[tid].getInstAsid(); }
395
396 /** Get data asid. */
397 int getDataAsid(unsigned tid)
398 { return regFile.miscRegs[tid].getDataAsid(); }
399#else
400 /** Get instruction asid. */
401 int getInstAsid(unsigned tid)
402 { return thread[tid]->getInstAsid(); }
403
404 /** Get data asid. */
405 int getDataAsid(unsigned tid)
406 { return thread[tid]->getDataAsid(); }
407
408#endif
409
410 /** Register accessors. Index refers to the physical register index. */
411 uint64_t readIntReg(int reg_idx);
412
413 TheISA::FloatReg readFloatReg(int reg_idx);
414
415 TheISA::FloatReg readFloatReg(int reg_idx, int width);
416
417 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
418
419 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
420
421 void setIntReg(int reg_idx, uint64_t val);
422
423 void setFloatReg(int reg_idx, TheISA::FloatReg val);
424
425 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
426
427 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
428
429 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
430
431 uint64_t readArchIntReg(int reg_idx, unsigned tid);
432
433 float readArchFloatRegSingle(int reg_idx, unsigned tid);
434
435 double readArchFloatRegDouble(int reg_idx, unsigned tid);
436
437 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
438
439 /** Architectural register accessors. Looks up in the commit
440 * rename table to obtain the true physical index of the
441 * architected register first, then accesses that physical
442 * register.
443 */
444 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
445
446 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
447
448 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
449
450 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
451
452 /** Reads the commit PC of a specific thread. */
453 Addr readPC(unsigned tid);
454
455 /** Sets the commit PC of a specific thread. */
456 void setPC(Addr new_PC, unsigned tid);
457
458 /** Reads the commit micro PC of a specific thread. */
459 Addr readMicroPC(unsigned tid);
460
461 /** Sets the commmit micro PC of a specific thread. */
462 void setMicroPC(Addr new_microPC, unsigned tid);
463
464 /** Reads the next PC of a specific thread. */
465 Addr readNextPC(unsigned tid);
466
467 /** Sets the next PC of a specific thread. */
468 void setNextPC(Addr val, unsigned tid);
469
470 /** Reads the next NPC of a specific thread. */
471 Addr readNextNPC(unsigned tid);
472
473 /** Sets the next NPC of a specific thread. */
474 void setNextNPC(Addr val, unsigned tid);
475
476 /** Reads the commit next micro PC of a specific thread. */
477 Addr readNextMicroPC(unsigned tid);
478
479 /** Sets the commit next micro PC of a specific thread. */
480 void setNextMicroPC(Addr val, unsigned tid);
481
482 /** Function to add instruction onto the head of the list of the
483 * instructions. Used when new instructions are fetched.
484 */
485 ListIt addInst(DynInstPtr &inst);
486
487 /** Function to tell the CPU that an instruction has completed. */
488 void instDone(unsigned tid);
489
490 /** Add Instructions to the CPU Remove List*/
491 void addToRemoveList(DynInstPtr &inst);
492
493 /** Remove an instruction from the front end of the list. There's
494 * no restriction on location of the instruction.
495 */
496 void removeFrontInst(DynInstPtr &inst);
497
498 /** Remove all instructions that are not currently in the ROB.
499 * There's also an option to not squash delay slot instructions.*/
500 void removeInstsNotInROB(unsigned tid);
501
502 /** Remove all instructions younger than the given sequence number. */
503 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
504
505 /** Removes the instruction pointed to by the iterator. */
506 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
507
508 /** Cleans up all instructions on the remove list. */
509 void cleanUpRemovedInsts();
510
511 /** Debug function to print all instructions on the list. */
512 void dumpInsts();
513
514 public:
515 /** List of all the instructions in flight. */
516 std::list<DynInstPtr> instList;
517
518 /** List of all the instructions that will be removed at the end of this
519 * cycle.
520 */
521 std::queue<ListIt> removeList;
522
523#ifdef DEBUG
524 /** Debug structure to keep track of the sequence numbers still in
525 * flight.
526 */
527 std::set<InstSeqNum> snList;
528#endif
529
530 /** Records if instructions need to be removed this cycle due to
531 * being retired or squashed.
532 */
533 bool removeInstsThisCycle;
534
535 protected:
536 /** The fetch stage. */
537 typename CPUPolicy::Fetch fetch;
538
539 /** The decode stage. */
540 typename CPUPolicy::Decode decode;
541
542 /** The dispatch stage. */
543 typename CPUPolicy::Rename rename;
544
545 /** The issue/execute/writeback stages. */
546 typename CPUPolicy::IEW iew;
547
548 /** The commit stage. */
549 typename CPUPolicy::Commit commit;
550
551 /** The register file. */
552 typename CPUPolicy::RegFile regFile;
553
554 /** The free list. */
555 typename CPUPolicy::FreeList freeList;
556
557 /** The rename map. */
558 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
559
560 /** The commit rename map. */
561 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
562
563 /** The re-order buffer. */
564 typename CPUPolicy::ROB rob;
565
566 /** Active Threads List */
567 std::list<unsigned> activeThreads;
568
569 /** Integer Register Scoreboard */
570 Scoreboard scoreboard;
571
572 public:
573 /** Enum to give each stage a specific index, so when calling
574 * activateStage() or deactivateStage(), they can specify which stage
575 * is being activated/deactivated.
576 */
577 enum StageIdx {
578 FetchIdx,
579 DecodeIdx,
580 RenameIdx,
581 IEWIdx,
582 CommitIdx,
583 NumStages };
584
585 /** Typedefs from the Impl to get the structs that each of the
586 * time buffers should use.
587 */
588 typedef typename CPUPolicy::TimeStruct TimeStruct;
589
590 typedef typename CPUPolicy::FetchStruct FetchStruct;
591
592 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
593
594 typedef typename CPUPolicy::RenameStruct RenameStruct;
595
596 typedef typename CPUPolicy::IEWStruct IEWStruct;
597
598 /** The main time buffer to do backwards communication. */
599 TimeBuffer<TimeStruct> timeBuffer;
600
601 /** The fetch stage's instruction queue. */
602 TimeBuffer<FetchStruct> fetchQueue;
603
604 /** The decode stage's instruction queue. */
605 TimeBuffer<DecodeStruct> decodeQueue;
606
607 /** The rename stage's instruction queue. */
608 TimeBuffer<RenameStruct> renameQueue;
609
610 /** The IEW stage's instruction queue. */
611 TimeBuffer<IEWStruct> iewQueue;
612
613 private:
614 /** The activity recorder; used to tell if the CPU has any
615 * activity remaining or if it can go to idle and deschedule
616 * itself.
617 */
618 ActivityRecorder activityRec;
619
620 public:
621 /** Records that there was time buffer activity this cycle. */
622 void activityThisCycle() { activityRec.activity(); }
623
624 /** Changes a stage's status to active within the activity recorder. */
625 void activateStage(const StageIdx idx)
626 { activityRec.activateStage(idx); }
627
628 /** Changes a stage's status to inactive within the activity recorder. */
629 void deactivateStage(const StageIdx idx)
630 { activityRec.deactivateStage(idx); }
631
632 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
633 void wakeCPU();
634
635 /** Gets a free thread id. Use if thread ids change across system. */
636 int getFreeTid();
637
638 public:
639 /** Returns a pointer to a thread context. */
640 ThreadContext *tcBase(unsigned tid)
641 {
642 return thread[tid]->getTC();
643 }
644
645 /** The global sequence number counter. */
646 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
647
648#if USE_CHECKER
649 /** Pointer to the checker, which can dynamically verify
650 * instruction results at run time. This can be set to NULL if it
651 * is not being used.
652 */
653 Checker<DynInstPtr> *checker;
654#endif
655
656#if FULL_SYSTEM
657 /** Pointer to the system. */
658 System *system;
659
660 /** Pointer to physical memory. */
661 PhysicalMemory *physmem;
662#endif
663
664 /** Event to call process() on once draining has completed. */
665 Event *drainEvent;
666
667 /** Counter of how many stages have completed draining. */
668 int drainCount;
669
670 /** Pointers to all of the threads in the CPU. */
671 std::vector<Thread *> thread;
672
673 /** Whether or not the CPU should defer its registration. */
674 bool deferRegistration;
675
676 /** Is there a context switch pending? */
677 bool contextSwitch;
678
679 /** Threads Scheduled to Enter CPU */
680 std::list<int> cpuWaitList;
681
682 /** The cycle that the CPU was last running, used for statistics. */
683 Tick lastRunningCycle;
684
685 /** The cycle that the CPU was last activated by a new thread*/
686 Tick lastActivatedCycle;
687
688 /** Number of Threads CPU can process */
689 unsigned numThreads;
690
691 /** Mapping for system thread id to cpu id */
692 std::map<unsigned,unsigned> threadMap;
693
694 /** Available thread ids in the cpu*/
695 std::vector<unsigned> tids;
696
697 /** Stat for total number of times the CPU is descheduled. */
698 Stats::Scalar<> timesIdled;
699 /** Stat for total number of cycles the CPU spends descheduled. */
700 Stats::Scalar<> idleCycles;
701 /** Stat for the number of committed instructions per thread. */
702 Stats::Vector<> committedInsts;
703 /** Stat for the total number of committed instructions. */
704 Stats::Scalar<> totalCommittedInsts;
705 /** Stat for the CPI per thread. */
706 Stats::Formula cpi;
707 /** Stat for the total CPI. */
708 Stats::Formula totalCpi;
709 /** Stat for the IPC per thread. */
710 Stats::Formula ipc;
711 /** Stat for the total IPC. */
712 Stats::Formula totalIpc;
713};
714
715#endif // __CPU_O3_CPU_HH__
|