1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
|
45#include "cpu/activity.hh"
46#include "cpu/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;
70
71 BaseO3CPU(Params *params);
72
73 void regStats();
74
75 /** Sets this CPU's ID. */
76 void setCpuId(int id) { cpu_id = id; }
77
78 /** Reads this CPU's ID. */
79 int readCpuId() { return cpu_id; }
80
81 protected:
82 int cpu_id;
83};
84
85/**
86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages. The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93 public:
94 // Typedefs from the Impl here.
95 typedef typename Impl::CPUPol CPUPolicy;
96 typedef typename Impl::Params Params;
97 typedef typename Impl::DynInstPtr DynInstPtr;
98 typedef typename Impl::O3CPU O3CPU;
99
100 typedef O3ThreadState<Impl> Thread;
101
102 typedef typename std::list<DynInstPtr>::iterator ListIt;
103
104 friend class O3ThreadContext<Impl>;
105
106 public:
107 enum Status {
108 Running,
109 Idle,
110 Halted,
111 Blocked,
112 SwitchedOut
113 };
114
115#if FULL_SYSTEM
116 TheISA::ITB * itb;
117 TheISA::DTB * dtb;
118#endif
119
120 /** Overall CPU status. */
121 Status _status;
122
123 /** Per-thread status in CPU, used for SMT. */
124 Status _threadStatus[Impl::MaxThreads];
125
126 private:
127 class TickEvent : public Event
128 {
129 private:
130 /** Pointer to the CPU. */
131 FullO3CPU<Impl> *cpu;
132
133 public:
134 /** Constructs a tick event. */
135 TickEvent(FullO3CPU<Impl> *c);
136
137 /** Processes a tick event, calling tick() on the CPU. */
138 void process();
139 /** Returns the description of the tick event. */
140 const char *description();
141 };
142
143 /** The tick event used for scheduling CPU ticks. */
144 TickEvent tickEvent;
145
146 /** Schedule tick event, regardless of its current state. */
147 void scheduleTickEvent(int delay)
148 {
149 if (tickEvent.squashed())
150 tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
151 else if (!tickEvent.scheduled())
152 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
153 }
154
155 /** Unschedule tick event, regardless of its current state. */
156 void unscheduleTickEvent()
157 {
158 if (tickEvent.scheduled())
159 tickEvent.squash();
160 }
161
162 class ActivateThreadEvent : public Event
163 {
164 private:
165 /** Number of Thread to Activate */
166 int tid;
167
168 /** Pointer to the CPU. */
169 FullO3CPU<Impl> *cpu;
170
171 public:
172 /** Constructs the event. */
173 ActivateThreadEvent();
174
175 /** Initialize Event */
176 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
177
178 /** Processes the event, calling activateThread() on the CPU. */
179 void process();
180
181 /** Returns the description of the event. */
182 const char *description();
183 };
184
185 /** Schedule thread to activate , regardless of its current state. */
186 void scheduleActivateThreadEvent(int tid, int delay)
187 {
188 // Schedule thread to activate, regardless of its current state.
189 if (activateThreadEvent[tid].squashed())
190 activateThreadEvent[tid].
191 reschedule(nextCycle(curTick + cycles(delay)));
192 else if (!activateThreadEvent[tid].scheduled())
193 activateThreadEvent[tid].
194 schedule(nextCycle(curTick + cycles(delay)));
195 }
196
197 /** Unschedule actiavte thread event, regardless of its current state. */
198 void unscheduleActivateThreadEvent(int tid)
199 {
200 if (activateThreadEvent[tid].scheduled())
201 activateThreadEvent[tid].squash();
202 }
203
204 /** The tick event used for scheduling CPU ticks. */
205 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
206
207 class DeallocateContextEvent : public Event
208 {
209 private:
210 /** Number of Thread to deactivate */
211 int tid;
212
213 /** Should the thread be removed from the CPU? */
214 bool remove;
215
216 /** Pointer to the CPU. */
217 FullO3CPU<Impl> *cpu;
218
219 public:
220 /** Constructs the event. */
221 DeallocateContextEvent();
222
223 /** Initialize Event */
224 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
225
226 /** Processes the event, calling activateThread() on the CPU. */
227 void process();
228
229 /** Sets whether the thread should also be removed from the CPU. */
230 void setRemove(bool _remove) { remove = _remove; }
231
232 /** Returns the description of the event. */
233 const char *description();
234 };
235
236 /** Schedule cpu to deallocate thread context.*/
237 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
238 {
239 // Schedule thread to activate, regardless of its current state.
240 if (deallocateContextEvent[tid].squashed())
241 deallocateContextEvent[tid].
242 reschedule(nextCycle(curTick + cycles(delay)));
243 else if (!deallocateContextEvent[tid].scheduled())
244 deallocateContextEvent[tid].
245 schedule(nextCycle(curTick + cycles(delay)));
246 }
247
248 /** Unschedule thread deallocation in CPU */
249 void unscheduleDeallocateContextEvent(int tid)
250 {
251 if (deallocateContextEvent[tid].scheduled())
252 deallocateContextEvent[tid].squash();
253 }
254
255 /** The tick event used for scheduling CPU ticks. */
256 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
257
258 public:
259 /** Constructs a CPU with the given parameters. */
260 FullO3CPU(O3CPU *o3_cpu, Params *params);
261 /** Destructor. */
262 ~FullO3CPU();
263
264 /** Registers statistics. */
265 void fullCPURegStats();
266
267 /** Returns a specific port. */
268 Port *getPort(const std::string &if_name, int idx);
269
270 /** Ticks CPU, calling tick() on each stage, and checking the overall
271 * activity to see if the CPU should deschedule itself.
272 */
273 void tick();
274
275 /** Initialize the CPU */
276 void init();
277
278 /** Returns the Number of Active Threads in the CPU */
279 int numActiveThreads()
280 { return activeThreads.size(); }
281
282 /** Add Thread to Active Threads List */
283 void activateThread(unsigned tid);
284
285 /** Remove Thread from Active Threads List */
286 void deactivateThread(unsigned tid);
287
288 /** Setup CPU to insert a thread's context */
289 void insertThread(unsigned tid);
290
291 /** Remove all of a thread's context from CPU */
292 void removeThread(unsigned tid);
293
294 /** Count the Total Instructions Committed in the CPU. */
295 virtual Counter totalInstructions() const
296 {
297 Counter total(0);
298
299 for (int i=0; i < thread.size(); i++)
300 total += thread[i]->numInst;
301
302 return total;
303 }
304
305 /** Add Thread to Active Threads List. */
306 void activateContext(int tid, int delay);
307
308 /** Remove Thread from Active Threads List */
309 void suspendContext(int tid);
310
311 /** Remove Thread from Active Threads List &&
312 * Possibly Remove Thread Context from CPU.
313 */
314 bool deallocateContext(int tid, bool remove, int delay = 1);
315
316 /** Remove Thread from Active Threads List &&
317 * Remove Thread Context from CPU.
318 */
319 void haltContext(int tid);
320
321 /** Activate a Thread When CPU Resources are Available. */
322 void activateWhenReady(int tid);
323
324 /** Add or Remove a Thread Context in the CPU. */
325 void doContextSwitch();
326
327 /** Update The Order In Which We Process Threads. */
328 void updateThreadPriority();
329
330 /** Serialize state. */
331 virtual void serialize(std::ostream &os);
332
333 /** Unserialize from a checkpoint. */
334 virtual void unserialize(Checkpoint *cp, const std::string §ion);
335
336 public:
337 /** Executes a syscall on this cycle.
338 * ---------------------------------------
339 * Note: this is a virtual function. CPU-Specific
340 * functionality defined in derived classes
341 */
342 virtual void syscall(int tid) { panic("Unimplemented!"); }
343
344 /** Starts draining the CPU's pipeline of all instructions in
345 * order to stop all memory accesses. */
346 virtual unsigned int drain(Event *drain_event);
347
348 /** Resumes execution after a drain. */
349 virtual void resume();
350
351 /** Signals to this CPU that a stage has completed switching out. */
352 void signalDrained();
353
354 /** Switches out this CPU. */
355 virtual void switchOut();
356
357 /** Takes over from another CPU. */
358 virtual void takeOverFrom(BaseCPU *oldCPU);
359
360 /** Get the current instruction sequence number, and increment it. */
361 InstSeqNum getAndIncrementInstSeq()
362 { return globalSeqNum++; }
363
364#if FULL_SYSTEM
365 /** Update the Virt and Phys ports of all ThreadContexts to
366 * reflect change in memory connections. */
367 void updateMemPorts();
368
369 /** Check if this address is a valid instruction address. */
370 bool validInstAddr(Addr addr) { return true; }
371
372 /** Check if this address is a valid data address. */
373 bool validDataAddr(Addr addr) { return true; }
374
375 /** Get instruction asid. */
376 int getInstAsid(unsigned tid)
377 { return regFile.miscRegs[tid].getInstAsid(); }
378
379 /** Get data asid. */
380 int getDataAsid(unsigned tid)
381 { return regFile.miscRegs[tid].getDataAsid(); }
382#else
383 /** Get instruction asid. */
384 int getInstAsid(unsigned tid)
385 { return thread[tid]->getInstAsid(); }
386
387 /** Get data asid. */
388 int getDataAsid(unsigned tid)
389 { return thread[tid]->getDataAsid(); }
390
391#endif
392
393 /** Register accessors. Index refers to the physical register index. */
394 uint64_t readIntReg(int reg_idx);
395
396 TheISA::FloatReg readFloatReg(int reg_idx);
397
398 TheISA::FloatReg readFloatReg(int reg_idx, int width);
399
400 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
401
402 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
403
404 void setIntReg(int reg_idx, uint64_t val);
405
406 void setFloatReg(int reg_idx, TheISA::FloatReg val);
407
408 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
409
410 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
411
412 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
413
414 uint64_t readArchIntReg(int reg_idx, unsigned tid);
415
416 float readArchFloatRegSingle(int reg_idx, unsigned tid);
417
418 double readArchFloatRegDouble(int reg_idx, unsigned tid);
419
420 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
421
422 /** Architectural register accessors. Looks up in the commit
423 * rename table to obtain the true physical index of the
424 * architected register first, then accesses that physical
425 * register.
426 */
427 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
428
429 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
430
431 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
432
433 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
434
435 /** Reads the commit PC of a specific thread. */
436 uint64_t readPC(unsigned tid);
437
438 /** Sets the commit PC of a specific thread. */
439 void setPC(Addr new_PC, unsigned tid);
440
441 /** Reads the next PC of a specific thread. */
442 uint64_t readNextPC(unsigned tid);
443
444 /** Sets the next PC of a specific thread. */
445 void setNextPC(uint64_t val, unsigned tid);
446
447 /** Reads the next NPC of a specific thread. */
448 uint64_t readNextNPC(unsigned tid);
449
450 /** Sets the next NPC of a specific thread. */
451 void setNextNPC(uint64_t val, unsigned tid);
452
453 /** Function to add instruction onto the head of the list of the
454 * instructions. Used when new instructions are fetched.
455 */
456 ListIt addInst(DynInstPtr &inst);
457
458 /** Function to tell the CPU that an instruction has completed. */
459 void instDone(unsigned tid);
460
461 /** Add Instructions to the CPU Remove List*/
462 void addToRemoveList(DynInstPtr &inst);
463
464 /** Remove an instruction from the front end of the list. There's
465 * no restriction on location of the instruction.
466 */
467 void removeFrontInst(DynInstPtr &inst);
468
469 /** Remove all instructions that are not currently in the ROB.
470 * There's also an option to not squash delay slot instructions.*/
471 void removeInstsNotInROB(unsigned tid, bool squash_delay_slot,
472 const InstSeqNum &delay_slot_seq_num);
473
474 /** Remove all instructions younger than the given sequence number. */
475 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
476
477 /** Removes the instruction pointed to by the iterator. */
478 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
479
480 /** Cleans up all instructions on the remove list. */
481 void cleanUpRemovedInsts();
482
483 /** Debug function to print all instructions on the list. */
484 void dumpInsts();
485
486 public:
487 /** List of all the instructions in flight. */
488 std::list<DynInstPtr> instList;
489
490 /** List of all the instructions that will be removed at the end of this
491 * cycle.
492 */
493 std::queue<ListIt> removeList;
494
495#ifdef DEBUG
496 /** Debug structure to keep track of the sequence numbers still in
497 * flight.
498 */
499 std::set<InstSeqNum> snList;
500#endif
501
502 /** Records if instructions need to be removed this cycle due to
503 * being retired or squashed.
504 */
505 bool removeInstsThisCycle;
506
507 protected:
508 /** The fetch stage. */
509 typename CPUPolicy::Fetch fetch;
510
511 /** The decode stage. */
512 typename CPUPolicy::Decode decode;
513
514 /** The dispatch stage. */
515 typename CPUPolicy::Rename rename;
516
517 /** The issue/execute/writeback stages. */
518 typename CPUPolicy::IEW iew;
519
520 /** The commit stage. */
521 typename CPUPolicy::Commit commit;
522
523 /** The register file. */
524 typename CPUPolicy::RegFile regFile;
525
526 /** The free list. */
527 typename CPUPolicy::FreeList freeList;
528
529 /** The rename map. */
530 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
531
532 /** The commit rename map. */
533 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
534
535 /** The re-order buffer. */
536 typename CPUPolicy::ROB rob;
537
538 /** Active Threads List */
539 std::list<unsigned> activeThreads;
540
541 /** Integer Register Scoreboard */
542 Scoreboard scoreboard;
543
544 public:
545 /** Enum to give each stage a specific index, so when calling
546 * activateStage() or deactivateStage(), they can specify which stage
547 * is being activated/deactivated.
548 */
549 enum StageIdx {
550 FetchIdx,
551 DecodeIdx,
552 RenameIdx,
553 IEWIdx,
554 CommitIdx,
555 NumStages };
556
557 /** Typedefs from the Impl to get the structs that each of the
558 * time buffers should use.
559 */
560 typedef typename CPUPolicy::TimeStruct TimeStruct;
561
562 typedef typename CPUPolicy::FetchStruct FetchStruct;
563
564 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
565
566 typedef typename CPUPolicy::RenameStruct RenameStruct;
567
568 typedef typename CPUPolicy::IEWStruct IEWStruct;
569
570 /** The main time buffer to do backwards communication. */
571 TimeBuffer<TimeStruct> timeBuffer;
572
573 /** The fetch stage's instruction queue. */
574 TimeBuffer<FetchStruct> fetchQueue;
575
576 /** The decode stage's instruction queue. */
577 TimeBuffer<DecodeStruct> decodeQueue;
578
579 /** The rename stage's instruction queue. */
580 TimeBuffer<RenameStruct> renameQueue;
581
582 /** The IEW stage's instruction queue. */
583 TimeBuffer<IEWStruct> iewQueue;
584
585 private:
586 /** The activity recorder; used to tell if the CPU has any
587 * activity remaining or if it can go to idle and deschedule
588 * itself.
589 */
590 ActivityRecorder activityRec;
591
592 public:
593 /** Records that there was time buffer activity this cycle. */
594 void activityThisCycle() { activityRec.activity(); }
595
596 /** Changes a stage's status to active within the activity recorder. */
597 void activateStage(const StageIdx idx)
598 { activityRec.activateStage(idx); }
599
600 /** Changes a stage's status to inactive within the activity recorder. */
601 void deactivateStage(const StageIdx idx)
602 { activityRec.deactivateStage(idx); }
603
604 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
605 void wakeCPU();
606
607 /** Gets a free thread id. Use if thread ids change across system. */
608 int getFreeTid();
609
610 public:
611 /** Returns a pointer to a thread context. */
612 ThreadContext *tcBase(unsigned tid)
613 {
614 return thread[tid]->getTC();
615 }
616
617 /** The global sequence number counter. */
618 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
619
| 46#include "cpu/activity.hh"
47#include "cpu/base.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/o3/comm.hh"
50#include "cpu/o3/cpu_policy.hh"
51#include "cpu/o3/scoreboard.hh"
52#include "cpu/o3/thread_state.hh"
53//#include "cpu/o3/thread_context.hh"
54#include "sim/process.hh"
55
56template <class>
57class Checker;
58class ThreadContext;
59template <class>
60class O3ThreadContext;
61
62class Checkpoint;
63class MemObject;
64class Process;
65
66class BaseO3CPU : public BaseCPU
67{
68 //Stuff that's pretty ISA independent will go here.
69 public:
70 typedef BaseCPU::Params Params;
71
72 BaseO3CPU(Params *params);
73
74 void regStats();
75
76 /** Sets this CPU's ID. */
77 void setCpuId(int id) { cpu_id = id; }
78
79 /** Reads this CPU's ID. */
80 int readCpuId() { return cpu_id; }
81
82 protected:
83 int cpu_id;
84};
85
86/**
87 * FullO3CPU class, has each of the stages (fetch through commit)
88 * within it, as well as all of the time buffers between stages. The
89 * tick() function for the CPU is defined here.
90 */
91template <class Impl>
92class FullO3CPU : public BaseO3CPU
93{
94 public:
95 // Typedefs from the Impl here.
96 typedef typename Impl::CPUPol CPUPolicy;
97 typedef typename Impl::Params Params;
98 typedef typename Impl::DynInstPtr DynInstPtr;
99 typedef typename Impl::O3CPU O3CPU;
100
101 typedef O3ThreadState<Impl> Thread;
102
103 typedef typename std::list<DynInstPtr>::iterator ListIt;
104
105 friend class O3ThreadContext<Impl>;
106
107 public:
108 enum Status {
109 Running,
110 Idle,
111 Halted,
112 Blocked,
113 SwitchedOut
114 };
115
116#if FULL_SYSTEM
117 TheISA::ITB * itb;
118 TheISA::DTB * dtb;
119#endif
120
121 /** Overall CPU status. */
122 Status _status;
123
124 /** Per-thread status in CPU, used for SMT. */
125 Status _threadStatus[Impl::MaxThreads];
126
127 private:
128 class TickEvent : public Event
129 {
130 private:
131 /** Pointer to the CPU. */
132 FullO3CPU<Impl> *cpu;
133
134 public:
135 /** Constructs a tick event. */
136 TickEvent(FullO3CPU<Impl> *c);
137
138 /** Processes a tick event, calling tick() on the CPU. */
139 void process();
140 /** Returns the description of the tick event. */
141 const char *description();
142 };
143
144 /** The tick event used for scheduling CPU ticks. */
145 TickEvent tickEvent;
146
147 /** Schedule tick event, regardless of its current state. */
148 void scheduleTickEvent(int delay)
149 {
150 if (tickEvent.squashed())
151 tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
152 else if (!tickEvent.scheduled())
153 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
154 }
155
156 /** Unschedule tick event, regardless of its current state. */
157 void unscheduleTickEvent()
158 {
159 if (tickEvent.scheduled())
160 tickEvent.squash();
161 }
162
163 class ActivateThreadEvent : public Event
164 {
165 private:
166 /** Number of Thread to Activate */
167 int tid;
168
169 /** Pointer to the CPU. */
170 FullO3CPU<Impl> *cpu;
171
172 public:
173 /** Constructs the event. */
174 ActivateThreadEvent();
175
176 /** Initialize Event */
177 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
178
179 /** Processes the event, calling activateThread() on the CPU. */
180 void process();
181
182 /** Returns the description of the event. */
183 const char *description();
184 };
185
186 /** Schedule thread to activate , regardless of its current state. */
187 void scheduleActivateThreadEvent(int tid, int delay)
188 {
189 // Schedule thread to activate, regardless of its current state.
190 if (activateThreadEvent[tid].squashed())
191 activateThreadEvent[tid].
192 reschedule(nextCycle(curTick + cycles(delay)));
193 else if (!activateThreadEvent[tid].scheduled())
194 activateThreadEvent[tid].
195 schedule(nextCycle(curTick + cycles(delay)));
196 }
197
198 /** Unschedule actiavte thread event, regardless of its current state. */
199 void unscheduleActivateThreadEvent(int tid)
200 {
201 if (activateThreadEvent[tid].scheduled())
202 activateThreadEvent[tid].squash();
203 }
204
205 /** The tick event used for scheduling CPU ticks. */
206 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
207
208 class DeallocateContextEvent : public Event
209 {
210 private:
211 /** Number of Thread to deactivate */
212 int tid;
213
214 /** Should the thread be removed from the CPU? */
215 bool remove;
216
217 /** Pointer to the CPU. */
218 FullO3CPU<Impl> *cpu;
219
220 public:
221 /** Constructs the event. */
222 DeallocateContextEvent();
223
224 /** Initialize Event */
225 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
226
227 /** Processes the event, calling activateThread() on the CPU. */
228 void process();
229
230 /** Sets whether the thread should also be removed from the CPU. */
231 void setRemove(bool _remove) { remove = _remove; }
232
233 /** Returns the description of the event. */
234 const char *description();
235 };
236
237 /** Schedule cpu to deallocate thread context.*/
238 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
239 {
240 // Schedule thread to activate, regardless of its current state.
241 if (deallocateContextEvent[tid].squashed())
242 deallocateContextEvent[tid].
243 reschedule(nextCycle(curTick + cycles(delay)));
244 else if (!deallocateContextEvent[tid].scheduled())
245 deallocateContextEvent[tid].
246 schedule(nextCycle(curTick + cycles(delay)));
247 }
248
249 /** Unschedule thread deallocation in CPU */
250 void unscheduleDeallocateContextEvent(int tid)
251 {
252 if (deallocateContextEvent[tid].scheduled())
253 deallocateContextEvent[tid].squash();
254 }
255
256 /** The tick event used for scheduling CPU ticks. */
257 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
258
259 public:
260 /** Constructs a CPU with the given parameters. */
261 FullO3CPU(O3CPU *o3_cpu, Params *params);
262 /** Destructor. */
263 ~FullO3CPU();
264
265 /** Registers statistics. */
266 void fullCPURegStats();
267
268 /** Returns a specific port. */
269 Port *getPort(const std::string &if_name, int idx);
270
271 /** Ticks CPU, calling tick() on each stage, and checking the overall
272 * activity to see if the CPU should deschedule itself.
273 */
274 void tick();
275
276 /** Initialize the CPU */
277 void init();
278
279 /** Returns the Number of Active Threads in the CPU */
280 int numActiveThreads()
281 { return activeThreads.size(); }
282
283 /** Add Thread to Active Threads List */
284 void activateThread(unsigned tid);
285
286 /** Remove Thread from Active Threads List */
287 void deactivateThread(unsigned tid);
288
289 /** Setup CPU to insert a thread's context */
290 void insertThread(unsigned tid);
291
292 /** Remove all of a thread's context from CPU */
293 void removeThread(unsigned tid);
294
295 /** Count the Total Instructions Committed in the CPU. */
296 virtual Counter totalInstructions() const
297 {
298 Counter total(0);
299
300 for (int i=0; i < thread.size(); i++)
301 total += thread[i]->numInst;
302
303 return total;
304 }
305
306 /** Add Thread to Active Threads List. */
307 void activateContext(int tid, int delay);
308
309 /** Remove Thread from Active Threads List */
310 void suspendContext(int tid);
311
312 /** Remove Thread from Active Threads List &&
313 * Possibly Remove Thread Context from CPU.
314 */
315 bool deallocateContext(int tid, bool remove, int delay = 1);
316
317 /** Remove Thread from Active Threads List &&
318 * Remove Thread Context from CPU.
319 */
320 void haltContext(int tid);
321
322 /** Activate a Thread When CPU Resources are Available. */
323 void activateWhenReady(int tid);
324
325 /** Add or Remove a Thread Context in the CPU. */
326 void doContextSwitch();
327
328 /** Update The Order In Which We Process Threads. */
329 void updateThreadPriority();
330
331 /** Serialize state. */
332 virtual void serialize(std::ostream &os);
333
334 /** Unserialize from a checkpoint. */
335 virtual void unserialize(Checkpoint *cp, const std::string §ion);
336
337 public:
338 /** Executes a syscall on this cycle.
339 * ---------------------------------------
340 * Note: this is a virtual function. CPU-Specific
341 * functionality defined in derived classes
342 */
343 virtual void syscall(int tid) { panic("Unimplemented!"); }
344
345 /** Starts draining the CPU's pipeline of all instructions in
346 * order to stop all memory accesses. */
347 virtual unsigned int drain(Event *drain_event);
348
349 /** Resumes execution after a drain. */
350 virtual void resume();
351
352 /** Signals to this CPU that a stage has completed switching out. */
353 void signalDrained();
354
355 /** Switches out this CPU. */
356 virtual void switchOut();
357
358 /** Takes over from another CPU. */
359 virtual void takeOverFrom(BaseCPU *oldCPU);
360
361 /** Get the current instruction sequence number, and increment it. */
362 InstSeqNum getAndIncrementInstSeq()
363 { return globalSeqNum++; }
364
365#if FULL_SYSTEM
366 /** Update the Virt and Phys ports of all ThreadContexts to
367 * reflect change in memory connections. */
368 void updateMemPorts();
369
370 /** Check if this address is a valid instruction address. */
371 bool validInstAddr(Addr addr) { return true; }
372
373 /** Check if this address is a valid data address. */
374 bool validDataAddr(Addr addr) { return true; }
375
376 /** Get instruction asid. */
377 int getInstAsid(unsigned tid)
378 { return regFile.miscRegs[tid].getInstAsid(); }
379
380 /** Get data asid. */
381 int getDataAsid(unsigned tid)
382 { return regFile.miscRegs[tid].getDataAsid(); }
383#else
384 /** Get instruction asid. */
385 int getInstAsid(unsigned tid)
386 { return thread[tid]->getInstAsid(); }
387
388 /** Get data asid. */
389 int getDataAsid(unsigned tid)
390 { return thread[tid]->getDataAsid(); }
391
392#endif
393
394 /** Register accessors. Index refers to the physical register index. */
395 uint64_t readIntReg(int reg_idx);
396
397 TheISA::FloatReg readFloatReg(int reg_idx);
398
399 TheISA::FloatReg readFloatReg(int reg_idx, int width);
400
401 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
402
403 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
404
405 void setIntReg(int reg_idx, uint64_t val);
406
407 void setFloatReg(int reg_idx, TheISA::FloatReg val);
408
409 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
410
411 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
412
413 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
414
415 uint64_t readArchIntReg(int reg_idx, unsigned tid);
416
417 float readArchFloatRegSingle(int reg_idx, unsigned tid);
418
419 double readArchFloatRegDouble(int reg_idx, unsigned tid);
420
421 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
422
423 /** Architectural register accessors. Looks up in the commit
424 * rename table to obtain the true physical index of the
425 * architected register first, then accesses that physical
426 * register.
427 */
428 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
429
430 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
431
432 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
433
434 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
435
436 /** Reads the commit PC of a specific thread. */
437 uint64_t readPC(unsigned tid);
438
439 /** Sets the commit PC of a specific thread. */
440 void setPC(Addr new_PC, unsigned tid);
441
442 /** Reads the next PC of a specific thread. */
443 uint64_t readNextPC(unsigned tid);
444
445 /** Sets the next PC of a specific thread. */
446 void setNextPC(uint64_t val, unsigned tid);
447
448 /** Reads the next NPC of a specific thread. */
449 uint64_t readNextNPC(unsigned tid);
450
451 /** Sets the next NPC of a specific thread. */
452 void setNextNPC(uint64_t val, unsigned tid);
453
454 /** Function to add instruction onto the head of the list of the
455 * instructions. Used when new instructions are fetched.
456 */
457 ListIt addInst(DynInstPtr &inst);
458
459 /** Function to tell the CPU that an instruction has completed. */
460 void instDone(unsigned tid);
461
462 /** Add Instructions to the CPU Remove List*/
463 void addToRemoveList(DynInstPtr &inst);
464
465 /** Remove an instruction from the front end of the list. There's
466 * no restriction on location of the instruction.
467 */
468 void removeFrontInst(DynInstPtr &inst);
469
470 /** Remove all instructions that are not currently in the ROB.
471 * There's also an option to not squash delay slot instructions.*/
472 void removeInstsNotInROB(unsigned tid, bool squash_delay_slot,
473 const InstSeqNum &delay_slot_seq_num);
474
475 /** Remove all instructions younger than the given sequence number. */
476 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
477
478 /** Removes the instruction pointed to by the iterator. */
479 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
480
481 /** Cleans up all instructions on the remove list. */
482 void cleanUpRemovedInsts();
483
484 /** Debug function to print all instructions on the list. */
485 void dumpInsts();
486
487 public:
488 /** List of all the instructions in flight. */
489 std::list<DynInstPtr> instList;
490
491 /** List of all the instructions that will be removed at the end of this
492 * cycle.
493 */
494 std::queue<ListIt> removeList;
495
496#ifdef DEBUG
497 /** Debug structure to keep track of the sequence numbers still in
498 * flight.
499 */
500 std::set<InstSeqNum> snList;
501#endif
502
503 /** Records if instructions need to be removed this cycle due to
504 * being retired or squashed.
505 */
506 bool removeInstsThisCycle;
507
508 protected:
509 /** The fetch stage. */
510 typename CPUPolicy::Fetch fetch;
511
512 /** The decode stage. */
513 typename CPUPolicy::Decode decode;
514
515 /** The dispatch stage. */
516 typename CPUPolicy::Rename rename;
517
518 /** The issue/execute/writeback stages. */
519 typename CPUPolicy::IEW iew;
520
521 /** The commit stage. */
522 typename CPUPolicy::Commit commit;
523
524 /** The register file. */
525 typename CPUPolicy::RegFile regFile;
526
527 /** The free list. */
528 typename CPUPolicy::FreeList freeList;
529
530 /** The rename map. */
531 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
532
533 /** The commit rename map. */
534 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
535
536 /** The re-order buffer. */
537 typename CPUPolicy::ROB rob;
538
539 /** Active Threads List */
540 std::list<unsigned> activeThreads;
541
542 /** Integer Register Scoreboard */
543 Scoreboard scoreboard;
544
545 public:
546 /** Enum to give each stage a specific index, so when calling
547 * activateStage() or deactivateStage(), they can specify which stage
548 * is being activated/deactivated.
549 */
550 enum StageIdx {
551 FetchIdx,
552 DecodeIdx,
553 RenameIdx,
554 IEWIdx,
555 CommitIdx,
556 NumStages };
557
558 /** Typedefs from the Impl to get the structs that each of the
559 * time buffers should use.
560 */
561 typedef typename CPUPolicy::TimeStruct TimeStruct;
562
563 typedef typename CPUPolicy::FetchStruct FetchStruct;
564
565 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
566
567 typedef typename CPUPolicy::RenameStruct RenameStruct;
568
569 typedef typename CPUPolicy::IEWStruct IEWStruct;
570
571 /** The main time buffer to do backwards communication. */
572 TimeBuffer<TimeStruct> timeBuffer;
573
574 /** The fetch stage's instruction queue. */
575 TimeBuffer<FetchStruct> fetchQueue;
576
577 /** The decode stage's instruction queue. */
578 TimeBuffer<DecodeStruct> decodeQueue;
579
580 /** The rename stage's instruction queue. */
581 TimeBuffer<RenameStruct> renameQueue;
582
583 /** The IEW stage's instruction queue. */
584 TimeBuffer<IEWStruct> iewQueue;
585
586 private:
587 /** The activity recorder; used to tell if the CPU has any
588 * activity remaining or if it can go to idle and deschedule
589 * itself.
590 */
591 ActivityRecorder activityRec;
592
593 public:
594 /** Records that there was time buffer activity this cycle. */
595 void activityThisCycle() { activityRec.activity(); }
596
597 /** Changes a stage's status to active within the activity recorder. */
598 void activateStage(const StageIdx idx)
599 { activityRec.activateStage(idx); }
600
601 /** Changes a stage's status to inactive within the activity recorder. */
602 void deactivateStage(const StageIdx idx)
603 { activityRec.deactivateStage(idx); }
604
605 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
606 void wakeCPU();
607
608 /** Gets a free thread id. Use if thread ids change across system. */
609 int getFreeTid();
610
611 public:
612 /** Returns a pointer to a thread context. */
613 ThreadContext *tcBase(unsigned tid)
614 {
615 return thread[tid]->getTC();
616 }
617
618 /** The global sequence number counter. */
619 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
620
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