1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/isa_traits.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "cpu/activity.hh" 46#include "cpu/base.hh" 47#include "cpu/simple_thread.hh" 48#include "cpu/o3/comm.hh" 49#include "cpu/o3/cpu_policy.hh" 50#include "cpu/o3/scoreboard.hh" 51#include "cpu/o3/thread_state.hh" 52//#include "cpu/o3/thread_context.hh" 53#include "sim/process.hh" 54 55template <class> 56class Checker; 57class ThreadContext; 58template <class> 59class O3ThreadContext;
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/isa_traits.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "cpu/activity.hh" 46#include "cpu/base.hh" 47#include "cpu/simple_thread.hh" 48#include "cpu/o3/comm.hh" 49#include "cpu/o3/cpu_policy.hh" 50#include "cpu/o3/scoreboard.hh" 51#include "cpu/o3/thread_state.hh" 52//#include "cpu/o3/thread_context.hh" 53#include "sim/process.hh" 54 55template <class> 56class Checker; 57class ThreadContext; 58template <class> 59class O3ThreadContext;
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60 61class Checkpoint;
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62class MemObject; 63class Process; 64 65class BaseO3CPU : public BaseCPU 66{ 67 //Stuff that's pretty ISA independent will go here. 68 public: 69 typedef BaseCPU::Params Params; 70 71 BaseO3CPU(Params *params); 72 73 void regStats(); 74 75 /** Sets this CPU's ID. */ 76 void setCpuId(int id) { cpu_id = id; } 77 78 /** Reads this CPU's ID. */ 79 int readCpuId() { return cpu_id; } 80 81 protected: 82 int cpu_id; 83}; 84 85/** 86 * FullO3CPU class, has each of the stages (fetch through commit) 87 * within it, as well as all of the time buffers between stages. The 88 * tick() function for the CPU is defined here. 89 */ 90template <class Impl> 91class FullO3CPU : public BaseO3CPU 92{ 93 public: 94 typedef TheISA::FloatReg FloatReg; 95 typedef TheISA::FloatRegBits FloatRegBits; 96 97 // Typedefs from the Impl here. 98 typedef typename Impl::CPUPol CPUPolicy; 99 typedef typename Impl::Params Params; 100 typedef typename Impl::DynInstPtr DynInstPtr; 101 102 typedef O3ThreadState<Impl> Thread; 103 104 typedef typename std::list<DynInstPtr>::iterator ListIt; 105 106 friend class O3ThreadContext<Impl>; 107 108 public: 109 enum Status { 110 Running, 111 Idle, 112 Halted, 113 Blocked, 114 SwitchedOut 115 }; 116 117 /** Overall CPU status. */ 118 Status _status; 119 120 /** Per-thread status in CPU, used for SMT. */ 121 Status _threadStatus[Impl::MaxThreads]; 122 123 private: 124 class TickEvent : public Event 125 { 126 private: 127 /** Pointer to the CPU. */ 128 FullO3CPU<Impl> *cpu; 129 130 public: 131 /** Constructs a tick event. */ 132 TickEvent(FullO3CPU<Impl> *c); 133 134 /** Processes a tick event, calling tick() on the CPU. */ 135 void process(); 136 /** Returns the description of the tick event. */ 137 const char *description(); 138 }; 139 140 /** The tick event used for scheduling CPU ticks. */ 141 TickEvent tickEvent; 142 143 /** Schedule tick event, regardless of its current state. */ 144 void scheduleTickEvent(int delay) 145 { 146 if (tickEvent.squashed()) 147 tickEvent.reschedule(curTick + cycles(delay)); 148 else if (!tickEvent.scheduled()) 149 tickEvent.schedule(curTick + cycles(delay)); 150 } 151 152 /** Unschedule tick event, regardless of its current state. */ 153 void unscheduleTickEvent() 154 { 155 if (tickEvent.scheduled()) 156 tickEvent.squash(); 157 } 158 159 class ActivateThreadEvent : public Event 160 { 161 private: 162 /** Number of Thread to Activate */ 163 int tid; 164 165 /** Pointer to the CPU. */ 166 FullO3CPU<Impl> *cpu; 167 168 public: 169 /** Constructs the event. */ 170 ActivateThreadEvent(); 171 172 /** Initialize Event */ 173 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 174 175 /** Processes the event, calling activateThread() on the CPU. */ 176 void process(); 177 178 /** Returns the description of the event. */ 179 const char *description(); 180 }; 181 182 /** Schedule thread to activate , regardless of its current state. */ 183 void scheduleActivateThreadEvent(int tid, int delay) 184 { 185 // Schedule thread to activate, regardless of its current state. 186 if (activateThreadEvent[tid].squashed()) 187 activateThreadEvent[tid].reschedule(curTick + cycles(delay)); 188 else if (!activateThreadEvent[tid].scheduled()) 189 activateThreadEvent[tid].schedule(curTick + cycles(delay)); 190 } 191 192 /** Unschedule actiavte thread event, regardless of its current state. */ 193 void unscheduleActivateThreadEvent(int tid) 194 { 195 if (activateThreadEvent[tid].scheduled()) 196 activateThreadEvent[tid].squash(); 197 } 198 199 /** The tick event used for scheduling CPU ticks. */ 200 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 201
| 60class MemObject; 61class Process; 62 63class BaseO3CPU : public BaseCPU 64{ 65 //Stuff that's pretty ISA independent will go here. 66 public: 67 typedef BaseCPU::Params Params; 68 69 BaseO3CPU(Params *params); 70 71 void regStats(); 72 73 /** Sets this CPU's ID. */ 74 void setCpuId(int id) { cpu_id = id; } 75 76 /** Reads this CPU's ID. */ 77 int readCpuId() { return cpu_id; } 78 79 protected: 80 int cpu_id; 81}; 82 83/** 84 * FullO3CPU class, has each of the stages (fetch through commit) 85 * within it, as well as all of the time buffers between stages. The 86 * tick() function for the CPU is defined here. 87 */ 88template <class Impl> 89class FullO3CPU : public BaseO3CPU 90{ 91 public: 92 typedef TheISA::FloatReg FloatReg; 93 typedef TheISA::FloatRegBits FloatRegBits; 94 95 // Typedefs from the Impl here. 96 typedef typename Impl::CPUPol CPUPolicy; 97 typedef typename Impl::Params Params; 98 typedef typename Impl::DynInstPtr DynInstPtr; 99 100 typedef O3ThreadState<Impl> Thread; 101 102 typedef typename std::list<DynInstPtr>::iterator ListIt; 103 104 friend class O3ThreadContext<Impl>; 105 106 public: 107 enum Status { 108 Running, 109 Idle, 110 Halted, 111 Blocked, 112 SwitchedOut 113 }; 114 115 /** Overall CPU status. */ 116 Status _status; 117 118 /** Per-thread status in CPU, used for SMT. */ 119 Status _threadStatus[Impl::MaxThreads]; 120 121 private: 122 class TickEvent : public Event 123 { 124 private: 125 /** Pointer to the CPU. */ 126 FullO3CPU<Impl> *cpu; 127 128 public: 129 /** Constructs a tick event. */ 130 TickEvent(FullO3CPU<Impl> *c); 131 132 /** Processes a tick event, calling tick() on the CPU. */ 133 void process(); 134 /** Returns the description of the tick event. */ 135 const char *description(); 136 }; 137 138 /** The tick event used for scheduling CPU ticks. */ 139 TickEvent tickEvent; 140 141 /** Schedule tick event, regardless of its current state. */ 142 void scheduleTickEvent(int delay) 143 { 144 if (tickEvent.squashed()) 145 tickEvent.reschedule(curTick + cycles(delay)); 146 else if (!tickEvent.scheduled()) 147 tickEvent.schedule(curTick + cycles(delay)); 148 } 149 150 /** Unschedule tick event, regardless of its current state. */ 151 void unscheduleTickEvent() 152 { 153 if (tickEvent.scheduled()) 154 tickEvent.squash(); 155 } 156 157 class ActivateThreadEvent : public Event 158 { 159 private: 160 /** Number of Thread to Activate */ 161 int tid; 162 163 /** Pointer to the CPU. */ 164 FullO3CPU<Impl> *cpu; 165 166 public: 167 /** Constructs the event. */ 168 ActivateThreadEvent(); 169 170 /** Initialize Event */ 171 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 172 173 /** Processes the event, calling activateThread() on the CPU. */ 174 void process(); 175 176 /** Returns the description of the event. */ 177 const char *description(); 178 }; 179 180 /** Schedule thread to activate , regardless of its current state. */ 181 void scheduleActivateThreadEvent(int tid, int delay) 182 { 183 // Schedule thread to activate, regardless of its current state. 184 if (activateThreadEvent[tid].squashed()) 185 activateThreadEvent[tid].reschedule(curTick + cycles(delay)); 186 else if (!activateThreadEvent[tid].scheduled()) 187 activateThreadEvent[tid].schedule(curTick + cycles(delay)); 188 } 189 190 /** Unschedule actiavte thread event, regardless of its current state. */ 191 void unscheduleActivateThreadEvent(int tid) 192 { 193 if (activateThreadEvent[tid].scheduled()) 194 activateThreadEvent[tid].squash(); 195 } 196 197 /** The tick event used for scheduling CPU ticks. */ 198 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 199
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| 200 class DeallocateContextEvent : public Event 201 { 202 private: 203 /** Number of Thread to Activate */ 204 int tid; 205 206 /** Pointer to the CPU. */ 207 FullO3CPU<Impl> *cpu; 208 209 public: 210 /** Constructs the event. */ 211 DeallocateContextEvent(); 212 213 /** Initialize Event */ 214 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 215 216 /** Processes the event, calling activateThread() on the CPU. */ 217 void process(); 218 219 /** Returns the description of the event. */ 220 const char *description(); 221 }; 222 223 /** Schedule cpu to deallocate thread context.*/ 224 void scheduleDeallocateContextEvent(int tid, int delay) 225 { 226 // Schedule thread to activate, regardless of its current state. 227 if (deallocateContextEvent[tid].squashed()) 228 deallocateContextEvent[tid].reschedule(curTick + cycles(delay)); 229 else if (!deallocateContextEvent[tid].scheduled()) 230 deallocateContextEvent[tid].schedule(curTick + cycles(delay)); 231 } 232 233 /** Unschedule thread deallocation in CPU */ 234 void unscheduleDeallocateContextEvent(int tid) 235 { 236 if (deallocateContextEvent[tid].scheduled()) 237 deallocateContextEvent[tid].squash(); 238 } 239 240 /** The tick event used for scheduling CPU ticks. */ 241 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 242
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202 public: 203 /** Constructs a CPU with the given parameters. */ 204 FullO3CPU(Params *params); 205 /** Destructor. */ 206 ~FullO3CPU(); 207 208 /** Registers statistics. */ 209 void fullCPURegStats(); 210
| 243 public: 244 /** Constructs a CPU with the given parameters. */ 245 FullO3CPU(Params *params); 246 /** Destructor. */ 247 ~FullO3CPU(); 248 249 /** Registers statistics. */ 250 void fullCPURegStats(); 251
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211 /** Returns a specific port. */ 212 Port *getPort(const std::string &if_name, int idx); 213
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214 /** Ticks CPU, calling tick() on each stage, and checking the overall 215 * activity to see if the CPU should deschedule itself. 216 */ 217 void tick(); 218 219 /** Initialize the CPU */ 220 void init(); 221 222 /** Returns the Number of Active Threads in the CPU */ 223 int numActiveThreads() 224 { return activeThreads.size(); } 225 226 /** Add Thread to Active Threads List */
| 252 /** Ticks CPU, calling tick() on each stage, and checking the overall 253 * activity to see if the CPU should deschedule itself. 254 */ 255 void tick(); 256 257 /** Initialize the CPU */ 258 void init(); 259 260 /** Returns the Number of Active Threads in the CPU */ 261 int numActiveThreads() 262 { return activeThreads.size(); } 263 264 /** Add Thread to Active Threads List */
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227 void activateThread(unsigned int tid);
| 265 void activateThread(unsigned tid);
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228
| 266
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| 267 /** Remove Thread from Active Threads List */ 268 void deactivateThread(unsigned tid); 269
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229 /** Setup CPU to insert a thread's context */ 230 void insertThread(unsigned tid); 231 232 /** Remove all of a thread's context from CPU */ 233 void removeThread(unsigned tid); 234 235 /** Count the Total Instructions Committed in the CPU. */ 236 virtual Counter totalInstructions() const 237 { 238 Counter total(0); 239 240 for (int i=0; i < thread.size(); i++) 241 total += thread[i]->numInst; 242 243 return total; 244 } 245 246 /** Add Thread to Active Threads List. */ 247 void activateContext(int tid, int delay); 248 249 /** Remove Thread from Active Threads List */ 250 void suspendContext(int tid); 251 252 /** Remove Thread from Active Threads List && 253 * Remove Thread Context from CPU. 254 */
| 270 /** Setup CPU to insert a thread's context */ 271 void insertThread(unsigned tid); 272 273 /** Remove all of a thread's context from CPU */ 274 void removeThread(unsigned tid); 275 276 /** Count the Total Instructions Committed in the CPU. */ 277 virtual Counter totalInstructions() const 278 { 279 Counter total(0); 280 281 for (int i=0; i < thread.size(); i++) 282 total += thread[i]->numInst; 283 284 return total; 285 } 286 287 /** Add Thread to Active Threads List. */ 288 void activateContext(int tid, int delay); 289 290 /** Remove Thread from Active Threads List */ 291 void suspendContext(int tid); 292 293 /** Remove Thread from Active Threads List && 294 * Remove Thread Context from CPU. 295 */
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255 void deallocateContext(int tid);
| 296 void deallocateContext(int tid, int delay = 1);
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256 257 /** Remove Thread from Active Threads List && 258 * Remove Thread Context from CPU. 259 */ 260 void haltContext(int tid); 261 262 /** Activate a Thread When CPU Resources are Available. */ 263 void activateWhenReady(int tid); 264 265 /** Add or Remove a Thread Context in the CPU. */ 266 void doContextSwitch(); 267 268 /** Update The Order In Which We Process Threads. */ 269 void updateThreadPriority(); 270
| 297 298 /** Remove Thread from Active Threads List && 299 * Remove Thread Context from CPU. 300 */ 301 void haltContext(int tid); 302 303 /** Activate a Thread When CPU Resources are Available. */ 304 void activateWhenReady(int tid); 305 306 /** Add or Remove a Thread Context in the CPU. */ 307 void doContextSwitch(); 308 309 /** Update The Order In Which We Process Threads. */ 310 void updateThreadPriority(); 311
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271 /** Serialize state. */ 272 virtual void serialize(std::ostream &os); 273 274 /** Unserialize from a checkpoint. */ 275 virtual void unserialize(Checkpoint *cp, const std::string §ion); 276 277 public:
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278 /** Executes a syscall on this cycle. 279 * --------------------------------------- 280 * Note: this is a virtual function. CPU-Specific 281 * functionality defined in derived classes 282 */ 283 virtual void syscall(int tid) { panic("Unimplemented!"); } 284
| 312 /** Executes a syscall on this cycle. 313 * --------------------------------------- 314 * Note: this is a virtual function. CPU-Specific 315 * functionality defined in derived classes 316 */ 317 virtual void syscall(int tid) { panic("Unimplemented!"); } 318
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285 /** Starts draining the CPU's pipeline of all instructions in 286 * order to stop all memory accesses. */ 287 virtual bool drain(Event *drain_event);
| 319 /** Switches out this CPU. */ 320 void switchOut();
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288
| 321
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289 /** Resumes execution after a drain. */ 290 virtual void resume(); 291
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292 /** Signals to this CPU that a stage has completed switching out. */
| 322 /** Signals to this CPU that a stage has completed switching out. */
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293 void signalDrained();
| 323 void signalSwitched();
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294
| 324
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295 /** Switches out this CPU. */ 296 virtual void switchOut(); 297
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298 /** Takes over from another CPU. */
| 325 /** Takes over from another CPU. */
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299 virtual void takeOverFrom(BaseCPU *oldCPU);
| 326 void takeOverFrom(BaseCPU *oldCPU);
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300 301 /** Get the current instruction sequence number, and increment it. */ 302 InstSeqNum getAndIncrementInstSeq() 303 { return globalSeqNum++; } 304 305#if FULL_SYSTEM 306 /** Check if this address is a valid instruction address. */ 307 bool validInstAddr(Addr addr) { return true; } 308 309 /** Check if this address is a valid data address. */ 310 bool validDataAddr(Addr addr) { return true; } 311 312 /** Get instruction asid. */ 313 int getInstAsid(unsigned tid) 314 { return regFile.miscRegs[tid].getInstAsid(); } 315 316 /** Get data asid. */ 317 int getDataAsid(unsigned tid) 318 { return regFile.miscRegs[tid].getDataAsid(); } 319#else 320 /** Get instruction asid. */ 321 int getInstAsid(unsigned tid) 322 { return thread[tid]->getInstAsid(); } 323 324 /** Get data asid. */ 325 int getDataAsid(unsigned tid) 326 { return thread[tid]->getDataAsid(); } 327 328#endif 329 330 /** Register accessors. Index refers to the physical register index. */ 331 uint64_t readIntReg(int reg_idx); 332 333 FloatReg readFloatReg(int reg_idx); 334 335 FloatReg readFloatReg(int reg_idx, int width); 336 337 FloatRegBits readFloatRegBits(int reg_idx); 338 339 FloatRegBits readFloatRegBits(int reg_idx, int width); 340 341 void setIntReg(int reg_idx, uint64_t val); 342 343 void setFloatReg(int reg_idx, FloatReg val); 344 345 void setFloatReg(int reg_idx, FloatReg val, int width); 346 347 void setFloatRegBits(int reg_idx, FloatRegBits val); 348 349 void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 350 351 uint64_t readArchIntReg(int reg_idx, unsigned tid); 352 353 float readArchFloatRegSingle(int reg_idx, unsigned tid); 354 355 double readArchFloatRegDouble(int reg_idx, unsigned tid); 356 357 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 358 359 /** Architectural register accessors. Looks up in the commit 360 * rename table to obtain the true physical index of the 361 * architected register first, then accesses that physical 362 * register. 363 */ 364 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 365 366 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 367 368 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 369 370 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 371 372 /** Reads the commit PC of a specific thread. */ 373 uint64_t readPC(unsigned tid); 374 375 /** Sets the commit PC of a specific thread. */ 376 void setPC(Addr new_PC, unsigned tid); 377 378 /** Reads the next PC of a specific thread. */ 379 uint64_t readNextPC(unsigned tid); 380 381 /** Sets the next PC of a specific thread. */ 382 void setNextPC(uint64_t val, unsigned tid); 383 384 /** Reads the next NPC of a specific thread. */ 385 uint64_t readNextNPC(unsigned tid); 386 387 /** Sets the next NPC of a specific thread. */ 388 void setNextNPC(uint64_t val, unsigned tid); 389 390 /** Function to add instruction onto the head of the list of the 391 * instructions. Used when new instructions are fetched. 392 */ 393 ListIt addInst(DynInstPtr &inst); 394 395 /** Function to tell the CPU that an instruction has completed. */ 396 void instDone(unsigned tid); 397 398 /** Add Instructions to the CPU Remove List*/ 399 void addToRemoveList(DynInstPtr &inst); 400 401 /** Remove an instruction from the front end of the list. There's 402 * no restriction on location of the instruction. 403 */ 404 void removeFrontInst(DynInstPtr &inst); 405 406 /** Remove all instructions that are not currently in the ROB. */ 407 void removeInstsNotInROB(unsigned tid); 408 409 /** Remove all instructions younger than the given sequence number. */ 410 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 411 412 /** Removes the instruction pointed to by the iterator. */ 413 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 414 415 /** Cleans up all instructions on the remove list. */ 416 void cleanUpRemovedInsts(); 417 418 /** Debug function to print all instructions on the list. */ 419 void dumpInsts(); 420 421 public: 422 /** List of all the instructions in flight. */ 423 std::list<DynInstPtr> instList; 424 425 /** List of all the instructions that will be removed at the end of this 426 * cycle. 427 */ 428 std::queue<ListIt> removeList; 429 430#ifdef DEBUG 431 /** Debug structure to keep track of the sequence numbers still in 432 * flight. 433 */ 434 std::set<InstSeqNum> snList; 435#endif 436 437 /** Records if instructions need to be removed this cycle due to 438 * being retired or squashed. 439 */ 440 bool removeInstsThisCycle; 441 442 protected: 443 /** The fetch stage. */ 444 typename CPUPolicy::Fetch fetch; 445 446 /** The decode stage. */ 447 typename CPUPolicy::Decode decode; 448 449 /** The dispatch stage. */ 450 typename CPUPolicy::Rename rename; 451 452 /** The issue/execute/writeback stages. */ 453 typename CPUPolicy::IEW iew; 454 455 /** The commit stage. */ 456 typename CPUPolicy::Commit commit; 457 458 /** The register file. */ 459 typename CPUPolicy::RegFile regFile; 460 461 /** The free list. */ 462 typename CPUPolicy::FreeList freeList; 463 464 /** The rename map. */ 465 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 466 467 /** The commit rename map. */ 468 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 469 470 /** The re-order buffer. */ 471 typename CPUPolicy::ROB rob; 472 473 /** Active Threads List */ 474 std::list<unsigned> activeThreads; 475 476 /** Integer Register Scoreboard */ 477 Scoreboard scoreboard; 478 479 public: 480 /** Enum to give each stage a specific index, so when calling 481 * activateStage() or deactivateStage(), they can specify which stage 482 * is being activated/deactivated. 483 */ 484 enum StageIdx { 485 FetchIdx, 486 DecodeIdx, 487 RenameIdx, 488 IEWIdx, 489 CommitIdx, 490 NumStages }; 491 492 /** Typedefs from the Impl to get the structs that each of the 493 * time buffers should use. 494 */ 495 typedef typename CPUPolicy::TimeStruct TimeStruct; 496 497 typedef typename CPUPolicy::FetchStruct FetchStruct; 498 499 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 500 501 typedef typename CPUPolicy::RenameStruct RenameStruct; 502 503 typedef typename CPUPolicy::IEWStruct IEWStruct; 504 505 /** The main time buffer to do backwards communication. */ 506 TimeBuffer<TimeStruct> timeBuffer; 507 508 /** The fetch stage's instruction queue. */ 509 TimeBuffer<FetchStruct> fetchQueue; 510 511 /** The decode stage's instruction queue. */ 512 TimeBuffer<DecodeStruct> decodeQueue; 513 514 /** The rename stage's instruction queue. */ 515 TimeBuffer<RenameStruct> renameQueue; 516 517 /** The IEW stage's instruction queue. */ 518 TimeBuffer<IEWStruct> iewQueue; 519 520 private: 521 /** The activity recorder; used to tell if the CPU has any 522 * activity remaining or if it can go to idle and deschedule 523 * itself. 524 */ 525 ActivityRecorder activityRec; 526 527 public: 528 /** Records that there was time buffer activity this cycle. */ 529 void activityThisCycle() { activityRec.activity(); } 530 531 /** Changes a stage's status to active within the activity recorder. */ 532 void activateStage(const StageIdx idx) 533 { activityRec.activateStage(idx); } 534 535 /** Changes a stage's status to inactive within the activity recorder. */ 536 void deactivateStage(const StageIdx idx) 537 { activityRec.deactivateStage(idx); } 538 539 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 540 void wakeCPU(); 541 542 /** Gets a free thread id. Use if thread ids change across system. */ 543 int getFreeTid(); 544 545 public: 546 /** Returns a pointer to a thread context. */ 547 ThreadContext *tcBase(unsigned tid) 548 { 549 return thread[tid]->getTC(); 550 } 551 552 /** The global sequence number counter. */ 553 InstSeqNum globalSeqNum; 554 555 /** Pointer to the checker, which can dynamically verify 556 * instruction results at run time. This can be set to NULL if it 557 * is not being used. 558 */ 559 Checker<DynInstPtr> *checker; 560 561#if FULL_SYSTEM 562 /** Pointer to the system. */ 563 System *system; 564 565 /** Pointer to physical memory. */ 566 PhysicalMemory *physmem; 567#endif 568 569 /** Pointer to memory. */ 570 MemObject *mem; 571
| 327 328 /** Get the current instruction sequence number, and increment it. */ 329 InstSeqNum getAndIncrementInstSeq() 330 { return globalSeqNum++; } 331 332#if FULL_SYSTEM 333 /** Check if this address is a valid instruction address. */ 334 bool validInstAddr(Addr addr) { return true; } 335 336 /** Check if this address is a valid data address. */ 337 bool validDataAddr(Addr addr) { return true; } 338 339 /** Get instruction asid. */ 340 int getInstAsid(unsigned tid) 341 { return regFile.miscRegs[tid].getInstAsid(); } 342 343 /** Get data asid. */ 344 int getDataAsid(unsigned tid) 345 { return regFile.miscRegs[tid].getDataAsid(); } 346#else 347 /** Get instruction asid. */ 348 int getInstAsid(unsigned tid) 349 { return thread[tid]->getInstAsid(); } 350 351 /** Get data asid. */ 352 int getDataAsid(unsigned tid) 353 { return thread[tid]->getDataAsid(); } 354 355#endif 356 357 /** Register accessors. Index refers to the physical register index. */ 358 uint64_t readIntReg(int reg_idx); 359 360 FloatReg readFloatReg(int reg_idx); 361 362 FloatReg readFloatReg(int reg_idx, int width); 363 364 FloatRegBits readFloatRegBits(int reg_idx); 365 366 FloatRegBits readFloatRegBits(int reg_idx, int width); 367 368 void setIntReg(int reg_idx, uint64_t val); 369 370 void setFloatReg(int reg_idx, FloatReg val); 371 372 void setFloatReg(int reg_idx, FloatReg val, int width); 373 374 void setFloatRegBits(int reg_idx, FloatRegBits val); 375 376 void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 377 378 uint64_t readArchIntReg(int reg_idx, unsigned tid); 379 380 float readArchFloatRegSingle(int reg_idx, unsigned tid); 381 382 double readArchFloatRegDouble(int reg_idx, unsigned tid); 383 384 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 385 386 /** Architectural register accessors. Looks up in the commit 387 * rename table to obtain the true physical index of the 388 * architected register first, then accesses that physical 389 * register. 390 */ 391 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 392 393 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 394 395 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 396 397 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 398 399 /** Reads the commit PC of a specific thread. */ 400 uint64_t readPC(unsigned tid); 401 402 /** Sets the commit PC of a specific thread. */ 403 void setPC(Addr new_PC, unsigned tid); 404 405 /** Reads the next PC of a specific thread. */ 406 uint64_t readNextPC(unsigned tid); 407 408 /** Sets the next PC of a specific thread. */ 409 void setNextPC(uint64_t val, unsigned tid); 410 411 /** Reads the next NPC of a specific thread. */ 412 uint64_t readNextNPC(unsigned tid); 413 414 /** Sets the next NPC of a specific thread. */ 415 void setNextNPC(uint64_t val, unsigned tid); 416 417 /** Function to add instruction onto the head of the list of the 418 * instructions. Used when new instructions are fetched. 419 */ 420 ListIt addInst(DynInstPtr &inst); 421 422 /** Function to tell the CPU that an instruction has completed. */ 423 void instDone(unsigned tid); 424 425 /** Add Instructions to the CPU Remove List*/ 426 void addToRemoveList(DynInstPtr &inst); 427 428 /** Remove an instruction from the front end of the list. There's 429 * no restriction on location of the instruction. 430 */ 431 void removeFrontInst(DynInstPtr &inst); 432 433 /** Remove all instructions that are not currently in the ROB. */ 434 void removeInstsNotInROB(unsigned tid); 435 436 /** Remove all instructions younger than the given sequence number. */ 437 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 438 439 /** Removes the instruction pointed to by the iterator. */ 440 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 441 442 /** Cleans up all instructions on the remove list. */ 443 void cleanUpRemovedInsts(); 444 445 /** Debug function to print all instructions on the list. */ 446 void dumpInsts(); 447 448 public: 449 /** List of all the instructions in flight. */ 450 std::list<DynInstPtr> instList; 451 452 /** List of all the instructions that will be removed at the end of this 453 * cycle. 454 */ 455 std::queue<ListIt> removeList; 456 457#ifdef DEBUG 458 /** Debug structure to keep track of the sequence numbers still in 459 * flight. 460 */ 461 std::set<InstSeqNum> snList; 462#endif 463 464 /** Records if instructions need to be removed this cycle due to 465 * being retired or squashed. 466 */ 467 bool removeInstsThisCycle; 468 469 protected: 470 /** The fetch stage. */ 471 typename CPUPolicy::Fetch fetch; 472 473 /** The decode stage. */ 474 typename CPUPolicy::Decode decode; 475 476 /** The dispatch stage. */ 477 typename CPUPolicy::Rename rename; 478 479 /** The issue/execute/writeback stages. */ 480 typename CPUPolicy::IEW iew; 481 482 /** The commit stage. */ 483 typename CPUPolicy::Commit commit; 484 485 /** The register file. */ 486 typename CPUPolicy::RegFile regFile; 487 488 /** The free list. */ 489 typename CPUPolicy::FreeList freeList; 490 491 /** The rename map. */ 492 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 493 494 /** The commit rename map. */ 495 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 496 497 /** The re-order buffer. */ 498 typename CPUPolicy::ROB rob; 499 500 /** Active Threads List */ 501 std::list<unsigned> activeThreads; 502 503 /** Integer Register Scoreboard */ 504 Scoreboard scoreboard; 505 506 public: 507 /** Enum to give each stage a specific index, so when calling 508 * activateStage() or deactivateStage(), they can specify which stage 509 * is being activated/deactivated. 510 */ 511 enum StageIdx { 512 FetchIdx, 513 DecodeIdx, 514 RenameIdx, 515 IEWIdx, 516 CommitIdx, 517 NumStages }; 518 519 /** Typedefs from the Impl to get the structs that each of the 520 * time buffers should use. 521 */ 522 typedef typename CPUPolicy::TimeStruct TimeStruct; 523 524 typedef typename CPUPolicy::FetchStruct FetchStruct; 525 526 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 527 528 typedef typename CPUPolicy::RenameStruct RenameStruct; 529 530 typedef typename CPUPolicy::IEWStruct IEWStruct; 531 532 /** The main time buffer to do backwards communication. */ 533 TimeBuffer<TimeStruct> timeBuffer; 534 535 /** The fetch stage's instruction queue. */ 536 TimeBuffer<FetchStruct> fetchQueue; 537 538 /** The decode stage's instruction queue. */ 539 TimeBuffer<DecodeStruct> decodeQueue; 540 541 /** The rename stage's instruction queue. */ 542 TimeBuffer<RenameStruct> renameQueue; 543 544 /** The IEW stage's instruction queue. */ 545 TimeBuffer<IEWStruct> iewQueue; 546 547 private: 548 /** The activity recorder; used to tell if the CPU has any 549 * activity remaining or if it can go to idle and deschedule 550 * itself. 551 */ 552 ActivityRecorder activityRec; 553 554 public: 555 /** Records that there was time buffer activity this cycle. */ 556 void activityThisCycle() { activityRec.activity(); } 557 558 /** Changes a stage's status to active within the activity recorder. */ 559 void activateStage(const StageIdx idx) 560 { activityRec.activateStage(idx); } 561 562 /** Changes a stage's status to inactive within the activity recorder. */ 563 void deactivateStage(const StageIdx idx) 564 { activityRec.deactivateStage(idx); } 565 566 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 567 void wakeCPU(); 568 569 /** Gets a free thread id. Use if thread ids change across system. */ 570 int getFreeTid(); 571 572 public: 573 /** Returns a pointer to a thread context. */ 574 ThreadContext *tcBase(unsigned tid) 575 { 576 return thread[tid]->getTC(); 577 } 578 579 /** The global sequence number counter. */ 580 InstSeqNum globalSeqNum; 581 582 /** Pointer to the checker, which can dynamically verify 583 * instruction results at run time. This can be set to NULL if it 584 * is not being used. 585 */ 586 Checker<DynInstPtr> *checker; 587 588#if FULL_SYSTEM 589 /** Pointer to the system. */ 590 System *system; 591 592 /** Pointer to physical memory. */ 593 PhysicalMemory *physmem; 594#endif 595 596 /** Pointer to memory. */ 597 MemObject *mem; 598
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572 /** Event to call process() on once draining has completed. */ 573 Event *drainEvent;
| 599 /** Counter of how many stages have completed switching out. */ 600 int switchCount;
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574
| 601
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575 /** Counter of how many stages have completed draining. */ 576 int drainCount; 577
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578 /** Pointers to all of the threads in the CPU. */ 579 std::vector<Thread *> thread; 580 581 /** Pointer to the icache interface. */ 582 MemInterface *icacheInterface; 583 /** Pointer to the dcache interface. */ 584 MemInterface *dcacheInterface; 585 586 /** Whether or not the CPU should defer its registration. */ 587 bool deferRegistration; 588 589 /** Is there a context switch pending? */ 590 bool contextSwitch; 591 592 /** Threads Scheduled to Enter CPU */ 593 std::list<int> cpuWaitList; 594 595 /** The cycle that the CPU was last running, used for statistics. */ 596 Tick lastRunningCycle; 597 598 /** The cycle that the CPU was last activated by a new thread*/ 599 Tick lastActivatedCycle; 600 601 /** Number of Threads CPU can process */ 602 unsigned numThreads; 603 604 /** Mapping for system thread id to cpu id */ 605 std::map<unsigned,unsigned> threadMap; 606 607 /** Available thread ids in the cpu*/ 608 std::vector<unsigned> tids; 609 610 /** Stat for total number of times the CPU is descheduled. */ 611 Stats::Scalar<> timesIdled; 612 /** Stat for total number of cycles the CPU spends descheduled. */ 613 Stats::Scalar<> idleCycles; 614 /** Stat for the number of committed instructions per thread. */ 615 Stats::Vector<> committedInsts; 616 /** Stat for the total number of committed instructions. */ 617 Stats::Scalar<> totalCommittedInsts; 618 /** Stat for the CPI per thread. */ 619 Stats::Formula cpi; 620 /** Stat for the total CPI. */ 621 Stats::Formula totalCpi; 622 /** Stat for the IPC per thread. */ 623 Stats::Formula ipc; 624 /** Stat for the total IPC. */ 625 Stats::Formula totalIpc; 626}; 627 628#endif // __CPU_O3_CPU_HH__
| 602 /** Pointers to all of the threads in the CPU. */ 603 std::vector<Thread *> thread; 604 605 /** Pointer to the icache interface. */ 606 MemInterface *icacheInterface; 607 /** Pointer to the dcache interface. */ 608 MemInterface *dcacheInterface; 609 610 /** Whether or not the CPU should defer its registration. */ 611 bool deferRegistration; 612 613 /** Is there a context switch pending? */ 614 bool contextSwitch; 615 616 /** Threads Scheduled to Enter CPU */ 617 std::list<int> cpuWaitList; 618 619 /** The cycle that the CPU was last running, used for statistics. */ 620 Tick lastRunningCycle; 621 622 /** The cycle that the CPU was last activated by a new thread*/ 623 Tick lastActivatedCycle; 624 625 /** Number of Threads CPU can process */ 626 unsigned numThreads; 627 628 /** Mapping for system thread id to cpu id */ 629 std::map<unsigned,unsigned> threadMap; 630 631 /** Available thread ids in the cpu*/ 632 std::vector<unsigned> tids; 633 634 /** Stat for total number of times the CPU is descheduled. */ 635 Stats::Scalar<> timesIdled; 636 /** Stat for total number of cycles the CPU spends descheduled. */ 637 Stats::Scalar<> idleCycles; 638 /** Stat for the number of committed instructions per thread. */ 639 Stats::Vector<> committedInsts; 640 /** Stat for the total number of committed instructions. */ 641 Stats::Scalar<> totalCommittedInsts; 642 /** Stat for the CPI per thread. */ 643 Stats::Formula cpi; 644 /** Stat for the total CPI. */ 645 Stats::Formula totalCpi; 646 /** Stat for the IPC per thread. */ 647 Stats::Formula ipc; 648 /** Stat for the total IPC. */ 649 Stats::Formula totalIpc; 650}; 651 652#endif // __CPU_O3_CPU_HH__
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