1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/isa_traits.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "cpu/activity.hh"
46#include "cpu/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;
70
71 BaseO3CPU(Params *params);
72
73 void regStats();
74
75 /** Sets this CPU's ID. */
76 void setCpuId(int id) { cpu_id = id; }
77
78 /** Reads this CPU's ID. */
79 int readCpuId() { return cpu_id; }
80
81 protected:
82 int cpu_id;
83};
84
85/**
86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages. The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93 public:
94 typedef TheISA::FloatReg FloatReg;
95 typedef TheISA::FloatRegBits FloatRegBits;
96
97 // Typedefs from the Impl here.
98 typedef typename Impl::CPUPol CPUPolicy;
99 typedef typename Impl::Params Params;
100 typedef typename Impl::DynInstPtr DynInstPtr;
101
102 typedef O3ThreadState<Impl> Thread;
103
104 typedef typename std::list<DynInstPtr>::iterator ListIt;
105
106 friend class O3ThreadContext<Impl>;
107
108 public:
109 enum Status {
110 Running,
111 Idle,
112 Halted,
113 Blocked,
114 SwitchedOut
115 };
116
117 /** Overall CPU status. */
118 Status _status;
119
120 /** Per-thread status in CPU, used for SMT. */
121 Status _threadStatus[Impl::MaxThreads];
122
123 private:
124 class TickEvent : public Event
125 {
126 private:
127 /** Pointer to the CPU. */
128 FullO3CPU<Impl> *cpu;
129
130 public:
131 /** Constructs a tick event. */
132 TickEvent(FullO3CPU<Impl> *c);
133
134 /** Processes a tick event, calling tick() on the CPU. */
135 void process();
136 /** Returns the description of the tick event. */
137 const char *description();
138 };
139
140 /** The tick event used for scheduling CPU ticks. */
141 TickEvent tickEvent;
142
143 /** Schedule tick event, regardless of its current state. */
144 void scheduleTickEvent(int delay)
145 {
146 if (tickEvent.squashed())
147 tickEvent.reschedule(curTick + cycles(delay));
148 else if (!tickEvent.scheduled())
149 tickEvent.schedule(curTick + cycles(delay));
150 }
151
152 /** Unschedule tick event, regardless of its current state. */
153 void unscheduleTickEvent()
154 {
155 if (tickEvent.scheduled())
156 tickEvent.squash();
157 }
158
159 class ActivateThreadEvent : public Event
160 {
161 private:
162 /** Number of Thread to Activate */
163 int tid;
164
165 /** Pointer to the CPU. */
166 FullO3CPU<Impl> *cpu;
167
168 public:
169 /** Constructs the event. */
170 ActivateThreadEvent();
171
172 /** Initialize Event */
173 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
174
175 /** Processes the event, calling activateThread() on the CPU. */
176 void process();
177
178 /** Returns the description of the event. */
179 const char *description();
180 };
181
182 /** Schedule thread to activate , regardless of its current state. */
183 void scheduleActivateThreadEvent(int tid, int delay)
184 {
185 // Schedule thread to activate, regardless of its current state.
186 if (activateThreadEvent[tid].squashed())
187 activateThreadEvent[tid].reschedule(curTick + cycles(delay));
188 else if (!activateThreadEvent[tid].scheduled())
189 activateThreadEvent[tid].schedule(curTick + cycles(delay));
190 }
191
192 /** Unschedule actiavte thread event, regardless of its current state. */
193 void unscheduleActivateThreadEvent(int tid)
194 {
195 if (activateThreadEvent[tid].scheduled())
196 activateThreadEvent[tid].squash();
197 }
198
199 /** The tick event used for scheduling CPU ticks. */
200 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
201
202 public:
203 /** Constructs a CPU with the given parameters. */
204 FullO3CPU(Params *params);
205 /** Destructor. */
206 ~FullO3CPU();
207
208 /** Registers statistics. */
209 void fullCPURegStats();
210
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/isa_traits.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "cpu/activity.hh"
46#include "cpu/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;
70
71 BaseO3CPU(Params *params);
72
73 void regStats();
74
75 /** Sets this CPU's ID. */
76 void setCpuId(int id) { cpu_id = id; }
77
78 /** Reads this CPU's ID. */
79 int readCpuId() { return cpu_id; }
80
81 protected:
82 int cpu_id;
83};
84
85/**
86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages. The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93 public:
94 typedef TheISA::FloatReg FloatReg;
95 typedef TheISA::FloatRegBits FloatRegBits;
96
97 // Typedefs from the Impl here.
98 typedef typename Impl::CPUPol CPUPolicy;
99 typedef typename Impl::Params Params;
100 typedef typename Impl::DynInstPtr DynInstPtr;
101
102 typedef O3ThreadState<Impl> Thread;
103
104 typedef typename std::list<DynInstPtr>::iterator ListIt;
105
106 friend class O3ThreadContext<Impl>;
107
108 public:
109 enum Status {
110 Running,
111 Idle,
112 Halted,
113 Blocked,
114 SwitchedOut
115 };
116
117 /** Overall CPU status. */
118 Status _status;
119
120 /** Per-thread status in CPU, used for SMT. */
121 Status _threadStatus[Impl::MaxThreads];
122
123 private:
124 class TickEvent : public Event
125 {
126 private:
127 /** Pointer to the CPU. */
128 FullO3CPU<Impl> *cpu;
129
130 public:
131 /** Constructs a tick event. */
132 TickEvent(FullO3CPU<Impl> *c);
133
134 /** Processes a tick event, calling tick() on the CPU. */
135 void process();
136 /** Returns the description of the tick event. */
137 const char *description();
138 };
139
140 /** The tick event used for scheduling CPU ticks. */
141 TickEvent tickEvent;
142
143 /** Schedule tick event, regardless of its current state. */
144 void scheduleTickEvent(int delay)
145 {
146 if (tickEvent.squashed())
147 tickEvent.reschedule(curTick + cycles(delay));
148 else if (!tickEvent.scheduled())
149 tickEvent.schedule(curTick + cycles(delay));
150 }
151
152 /** Unschedule tick event, regardless of its current state. */
153 void unscheduleTickEvent()
154 {
155 if (tickEvent.scheduled())
156 tickEvent.squash();
157 }
158
159 class ActivateThreadEvent : public Event
160 {
161 private:
162 /** Number of Thread to Activate */
163 int tid;
164
165 /** Pointer to the CPU. */
166 FullO3CPU<Impl> *cpu;
167
168 public:
169 /** Constructs the event. */
170 ActivateThreadEvent();
171
172 /** Initialize Event */
173 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
174
175 /** Processes the event, calling activateThread() on the CPU. */
176 void process();
177
178 /** Returns the description of the event. */
179 const char *description();
180 };
181
182 /** Schedule thread to activate , regardless of its current state. */
183 void scheduleActivateThreadEvent(int tid, int delay)
184 {
185 // Schedule thread to activate, regardless of its current state.
186 if (activateThreadEvent[tid].squashed())
187 activateThreadEvent[tid].reschedule(curTick + cycles(delay));
188 else if (!activateThreadEvent[tid].scheduled())
189 activateThreadEvent[tid].schedule(curTick + cycles(delay));
190 }
191
192 /** Unschedule actiavte thread event, regardless of its current state. */
193 void unscheduleActivateThreadEvent(int tid)
194 {
195 if (activateThreadEvent[tid].scheduled())
196 activateThreadEvent[tid].squash();
197 }
198
199 /** The tick event used for scheduling CPU ticks. */
200 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
201
202 public:
203 /** Constructs a CPU with the given parameters. */
204 FullO3CPU(Params *params);
205 /** Destructor. */
206 ~FullO3CPU();
207
208 /** Registers statistics. */
209 void fullCPURegStats();
210
|
211 /** Ticks CPU, calling tick() on each stage, and checking the overall
212 * activity to see if the CPU should deschedule itself.
213 */
214 void tick();
215
216 /** Initialize the CPU */
217 void init();
218
219 /** Returns the Number of Active Threads in the CPU */
220 int numActiveThreads()
221 { return activeThreads.size(); }
222
223 /** Add Thread to Active Threads List */
224 void activateThread(unsigned int tid);
225
226 /** Setup CPU to insert a thread's context */
227 void insertThread(unsigned tid);
228
229 /** Remove all of a thread's context from CPU */
230 void removeThread(unsigned tid);
231
232 /** Count the Total Instructions Committed in the CPU. */
233 virtual Counter totalInstructions() const
234 {
235 Counter total(0);
236
237 for (int i=0; i < thread.size(); i++)
238 total += thread[i]->numInst;
239
240 return total;
241 }
242
243 /** Add Thread to Active Threads List. */
244 void activateContext(int tid, int delay);
245
246 /** Remove Thread from Active Threads List */
247 void suspendContext(int tid);
248
249 /** Remove Thread from Active Threads List &&
250 * Remove Thread Context from CPU.
251 */
252 void deallocateContext(int tid);
253
254 /** Remove Thread from Active Threads List &&
255 * Remove Thread Context from CPU.
256 */
257 void haltContext(int tid);
258
259 /** Activate a Thread When CPU Resources are Available. */
260 void activateWhenReady(int tid);
261
262 /** Add or Remove a Thread Context in the CPU. */
263 void doContextSwitch();
264
265 /** Update The Order In Which We Process Threads. */
266 void updateThreadPriority();
267
268 /** Serialize state. */
269 virtual void serialize(std::ostream &os);
270
271 /** Unserialize from a checkpoint. */
272 virtual void unserialize(Checkpoint *cp, const std::string §ion);
273
274 public:
275 /** Executes a syscall on this cycle.
276 * ---------------------------------------
277 * Note: this is a virtual function. CPU-Specific
278 * functionality defined in derived classes
279 */
280 virtual void syscall(int tid) { panic("Unimplemented!"); }
281
282 /** Starts draining the CPU's pipeline of all instructions in
283 * order to stop all memory accesses. */
284 virtual bool drain(Event *drain_event);
285
286 /** Resumes execution after a drain. */
287 virtual void resume();
288
289 /** Signals to this CPU that a stage has completed switching out. */
290 void signalDrained();
291
292 /** Switches out this CPU. */
293 virtual void switchOut();
294
295 /** Takes over from another CPU. */
296 virtual void takeOverFrom(BaseCPU *oldCPU);
297
298 /** Get the current instruction sequence number, and increment it. */
299 InstSeqNum getAndIncrementInstSeq()
300 { return globalSeqNum++; }
301
302#if FULL_SYSTEM
303 /** Check if this address is a valid instruction address. */
304 bool validInstAddr(Addr addr) { return true; }
305
306 /** Check if this address is a valid data address. */
307 bool validDataAddr(Addr addr) { return true; }
308
309 /** Get instruction asid. */
310 int getInstAsid(unsigned tid)
311 { return regFile.miscRegs[tid].getInstAsid(); }
312
313 /** Get data asid. */
314 int getDataAsid(unsigned tid)
315 { return regFile.miscRegs[tid].getDataAsid(); }
316#else
317 /** Get instruction asid. */
318 int getInstAsid(unsigned tid)
319 { return thread[tid]->getInstAsid(); }
320
321 /** Get data asid. */
322 int getDataAsid(unsigned tid)
323 { return thread[tid]->getDataAsid(); }
324
325#endif
326
327 /** Register accessors. Index refers to the physical register index. */
328 uint64_t readIntReg(int reg_idx);
329
330 FloatReg readFloatReg(int reg_idx);
331
332 FloatReg readFloatReg(int reg_idx, int width);
333
334 FloatRegBits readFloatRegBits(int reg_idx);
335
336 FloatRegBits readFloatRegBits(int reg_idx, int width);
337
338 void setIntReg(int reg_idx, uint64_t val);
339
340 void setFloatReg(int reg_idx, FloatReg val);
341
342 void setFloatReg(int reg_idx, FloatReg val, int width);
343
344 void setFloatRegBits(int reg_idx, FloatRegBits val);
345
346 void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
347
348 uint64_t readArchIntReg(int reg_idx, unsigned tid);
349
350 float readArchFloatRegSingle(int reg_idx, unsigned tid);
351
352 double readArchFloatRegDouble(int reg_idx, unsigned tid);
353
354 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
355
356 /** Architectural register accessors. Looks up in the commit
357 * rename table to obtain the true physical index of the
358 * architected register first, then accesses that physical
359 * register.
360 */
361 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
362
363 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
364
365 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
366
367 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
368
369 /** Reads the commit PC of a specific thread. */
370 uint64_t readPC(unsigned tid);
371
372 /** Sets the commit PC of a specific thread. */
373 void setPC(Addr new_PC, unsigned tid);
374
375 /** Reads the next PC of a specific thread. */
376 uint64_t readNextPC(unsigned tid);
377
378 /** Sets the next PC of a specific thread. */
379 void setNextPC(uint64_t val, unsigned tid);
380
381 /** Reads the next NPC of a specific thread. */
382 uint64_t readNextNPC(unsigned tid);
383
384 /** Sets the next NPC of a specific thread. */
385 void setNextNPC(uint64_t val, unsigned tid);
386
387 /** Function to add instruction onto the head of the list of the
388 * instructions. Used when new instructions are fetched.
389 */
390 ListIt addInst(DynInstPtr &inst);
391
392 /** Function to tell the CPU that an instruction has completed. */
393 void instDone(unsigned tid);
394
395 /** Add Instructions to the CPU Remove List*/
396 void addToRemoveList(DynInstPtr &inst);
397
398 /** Remove an instruction from the front end of the list. There's
399 * no restriction on location of the instruction.
400 */
401 void removeFrontInst(DynInstPtr &inst);
402
403 /** Remove all instructions that are not currently in the ROB. */
404 void removeInstsNotInROB(unsigned tid);
405
406 /** Remove all instructions younger than the given sequence number. */
407 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
408
409 /** Removes the instruction pointed to by the iterator. */
410 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
411
412 /** Cleans up all instructions on the remove list. */
413 void cleanUpRemovedInsts();
414
415 /** Debug function to print all instructions on the list. */
416 void dumpInsts();
417
418 public:
419 /** List of all the instructions in flight. */
420 std::list<DynInstPtr> instList;
421
422 /** List of all the instructions that will be removed at the end of this
423 * cycle.
424 */
425 std::queue<ListIt> removeList;
426
427#ifdef DEBUG
428 /** Debug structure to keep track of the sequence numbers still in
429 * flight.
430 */
431 std::set<InstSeqNum> snList;
432#endif
433
434 /** Records if instructions need to be removed this cycle due to
435 * being retired or squashed.
436 */
437 bool removeInstsThisCycle;
438
439 protected:
440 /** The fetch stage. */
441 typename CPUPolicy::Fetch fetch;
442
443 /** The decode stage. */
444 typename CPUPolicy::Decode decode;
445
446 /** The dispatch stage. */
447 typename CPUPolicy::Rename rename;
448
449 /** The issue/execute/writeback stages. */
450 typename CPUPolicy::IEW iew;
451
452 /** The commit stage. */
453 typename CPUPolicy::Commit commit;
454
455 /** The register file. */
456 typename CPUPolicy::RegFile regFile;
457
458 /** The free list. */
459 typename CPUPolicy::FreeList freeList;
460
461 /** The rename map. */
462 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
463
464 /** The commit rename map. */
465 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
466
467 /** The re-order buffer. */
468 typename CPUPolicy::ROB rob;
469
470 /** Active Threads List */
471 std::list<unsigned> activeThreads;
472
473 /** Integer Register Scoreboard */
474 Scoreboard scoreboard;
475
476 public:
477 /** Enum to give each stage a specific index, so when calling
478 * activateStage() or deactivateStage(), they can specify which stage
479 * is being activated/deactivated.
480 */
481 enum StageIdx {
482 FetchIdx,
483 DecodeIdx,
484 RenameIdx,
485 IEWIdx,
486 CommitIdx,
487 NumStages };
488
489 /** Typedefs from the Impl to get the structs that each of the
490 * time buffers should use.
491 */
492 typedef typename CPUPolicy::TimeStruct TimeStruct;
493
494 typedef typename CPUPolicy::FetchStruct FetchStruct;
495
496 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
497
498 typedef typename CPUPolicy::RenameStruct RenameStruct;
499
500 typedef typename CPUPolicy::IEWStruct IEWStruct;
501
502 /** The main time buffer to do backwards communication. */
503 TimeBuffer<TimeStruct> timeBuffer;
504
505 /** The fetch stage's instruction queue. */
506 TimeBuffer<FetchStruct> fetchQueue;
507
508 /** The decode stage's instruction queue. */
509 TimeBuffer<DecodeStruct> decodeQueue;
510
511 /** The rename stage's instruction queue. */
512 TimeBuffer<RenameStruct> renameQueue;
513
514 /** The IEW stage's instruction queue. */
515 TimeBuffer<IEWStruct> iewQueue;
516
517 private:
518 /** The activity recorder; used to tell if the CPU has any
519 * activity remaining or if it can go to idle and deschedule
520 * itself.
521 */
522 ActivityRecorder activityRec;
523
524 public:
525 /** Records that there was time buffer activity this cycle. */
526 void activityThisCycle() { activityRec.activity(); }
527
528 /** Changes a stage's status to active within the activity recorder. */
529 void activateStage(const StageIdx idx)
530 { activityRec.activateStage(idx); }
531
532 /** Changes a stage's status to inactive within the activity recorder. */
533 void deactivateStage(const StageIdx idx)
534 { activityRec.deactivateStage(idx); }
535
536 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
537 void wakeCPU();
538
539 /** Gets a free thread id. Use if thread ids change across system. */
540 int getFreeTid();
541
542 public:
543 /** Returns a pointer to a thread context. */
544 ThreadContext *tcBase(unsigned tid)
545 {
546 return thread[tid]->getTC();
547 }
548
549 /** The global sequence number counter. */
550 InstSeqNum globalSeqNum;
551
552 /** Pointer to the checker, which can dynamically verify
553 * instruction results at run time. This can be set to NULL if it
554 * is not being used.
555 */
556 Checker<DynInstPtr> *checker;
557
558#if FULL_SYSTEM
559 /** Pointer to the system. */
560 System *system;
561
562 /** Pointer to physical memory. */
563 PhysicalMemory *physmem;
564#endif
565
566 /** Pointer to memory. */
567 MemObject *mem;
568
569 /** Event to call process() on once draining has completed. */
570 Event *drainEvent;
571
572 /** Counter of how many stages have completed draining. */
573 int drainCount;
574
575 /** Pointers to all of the threads in the CPU. */
576 std::vector<Thread *> thread;
577
578 /** Pointer to the icache interface. */
579 MemInterface *icacheInterface;
580 /** Pointer to the dcache interface. */
581 MemInterface *dcacheInterface;
582
583 /** Whether or not the CPU should defer its registration. */
584 bool deferRegistration;
585
586 /** Is there a context switch pending? */
587 bool contextSwitch;
588
589 /** Threads Scheduled to Enter CPU */
590 std::list<int> cpuWaitList;
591
592 /** The cycle that the CPU was last running, used for statistics. */
593 Tick lastRunningCycle;
594
595 /** The cycle that the CPU was last activated by a new thread*/
596 Tick lastActivatedCycle;
597
598 /** Number of Threads CPU can process */
599 unsigned numThreads;
600
601 /** Mapping for system thread id to cpu id */
602 std::map<unsigned,unsigned> threadMap;
603
604 /** Available thread ids in the cpu*/
605 std::vector<unsigned> tids;
606
607 /** Stat for total number of times the CPU is descheduled. */
608 Stats::Scalar<> timesIdled;
609 /** Stat for total number of cycles the CPU spends descheduled. */
610 Stats::Scalar<> idleCycles;
611 /** Stat for the number of committed instructions per thread. */
612 Stats::Vector<> committedInsts;
613 /** Stat for the total number of committed instructions. */
614 Stats::Scalar<> totalCommittedInsts;
615 /** Stat for the CPI per thread. */
616 Stats::Formula cpi;
617 /** Stat for the total CPI. */
618 Stats::Formula totalCpi;
619 /** Stat for the IPC per thread. */
620 Stats::Formula ipc;
621 /** Stat for the total IPC. */
622 Stats::Formula totalIpc;
623};
624
625#endif // __CPU_O3_CPU_HH__
| 214 /** Ticks CPU, calling tick() on each stage, and checking the overall
215 * activity to see if the CPU should deschedule itself.
216 */
217 void tick();
218
219 /** Initialize the CPU */
220 void init();
221
222 /** Returns the Number of Active Threads in the CPU */
223 int numActiveThreads()
224 { return activeThreads.size(); }
225
226 /** Add Thread to Active Threads List */
227 void activateThread(unsigned int tid);
228
229 /** Setup CPU to insert a thread's context */
230 void insertThread(unsigned tid);
231
232 /** Remove all of a thread's context from CPU */
233 void removeThread(unsigned tid);
234
235 /** Count the Total Instructions Committed in the CPU. */
236 virtual Counter totalInstructions() const
237 {
238 Counter total(0);
239
240 for (int i=0; i < thread.size(); i++)
241 total += thread[i]->numInst;
242
243 return total;
244 }
245
246 /** Add Thread to Active Threads List. */
247 void activateContext(int tid, int delay);
248
249 /** Remove Thread from Active Threads List */
250 void suspendContext(int tid);
251
252 /** Remove Thread from Active Threads List &&
253 * Remove Thread Context from CPU.
254 */
255 void deallocateContext(int tid);
256
257 /** Remove Thread from Active Threads List &&
258 * Remove Thread Context from CPU.
259 */
260 void haltContext(int tid);
261
262 /** Activate a Thread When CPU Resources are Available. */
263 void activateWhenReady(int tid);
264
265 /** Add or Remove a Thread Context in the CPU. */
266 void doContextSwitch();
267
268 /** Update The Order In Which We Process Threads. */
269 void updateThreadPriority();
270
271 /** Serialize state. */
272 virtual void serialize(std::ostream &os);
273
274 /** Unserialize from a checkpoint. */
275 virtual void unserialize(Checkpoint *cp, const std::string §ion);
276
277 public:
278 /** Executes a syscall on this cycle.
279 * ---------------------------------------
280 * Note: this is a virtual function. CPU-Specific
281 * functionality defined in derived classes
282 */
283 virtual void syscall(int tid) { panic("Unimplemented!"); }
284
285 /** Starts draining the CPU's pipeline of all instructions in
286 * order to stop all memory accesses. */
287 virtual bool drain(Event *drain_event);
288
289 /** Resumes execution after a drain. */
290 virtual void resume();
291
292 /** Signals to this CPU that a stage has completed switching out. */
293 void signalDrained();
294
295 /** Switches out this CPU. */
296 virtual void switchOut();
297
298 /** Takes over from another CPU. */
299 virtual void takeOverFrom(BaseCPU *oldCPU);
300
301 /** Get the current instruction sequence number, and increment it. */
302 InstSeqNum getAndIncrementInstSeq()
303 { return globalSeqNum++; }
304
305#if FULL_SYSTEM
306 /** Check if this address is a valid instruction address. */
307 bool validInstAddr(Addr addr) { return true; }
308
309 /** Check if this address is a valid data address. */
310 bool validDataAddr(Addr addr) { return true; }
311
312 /** Get instruction asid. */
313 int getInstAsid(unsigned tid)
314 { return regFile.miscRegs[tid].getInstAsid(); }
315
316 /** Get data asid. */
317 int getDataAsid(unsigned tid)
318 { return regFile.miscRegs[tid].getDataAsid(); }
319#else
320 /** Get instruction asid. */
321 int getInstAsid(unsigned tid)
322 { return thread[tid]->getInstAsid(); }
323
324 /** Get data asid. */
325 int getDataAsid(unsigned tid)
326 { return thread[tid]->getDataAsid(); }
327
328#endif
329
330 /** Register accessors. Index refers to the physical register index. */
331 uint64_t readIntReg(int reg_idx);
332
333 FloatReg readFloatReg(int reg_idx);
334
335 FloatReg readFloatReg(int reg_idx, int width);
336
337 FloatRegBits readFloatRegBits(int reg_idx);
338
339 FloatRegBits readFloatRegBits(int reg_idx, int width);
340
341 void setIntReg(int reg_idx, uint64_t val);
342
343 void setFloatReg(int reg_idx, FloatReg val);
344
345 void setFloatReg(int reg_idx, FloatReg val, int width);
346
347 void setFloatRegBits(int reg_idx, FloatRegBits val);
348
349 void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
350
351 uint64_t readArchIntReg(int reg_idx, unsigned tid);
352
353 float readArchFloatRegSingle(int reg_idx, unsigned tid);
354
355 double readArchFloatRegDouble(int reg_idx, unsigned tid);
356
357 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
358
359 /** Architectural register accessors. Looks up in the commit
360 * rename table to obtain the true physical index of the
361 * architected register first, then accesses that physical
362 * register.
363 */
364 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
365
366 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
367
368 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
369
370 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
371
372 /** Reads the commit PC of a specific thread. */
373 uint64_t readPC(unsigned tid);
374
375 /** Sets the commit PC of a specific thread. */
376 void setPC(Addr new_PC, unsigned tid);
377
378 /** Reads the next PC of a specific thread. */
379 uint64_t readNextPC(unsigned tid);
380
381 /** Sets the next PC of a specific thread. */
382 void setNextPC(uint64_t val, unsigned tid);
383
384 /** Reads the next NPC of a specific thread. */
385 uint64_t readNextNPC(unsigned tid);
386
387 /** Sets the next NPC of a specific thread. */
388 void setNextNPC(uint64_t val, unsigned tid);
389
390 /** Function to add instruction onto the head of the list of the
391 * instructions. Used when new instructions are fetched.
392 */
393 ListIt addInst(DynInstPtr &inst);
394
395 /** Function to tell the CPU that an instruction has completed. */
396 void instDone(unsigned tid);
397
398 /** Add Instructions to the CPU Remove List*/
399 void addToRemoveList(DynInstPtr &inst);
400
401 /** Remove an instruction from the front end of the list. There's
402 * no restriction on location of the instruction.
403 */
404 void removeFrontInst(DynInstPtr &inst);
405
406 /** Remove all instructions that are not currently in the ROB. */
407 void removeInstsNotInROB(unsigned tid);
408
409 /** Remove all instructions younger than the given sequence number. */
410 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
411
412 /** Removes the instruction pointed to by the iterator. */
413 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
414
415 /** Cleans up all instructions on the remove list. */
416 void cleanUpRemovedInsts();
417
418 /** Debug function to print all instructions on the list. */
419 void dumpInsts();
420
421 public:
422 /** List of all the instructions in flight. */
423 std::list<DynInstPtr> instList;
424
425 /** List of all the instructions that will be removed at the end of this
426 * cycle.
427 */
428 std::queue<ListIt> removeList;
429
430#ifdef DEBUG
431 /** Debug structure to keep track of the sequence numbers still in
432 * flight.
433 */
434 std::set<InstSeqNum> snList;
435#endif
436
437 /** Records if instructions need to be removed this cycle due to
438 * being retired or squashed.
439 */
440 bool removeInstsThisCycle;
441
442 protected:
443 /** The fetch stage. */
444 typename CPUPolicy::Fetch fetch;
445
446 /** The decode stage. */
447 typename CPUPolicy::Decode decode;
448
449 /** The dispatch stage. */
450 typename CPUPolicy::Rename rename;
451
452 /** The issue/execute/writeback stages. */
453 typename CPUPolicy::IEW iew;
454
455 /** The commit stage. */
456 typename CPUPolicy::Commit commit;
457
458 /** The register file. */
459 typename CPUPolicy::RegFile regFile;
460
461 /** The free list. */
462 typename CPUPolicy::FreeList freeList;
463
464 /** The rename map. */
465 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
466
467 /** The commit rename map. */
468 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
469
470 /** The re-order buffer. */
471 typename CPUPolicy::ROB rob;
472
473 /** Active Threads List */
474 std::list<unsigned> activeThreads;
475
476 /** Integer Register Scoreboard */
477 Scoreboard scoreboard;
478
479 public:
480 /** Enum to give each stage a specific index, so when calling
481 * activateStage() or deactivateStage(), they can specify which stage
482 * is being activated/deactivated.
483 */
484 enum StageIdx {
485 FetchIdx,
486 DecodeIdx,
487 RenameIdx,
488 IEWIdx,
489 CommitIdx,
490 NumStages };
491
492 /** Typedefs from the Impl to get the structs that each of the
493 * time buffers should use.
494 */
495 typedef typename CPUPolicy::TimeStruct TimeStruct;
496
497 typedef typename CPUPolicy::FetchStruct FetchStruct;
498
499 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
500
501 typedef typename CPUPolicy::RenameStruct RenameStruct;
502
503 typedef typename CPUPolicy::IEWStruct IEWStruct;
504
505 /** The main time buffer to do backwards communication. */
506 TimeBuffer<TimeStruct> timeBuffer;
507
508 /** The fetch stage's instruction queue. */
509 TimeBuffer<FetchStruct> fetchQueue;
510
511 /** The decode stage's instruction queue. */
512 TimeBuffer<DecodeStruct> decodeQueue;
513
514 /** The rename stage's instruction queue. */
515 TimeBuffer<RenameStruct> renameQueue;
516
517 /** The IEW stage's instruction queue. */
518 TimeBuffer<IEWStruct> iewQueue;
519
520 private:
521 /** The activity recorder; used to tell if the CPU has any
522 * activity remaining or if it can go to idle and deschedule
523 * itself.
524 */
525 ActivityRecorder activityRec;
526
527 public:
528 /** Records that there was time buffer activity this cycle. */
529 void activityThisCycle() { activityRec.activity(); }
530
531 /** Changes a stage's status to active within the activity recorder. */
532 void activateStage(const StageIdx idx)
533 { activityRec.activateStage(idx); }
534
535 /** Changes a stage's status to inactive within the activity recorder. */
536 void deactivateStage(const StageIdx idx)
537 { activityRec.deactivateStage(idx); }
538
539 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
540 void wakeCPU();
541
542 /** Gets a free thread id. Use if thread ids change across system. */
543 int getFreeTid();
544
545 public:
546 /** Returns a pointer to a thread context. */
547 ThreadContext *tcBase(unsigned tid)
548 {
549 return thread[tid]->getTC();
550 }
551
552 /** The global sequence number counter. */
553 InstSeqNum globalSeqNum;
554
555 /** Pointer to the checker, which can dynamically verify
556 * instruction results at run time. This can be set to NULL if it
557 * is not being used.
558 */
559 Checker<DynInstPtr> *checker;
560
561#if FULL_SYSTEM
562 /** Pointer to the system. */
563 System *system;
564
565 /** Pointer to physical memory. */
566 PhysicalMemory *physmem;
567#endif
568
569 /** Pointer to memory. */
570 MemObject *mem;
571
572 /** Event to call process() on once draining has completed. */
573 Event *drainEvent;
574
575 /** Counter of how many stages have completed draining. */
576 int drainCount;
577
578 /** Pointers to all of the threads in the CPU. */
579 std::vector<Thread *> thread;
580
581 /** Pointer to the icache interface. */
582 MemInterface *icacheInterface;
583 /** Pointer to the dcache interface. */
584 MemInterface *dcacheInterface;
585
586 /** Whether or not the CPU should defer its registration. */
587 bool deferRegistration;
588
589 /** Is there a context switch pending? */
590 bool contextSwitch;
591
592 /** Threads Scheduled to Enter CPU */
593 std::list<int> cpuWaitList;
594
595 /** The cycle that the CPU was last running, used for statistics. */
596 Tick lastRunningCycle;
597
598 /** The cycle that the CPU was last activated by a new thread*/
599 Tick lastActivatedCycle;
600
601 /** Number of Threads CPU can process */
602 unsigned numThreads;
603
604 /** Mapping for system thread id to cpu id */
605 std::map<unsigned,unsigned> threadMap;
606
607 /** Available thread ids in the cpu*/
608 std::vector<unsigned> tids;
609
610 /** Stat for total number of times the CPU is descheduled. */
611 Stats::Scalar<> timesIdled;
612 /** Stat for total number of cycles the CPU spends descheduled. */
613 Stats::Scalar<> idleCycles;
614 /** Stat for the number of committed instructions per thread. */
615 Stats::Vector<> committedInsts;
616 /** Stat for the total number of committed instructions. */
617 Stats::Scalar<> totalCommittedInsts;
618 /** Stat for the CPI per thread. */
619 Stats::Formula cpi;
620 /** Stat for the total CPI. */
621 Stats::Formula totalCpi;
622 /** Stat for the IPC per thread. */
623 Stats::Formula ipc;
624 /** Stat for the total IPC. */
625 Stats::Formula totalIpc;
626};
627
628#endif // __CPU_O3_CPU_HH__
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