1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 27 * 28 * Authors: Kevin Lim
|
27 */ 28
| 29 */ 30
|
29#ifndef __CPU_O3_CPU_HH__ 30#define __CPU_O3_CPU_HH__
| 31//Todo: Add in a lot of the functions that are ISA specific. Also define 32//the functions that currently exist within the base cpu class. Define 33//everything for the simobject stuff so it can be serialized and 34//instantiated, add in debugging statements everywhere. Have CPU schedule 35//itself properly. Threads! 36// Avoid running stages and advancing queues if idle/stalled.
|
31
| 37
|
| 38#ifndef __CPU_O3_CPU_FULL_CPU_HH__ 39#define __CPU_O3_CPU_FULL_CPU_HH__ 40
|
32#include <iostream> 33#include <list>
| 41#include <iostream> 42#include <list>
|
34#include <queue> 35#include <set>
| |
36#include <vector> 37 38#include "base/statistics.hh" 39#include "base/timebuf.hh" 40#include "config/full_system.hh"
| 43#include <vector> 44 45#include "base/statistics.hh" 46#include "base/timebuf.hh" 47#include "config/full_system.hh"
|
41#include "cpu/activity.hh"
| |
42#include "cpu/base.hh" 43#include "cpu/cpu_exec_context.hh" 44#include "cpu/o3/comm.hh" 45#include "cpu/o3/cpu_policy.hh"
| 48#include "cpu/base.hh" 49#include "cpu/cpu_exec_context.hh" 50#include "cpu/o3/comm.hh" 51#include "cpu/o3/cpu_policy.hh"
|
46#include "cpu/o3/scoreboard.hh" 47#include "cpu/o3/thread_state.hh"
| |
48#include "sim/process.hh" 49
| 52#include "sim/process.hh" 53
|
50template <class> 51class Checker;
| |
52class ExecContext;
| 54class ExecContext;
|
53class MemInterface;
| 55class FunctionalMemory;
|
54class Process; 55 56class BaseFullCPU : public BaseCPU 57{ 58 //Stuff that's pretty ISA independent will go here. 59 public: 60 typedef BaseCPU::Params Params; 61
| 56class Process; 57 58class BaseFullCPU : public BaseCPU 59{ 60 //Stuff that's pretty ISA independent will go here. 61 public: 62 typedef BaseCPU::Params Params; 63
|
62 BaseFullCPU(Params *params);
| 64#if FULL_SYSTEM 65 BaseFullCPU(Params ¶ms); 66#else 67 BaseFullCPU(Params ¶ms); 68#endif // FULL_SYSTEM
|
63
| 69
|
64 void regStats(); 65
| |
66 protected: 67 int cpu_id; 68}; 69 70template <class Impl> 71class FullO3CPU : public BaseFullCPU 72{ 73 public:
| 70 protected: 71 int cpu_id; 72}; 73 74template <class Impl> 75class FullO3CPU : public BaseFullCPU 76{ 77 public:
|
74 // Typedefs from the Impl here.
| 78 //Put typedefs from the Impl here.
|
75 typedef typename Impl::CPUPol CPUPolicy; 76 typedef typename Impl::Params Params; 77 typedef typename Impl::DynInstPtr DynInstPtr; 78
| 79 typedef typename Impl::CPUPol CPUPolicy; 80 typedef typename Impl::Params Params; 81 typedef typename Impl::DynInstPtr DynInstPtr; 82
|
79 typedef O3ThreadState<Impl> Thread; 80 81 typedef typename std::list<DynInstPtr>::iterator ListIt; 82
| |
83 public: 84 enum Status { 85 Running, 86 Idle, 87 Halted,
| 83 public: 84 enum Status { 85 Running, 86 Idle, 87 Halted,
|
88 Blocked, 89 SwitchedOut
| 88 Blocked // ?
|
90 }; 91
| 89 }; 90
|
92 /** Overall CPU status. */
| |
93 Status _status; 94 95 private: 96 class TickEvent : public Event 97 { 98 private:
| 91 Status _status; 92 93 private: 94 class TickEvent : public Event 95 { 96 private:
|
99 /** Pointer to the CPU. */
| |
100 FullO3CPU<Impl> *cpu; 101 102 public:
| 97 FullO3CPU<Impl> *cpu; 98 99 public:
|
103 /** Constructs a tick event. */
| |
104 TickEvent(FullO3CPU<Impl> *c);
| 100 TickEvent(FullO3CPU<Impl> *c);
|
105 106 /** Processes a tick event, calling tick() on the CPU. */
| |
107 void process();
| 101 void process();
|
108 /** Returns the description of the tick event. */
| |
109 const char *description(); 110 }; 111
| 102 const char *description(); 103 }; 104
|
112 /** The tick event used for scheduling CPU ticks. */
| |
113 TickEvent tickEvent; 114
| 105 TickEvent tickEvent; 106
|
115 /** Schedule tick event, regardless of its current state. */
| 107 /// Schedule tick event, regardless of its current state.
|
116 void scheduleTickEvent(int delay) 117 { 118 if (tickEvent.squashed())
| 108 void scheduleTickEvent(int delay) 109 { 110 if (tickEvent.squashed())
|
119 tickEvent.reschedule(curTick + cycles(delay));
| 111 tickEvent.reschedule(curTick + delay);
|
120 else if (!tickEvent.scheduled())
| 112 else if (!tickEvent.scheduled())
|
121 tickEvent.schedule(curTick + cycles(delay));
| 113 tickEvent.schedule(curTick + delay);
|
122 } 123
| 114 } 115
|
124 /** Unschedule tick event, regardless of its current state. */
| 116 /// Unschedule tick event, regardless of its current state.
|
125 void unscheduleTickEvent() 126 { 127 if (tickEvent.scheduled()) 128 tickEvent.squash(); 129 } 130 131 public:
| 117 void unscheduleTickEvent() 118 { 119 if (tickEvent.scheduled()) 120 tickEvent.squash(); 121 } 122 123 public:
|
132 /** Constructs a CPU with the given parameters. */ 133 FullO3CPU(Params *params); 134 /** Destructor. */
| 124 FullO3CPU(Params ¶ms);
|
135 ~FullO3CPU(); 136
| 125 ~FullO3CPU(); 126
|
137 /** Registers statistics. */
| |
138 void fullCPURegStats(); 139
| 127 void fullCPURegStats(); 128
|
140 /** Ticks CPU, calling tick() on each stage, and checking the overall 141 * activity to see if the CPU should deschedule itself. 142 */
| |
143 void tick(); 144
| 129 void tick(); 130
|
145 /** Initialize the CPU */
| |
146 void init(); 147
| 131 void init(); 132
|
148 /** Setup CPU to insert a thread's context */ 149 void insertThread(unsigned tid);
| 133 void activateContext(int thread_num, int delay); 134 void suspendContext(int thread_num); 135 void deallocateContext(int thread_num); 136 void haltContext(int thread_num);
|
150
| 137
|
151 /** Remove all of a thread's context from CPU */ 152 void removeThread(unsigned tid); 153 154 /** Count the Total Instructions Committed in the CPU. */ 155 virtual Counter totalInstructions() const 156 { 157 Counter total(0); 158 159 for (int i=0; i < thread.size(); i++) 160 total += thread[i]->numInst; 161 162 return total; 163 } 164 165 /** Add Thread to Active Threads List. */ 166 void activateContext(int tid, int delay); 167 168 /** Remove Thread from Active Threads List */ 169 void suspendContext(int tid); 170 171 /** Remove Thread from Active Threads List && 172 * Remove Thread Context from CPU. 173 */ 174 void deallocateContext(int tid); 175 176 /** Remove Thread from Active Threads List && 177 * Remove Thread Context from CPU. 178 */ 179 void haltContext(int tid); 180 181 /** Activate a Thread When CPU Resources are Available. */ 182 void activateWhenReady(int tid); 183 184 /** Add or Remove a Thread Context in the CPU. */ 185 void doContextSwitch(); 186 187 /** Update The Order In Which We Process Threads. */ 188 void updateThreadPriority(); 189 190 /** Executes a syscall on this cycle. 191 * --------------------------------------- 192 * Note: this is a virtual function. CPU-Specific 193 * functionality defined in derived classes 194 */ 195 virtual void syscall(int tid) { panic("Unimplemented!"); } 196 197 /** Check if there are any system calls pending. */ 198 void checkSyscalls(); 199 200 /** Switches out this CPU. 201 */ 202 void switchOut(Sampler *sampler); 203 204 void signalSwitched(); 205 206 /** Takes over from another CPU. 207 */
| 138 void switchOut();
|
208 void takeOverFrom(BaseCPU *oldCPU); 209 210 /** Get the current instruction sequence number, and increment it. */
| 139 void takeOverFrom(BaseCPU *oldCPU); 140 141 /** Get the current instruction sequence number, and increment it. */
|
211 InstSeqNum getAndIncrementInstSeq() 212 { return globalSeqNum++; }
| 142 InstSeqNum getAndIncrementInstSeq();
|
213 214#if FULL_SYSTEM 215 /** Check if this address is a valid instruction address. */ 216 bool validInstAddr(Addr addr) { return true; } 217 218 /** Check if this address is a valid data address. */ 219 bool validDataAddr(Addr addr) { return true; } 220 221 /** Get instruction asid. */
| 143 144#if FULL_SYSTEM 145 /** Check if this address is a valid instruction address. */ 146 bool validInstAddr(Addr addr) { return true; } 147 148 /** Check if this address is a valid data address. */ 149 bool validDataAddr(Addr addr) { return true; } 150 151 /** Get instruction asid. */
|
222 int getInstAsid(unsigned tid) 223 { return regFile.miscRegs[tid].getInstAsid(); }
| 152 int getInstAsid() 153 { return regFile.miscRegs.getInstAsid(); }
|
224 225 /** Get data asid. */
| 154 155 /** Get data asid. */
|
226 int getDataAsid(unsigned tid) 227 { return regFile.miscRegs[tid].getDataAsid(); }
| 156 int getDataAsid() 157 { return regFile.miscRegs.getDataAsid(); }
|
228#else
| 158#else
|
229 /** Check if this address is a valid instruction address. */ 230 bool validInstAddr(Addr addr,unsigned tid) 231 { return thread[tid]->validInstAddr(addr); }
| 159 bool validInstAddr(Addr addr) 160 { return thread[0]->validInstAddr(addr); }
|
232
| 161
|
233 /** Check if this address is a valid data address. */ 234 bool validDataAddr(Addr addr,unsigned tid) 235 { return thread[tid]->validDataAddr(addr); }
| 162 bool validDataAddr(Addr addr) 163 { return thread[0]->validDataAddr(addr); }
|
236
| 164
|
237 /** Get instruction asid. */ 238 int getInstAsid(unsigned tid) 239 { return thread[tid]->asid; }
| 165 int getInstAsid() { return thread[0]->getInstAsid(); } 166 int getDataAsid() { return thread[0]->getDataAsid(); }
|
240
| 167
|
241 /** Get data asid. */ 242 int getDataAsid(unsigned tid) 243 { return thread[tid]->asid; } 244
| |
245#endif 246 247 // 248 // New accessors for new decoder. 249 // 250 uint64_t readIntReg(int reg_idx); 251 252 FloatReg readFloatReg(int reg_idx); 253 254 FloatReg readFloatReg(int reg_idx, int width); 255 256 FloatRegBits readFloatRegBits(int reg_idx); 257 258 FloatRegBits readFloatRegBits(int reg_idx, int width); 259 260 void setIntReg(int reg_idx, uint64_t val); 261 262 void setFloatReg(int reg_idx, FloatReg val, int width); 263 264 void setFloatReg(int reg_idx, FloatReg val, int width); 265 266 void setFloatRegBits(int reg_idx, FloatRegBits val); 267 268 void setFloatRegBits(int reg_idx, FloatRegBits val); 269
| 168#endif 169 170 // 171 // New accessors for new decoder. 172 // 173 uint64_t readIntReg(int reg_idx); 174 175 FloatReg readFloatReg(int reg_idx); 176 177 FloatReg readFloatReg(int reg_idx, int width); 178 179 FloatRegBits readFloatRegBits(int reg_idx); 180 181 FloatRegBits readFloatRegBits(int reg_idx, int width); 182 183 void setIntReg(int reg_idx, uint64_t val); 184 185 void setFloatReg(int reg_idx, FloatReg val, int width); 186 187 void setFloatReg(int reg_idx, FloatReg val, int width); 188 189 void setFloatRegBits(int reg_idx, FloatRegBits val); 190 191 void setFloatRegBits(int reg_idx, FloatRegBits val); 192
|
270 uint64_t readArchIntReg(int reg_idx, unsigned tid);
| 193 uint64_t readPC();
|
271
| 194
|
272 float readArchFloatRegSingle(int reg_idx, unsigned tid);
| 195 void setNextPC(uint64_t val);
|
273
| 196
|
274 double readArchFloatRegDouble(int reg_idx, unsigned tid);
| 197 void setPC(Addr new_PC);
|
275
| 198
|
276 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 277 278 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 279 280 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 281 282 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 283 284 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 285 286 uint64_t readPC(unsigned tid); 287 288 void setPC(Addr new_PC,unsigned tid); 289 290 uint64_t readNextPC(unsigned tid); 291 292 void setNextPC(uint64_t val,unsigned tid); 293
| |
294 /** Function to add instruction onto the head of the list of the 295 * instructions. Used when new instructions are fetched. 296 */
| 199 /** Function to add instruction onto the head of the list of the 200 * instructions. Used when new instructions are fetched. 201 */
|
297 ListIt addInst(DynInstPtr &inst);
| 202 void addInst(DynInstPtr &inst);
|
298 299 /** Function to tell the CPU that an instruction has completed. */
| 203 204 /** Function to tell the CPU that an instruction has completed. */
|
300 void instDone(unsigned tid);
| 205 void instDone();
|
301
| 206
|
302 /** Add Instructions to the CPU Remove List*/ 303 void addToRemoveList(DynInstPtr &inst);
| 207 /** Remove all instructions in back of the given instruction, but leave 208 * that instruction in the list. This is useful in a squash, when there 209 * are instructions in this list that don't exist in structures such as 210 * the ROB. The instruction doesn't have to be the last instruction in 211 * the list, but will be once this function completes. 212 * @todo: Remove only up until that inst? Squashed inst is most likely 213 * valid. 214 */ 215 void removeBackInst(DynInstPtr &inst);
|
304
| 216
|
305 /** Remove an instruction from the front end of the list. There's 306 * no restriction on location of the instruction.
| 217 /** Remove an instruction from the front of the list. It is expected 218 * that there are no instructions in front of it (that is, none are older 219 * than the instruction being removed). Used when retiring instructions. 220 * @todo: Remove the argument to this function, and just have it remove 221 * last instruction once it's verified that commit has the same ordering 222 * as the instruction list.
|
307 */ 308 void removeFrontInst(DynInstPtr &inst); 309 310 /** Remove all instructions that are not currently in the ROB. */
| 223 */ 224 void removeFrontInst(DynInstPtr &inst); 225 226 /** Remove all instructions that are not currently in the ROB. */
|
311 void removeInstsNotInROB(unsigned tid);
| 227 void removeInstsNotInROB();
|
312 313 /** Remove all instructions younger than the given sequence number. */
| 228 229 /** Remove all instructions younger than the given sequence number. */
|
314 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
| 230 void removeInstsUntil(const InstSeqNum &seq_num);
|
315
| 231
|
316 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 317 318 void cleanUpRemovedInsts(); 319
| |
320 /** Remove all instructions from the list. */
| 232 /** Remove all instructions from the list. */
|
321// void removeAllInsts();
| 233 void removeAllInsts();
|
322 323 void dumpInsts(); 324 325 /** Basically a wrapper function so that instructions executed at
| 234 235 void dumpInsts(); 236 237 /** Basically a wrapper function so that instructions executed at
|
326 * commit can tell the instruction queue that they have 327 * completed. Eventually this hack should be removed.
| 238 * commit can tell the instruction queue that they have completed. 239 * Eventually this hack should be removed.
|
328 */
| 240 */
|
329// void wakeDependents(DynInstPtr &inst);
| 241 void wakeDependents(DynInstPtr &inst);
|
330 331 public: 332 /** List of all the instructions in flight. */
| 242 243 public: 244 /** List of all the instructions in flight. */
|
333 std::list<DynInstPtr> instList;
| 245 list instList;
|
334
| 246
|
335 /** List of all the instructions that will be removed at the end of this 336 * cycle. 337 */ 338 std::queue<ListIt> removeList; 339 340#ifdef DEBUG 341 std::set<InstSeqNum> snList; 342#endif 343 344 /** Records if instructions need to be removed this cycle due to 345 * being retired or squashed. 346 */ 347 bool removeInstsThisCycle; 348
| 247 //not sure these should be private.
|
349 protected: 350 /** The fetch stage. */ 351 typename CPUPolicy::Fetch fetch; 352
| 248 protected: 249 /** The fetch stage. */ 250 typename CPUPolicy::Fetch fetch; 251
|
| 252 /** The fetch stage's status. */ 253 typename CPUPolicy::Fetch::Status fetchStatus; 254
|
353 /** The decode stage. */ 354 typename CPUPolicy::Decode decode; 355
| 255 /** The decode stage. */ 256 typename CPUPolicy::Decode decode; 257
|
| 258 /** The decode stage's status. */ 259 typename CPUPolicy::Decode::Status decodeStatus; 260
|
356 /** The dispatch stage. */ 357 typename CPUPolicy::Rename rename; 358
| 261 /** The dispatch stage. */ 262 typename CPUPolicy::Rename rename; 263
|
| 264 /** The dispatch stage's status. */ 265 typename CPUPolicy::Rename::Status renameStatus; 266
|
359 /** The issue/execute/writeback stages. */ 360 typename CPUPolicy::IEW iew; 361
| 267 /** The issue/execute/writeback stages. */ 268 typename CPUPolicy::IEW iew; 269
|
| 270 /** The issue/execute/writeback stage's status. */ 271 typename CPUPolicy::IEW::Status iewStatus; 272
|
362 /** The commit stage. */ 363 typename CPUPolicy::Commit commit; 364
| 273 /** The commit stage. */ 274 typename CPUPolicy::Commit commit; 275
|
| 276 /** The fetch stage's status. */ 277 typename CPUPolicy::Commit::Status commitStatus; 278 279 //Might want to just pass these objects in to the constructors of the 280 //appropriate stage. regFile is in iew, freeList in dispatch, renameMap 281 //in dispatch, and the rob in commit.
|
365 /** The register file. */ 366 typename CPUPolicy::RegFile regFile; 367 368 /** The free list. */ 369 typename CPUPolicy::FreeList freeList; 370 371 /** The rename map. */
| 282 /** The register file. */ 283 typename CPUPolicy::RegFile regFile; 284 285 /** The free list. */ 286 typename CPUPolicy::FreeList freeList; 287 288 /** The rename map. */
|
372 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
| 289 typename CPUPolicy::RenameMap renameMap;
|
373
| 290
|
374 /** The commit rename map. */ 375 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 376
| |
377 /** The re-order buffer. */ 378 typename CPUPolicy::ROB rob; 379
| 291 /** The re-order buffer. */ 292 typename CPUPolicy::ROB rob; 293
|
380 /** Active Threads List */ 381 std::list<unsigned> activeThreads; 382 383 /** Integer Register Scoreboard */ 384 Scoreboard scoreboard; 385
| |
386 public:
| 294 public:
|
387 /** Enum to give each stage a specific index, so when calling 388 * activateStage() or deactivateStage(), they can specify which stage 389 * is being activated/deactivated. 390 */ 391 enum StageIdx { 392 FetchIdx, 393 DecodeIdx, 394 RenameIdx, 395 IEWIdx, 396 CommitIdx, 397 NumStages }; 398
| |
399 /** Typedefs from the Impl to get the structs that each of the 400 * time buffers should use. 401 */ 402 typedef typename CPUPolicy::TimeStruct TimeStruct; 403 404 typedef typename CPUPolicy::FetchStruct FetchStruct; 405 406 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 407 408 typedef typename CPUPolicy::RenameStruct RenameStruct; 409 410 typedef typename CPUPolicy::IEWStruct IEWStruct; 411 412 /** The main time buffer to do backwards communication. */ 413 TimeBuffer<TimeStruct> timeBuffer; 414 415 /** The fetch stage's instruction queue. */ 416 TimeBuffer<FetchStruct> fetchQueue; 417 418 /** The decode stage's instruction queue. */ 419 TimeBuffer<DecodeStruct> decodeQueue; 420 421 /** The rename stage's instruction queue. */ 422 TimeBuffer<RenameStruct> renameQueue; 423 424 /** The IEW stage's instruction queue. */ 425 TimeBuffer<IEWStruct> iewQueue; 426 427 public:
| 295 /** Typedefs from the Impl to get the structs that each of the 296 * time buffers should use. 297 */ 298 typedef typename CPUPolicy::TimeStruct TimeStruct; 299 300 typedef typename CPUPolicy::FetchStruct FetchStruct; 301 302 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 303 304 typedef typename CPUPolicy::RenameStruct RenameStruct; 305 306 typedef typename CPUPolicy::IEWStruct IEWStruct; 307 308 /** The main time buffer to do backwards communication. */ 309 TimeBuffer<TimeStruct> timeBuffer; 310 311 /** The fetch stage's instruction queue. */ 312 TimeBuffer<FetchStruct> fetchQueue; 313 314 /** The decode stage's instruction queue. */ 315 TimeBuffer<DecodeStruct> decodeQueue; 316 317 /** The rename stage's instruction queue. */ 318 TimeBuffer<RenameStruct> renameQueue; 319 320 /** The IEW stage's instruction queue. */ 321 TimeBuffer<IEWStruct> iewQueue; 322 323 public:
|
428 ActivityRecorder activityRec;
| 324 /** The temporary exec context to support older accessors. */ 325 CPUExecContext *cpuXC;
|
429
| 326
|
430 void activityThisCycle() { activityRec.activity(); } 431 432 void activateStage(const StageIdx idx) 433 { activityRec.activateStage(idx); } 434 435 void deactivateStage(const StageIdx idx) 436 { activityRec.deactivateStage(idx); } 437 438 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 439 void wakeCPU(); 440 441 /** Gets a free thread id. Use if thread ids change across system. */ 442 int getFreeTid(); 443 444 public:
| |
445 /** Temporary function to get pointer to exec context. */
| 327 /** Temporary function to get pointer to exec context. */
|
446 ExecContext *xcBase(unsigned tid)
| 328 ExecContext *xcBase()
|
447 {
| 329 {
|
448 return thread[tid]->getXCProxy();
| 330 return thread[0]->getProxy();
|
449 } 450
| 331 } 332
|
451 /** The global sequence number counter. */
| 333 CPUExecContext *cpuXCBase() 334 { 335 return thread[0]; 336 } 337
|
452 InstSeqNum globalSeqNum; 453
| 338 InstSeqNum globalSeqNum; 339
|
454 Checker<DynInstPtr> *checker; 455
| |
456#if FULL_SYSTEM
| 340#if FULL_SYSTEM
|
457 /** Pointer to the system. */
| |
458 System *system; 459
| 341 System *system; 342
|
460 /** Pointer to the memory controller. */
| |
461 MemoryController *memCtrl;
| 343 MemoryController *memCtrl;
|
462 /** Pointer to physical memory. */
| |
463 PhysicalMemory *physmem;
| 344 PhysicalMemory *physmem;
|
464#endif
| |
465
| 345
|
466 /** Pointer to memory. */ 467 FunctionalMemory *mem;
| 346 AlphaITB *itb; 347 AlphaDTB *dtb;
|
468
| 348
|
469 Sampler *sampler; 470 471 int switchCount; 472 473 // List of all ExecContexts. 474 std::vector<Thread *> thread; 475 476#if 0 477 /** Page table pointer. */ 478 PageTable *pTable;
| 349// SWContext *swCtx;
|
479#endif
| 350#endif
|
| 351 std::vector<CPUExecContext *> thread;
|
480
| 352
|
481 /** Pointer to the icache interface. */
| 353 FunctionalMemory *mem; 354
|
482 MemInterface *icacheInterface;
| 355 MemInterface *icacheInterface;
|
483 /** Pointer to the dcache interface. */
| |
484 MemInterface *dcacheInterface; 485
| 356 MemInterface *dcacheInterface; 357
|
486 /** Whether or not the CPU should defer its registration. */
| |
487 bool deferRegistration; 488
| 358 bool deferRegistration; 359
|
489 /** Is there a context switch pending? */ 490 bool contextSwitch;
| 360 Counter numInsts;
|
491
| 361
|
492 /** Threads Scheduled to Enter CPU */ 493 std::list<int> cpuWaitList; 494 495 /** The cycle that the CPU was last running, used for statistics. */ 496 Tick lastRunningCycle; 497 498 /** Number of Threads CPU can process */ 499 unsigned numThreads; 500 501 /** Mapping for system thread id to cpu id */ 502 std::map<unsigned,unsigned> threadMap; 503 504 /** Available thread ids in the cpu*/ 505 std::vector<unsigned> tids; 506 507 /** Stat for total number of times the CPU is descheduled. */ 508 Stats::Scalar<> timesIdled; 509 /** Stat for total number of cycles the CPU spends descheduled. */ 510 Stats::Scalar<> idleCycles; 511 /** Stat for the number of committed instructions per thread. */ 512 Stats::Vector<> committedInsts; 513 /** Stat for the total number of committed instructions. */ 514 Stats::Scalar<> totalCommittedInsts; 515 /** Stat for the CPI per thread. */ 516 Stats::Formula cpi; 517 /** Stat for the total CPI. */ 518 Stats::Formula totalCpi; 519 /** Stat for the IPC per thread. */ 520 Stats::Formula ipc; 521 /** Stat for the total IPC. */ 522 Stats::Formula totalIpc;
| 362 Counter funcExeInst;
|
523}; 524
| 363}; 364
|
525#endif // __CPU_O3_CPU_HH__
| 365#endif
|
| |