1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/generic/types.hh"
57#include "arch/types.hh"
58#include "base/statistics.hh"
59#include "config/the_isa.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"
65#include "cpu/base.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/timebuf.hh"
68//#include "cpu/o3/thread_context.hh"
69#include "params/DerivO3CPU.hh"
70#include "sim/process.hh"
71
72template <class>
73class Checker;
74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 using VecElem = TheISA::VecElem;
107 using VecRegContainer = TheISA::VecRegContainer;
108
109 using VecPredRegContainer = TheISA::VecPredRegContainer;
110
111 typedef O3ThreadState<Impl> ImplState;
112 typedef O3ThreadState<Impl> Thread;
113
114 typedef typename std::list<DynInstPtr>::iterator ListIt;
115
116 friend class O3ThreadContext<Impl>;
117
118 public:
119 enum Status {
120 Running,
121 Idle,
122 Halted,
123 Blocked,
124 SwitchedOut
125 };
126
127 BaseTLB *itb;
128 BaseTLB *dtb;
129 using LSQRequest = typename LSQ<Impl>::LSQRequest;
130
131 /** Overall CPU status. */
132 Status _status;
133
134 private:
135
136 /** The tick event used for scheduling CPU ticks. */
137 EventFunctionWrapper tickEvent;
138
139 /** The exit event used for terminating all ready-to-exit threads */
140 EventFunctionWrapper threadExitEvent;
141
142 /** Schedule tick event, regardless of its current state. */
143 void scheduleTickEvent(Cycles delay)
144 {
145 if (tickEvent.squashed())
146 reschedule(tickEvent, clockEdge(delay));
147 else if (!tickEvent.scheduled())
148 schedule(tickEvent, clockEdge(delay));
149 }
150
151 /** Unschedule tick event, regardless of its current state. */
152 void unscheduleTickEvent()
153 {
154 if (tickEvent.scheduled())
155 tickEvent.squash();
156 }
157
158 /**
159 * Check if the pipeline has drained and signal drain done.
160 *
161 * This method checks if a drain has been requested and if the CPU
162 * has drained successfully (i.e., there are no instructions in
163 * the pipeline). If the CPU has drained, it deschedules the tick
164 * event and signals the drain manager.
165 *
166 * @return False if a drain hasn't been requested or the CPU
167 * hasn't drained, true otherwise.
168 */
169 bool tryDrain();
170
171 /**
172 * Perform sanity checks after a drain.
173 *
174 * This method is called from drain() when it has determined that
175 * the CPU is fully drained when gem5 is compiled with the NDEBUG
176 * macro undefined. The intention of this method is to do more
177 * extensive tests than the isDrained() method to weed out any
178 * draining bugs.
179 */
180 void drainSanityCheck() const;
181
182 /** Check if a system is in a drained state. */
183 bool isCpuDrained() const;
184
185 public:
186 /** Constructs a CPU with the given parameters. */
187 FullO3CPU(DerivO3CPUParams *params);
188 /** Destructor. */
189 ~FullO3CPU();
190
191 /** Registers statistics. */
192 void regStats() override;
193
194 ProbePointArg<PacketPtr> *ppInstAccessComplete;
195 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
196
197 /** Register probe points. */
198 void regProbePoints() override;
199
200 void demapPage(Addr vaddr, uint64_t asn)
201 {
202 this->itb->demapPage(vaddr, asn);
203 this->dtb->demapPage(vaddr, asn);
204 }
205
206 void demapInstPage(Addr vaddr, uint64_t asn)
207 {
208 this->itb->demapPage(vaddr, asn);
209 }
210
211 void demapDataPage(Addr vaddr, uint64_t asn)
212 {
213 this->dtb->demapPage(vaddr, asn);
214 }
215
216 /** Ticks CPU, calling tick() on each stage, and checking the overall
217 * activity to see if the CPU should deschedule itself.
218 */
219 void tick();
220
221 /** Initialize the CPU */
222 void init() override;
223
224 void startup() override;
225
226 /** Returns the Number of Active Threads in the CPU */
227 int numActiveThreads()
228 { return activeThreads.size(); }
229
230 /** Add Thread to Active Threads List */
231 void activateThread(ThreadID tid);
232
233 /** Remove Thread from Active Threads List */
234 void deactivateThread(ThreadID tid);
235
236 /** Setup CPU to insert a thread's context */
237 void insertThread(ThreadID tid);
238
239 /** Remove all of a thread's context from CPU */
240 void removeThread(ThreadID tid);
241
242 /** Count the Total Instructions Committed in the CPU. */
243 Counter totalInsts() const override;
244
245 /** Count the Total Ops (including micro ops) committed in the CPU. */
246 Counter totalOps() const override;
247
248 /** Add Thread to Active Threads List. */
249 void activateContext(ThreadID tid) override;
250
251 /** Remove Thread from Active Threads List */
252 void suspendContext(ThreadID tid) override;
253
254 /** Remove Thread from Active Threads List &&
255 * Remove Thread Context from CPU.
256 */
257 void haltContext(ThreadID tid) override;
258
259 /** Update The Order In Which We Process Threads. */
260 void updateThreadPriority();
261
262 /** Is the CPU draining? */
263 bool isDraining() const { return drainState() == DrainState::Draining; }
264
265 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
266 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
267
268 /** Insert tid to the list of threads trying to exit */
269 void addThreadToExitingList(ThreadID tid);
270
271 /** Is the thread trying to exit? */
272 bool isThreadExiting(ThreadID tid) const;
273
274 /**
275 * If a thread is trying to exit and its corresponding trap event
276 * has been completed, schedule an event to terminate the thread.
277 */
278 void scheduleThreadExitEvent(ThreadID tid);
279
280 /** Terminate all threads that are ready to exit */
281 void exitThreads();
282
283 public:
284 /** Executes a syscall.
285 * @todo: Determine if this needs to be virtual.
286 */
287 void syscall(int64_t callnum, ThreadID tid, Fault *fault);
288
289 /** Starts draining the CPU's pipeline of all instructions in
290 * order to stop all memory accesses. */
291 DrainState drain() override;
292
293 /** Resumes execution after a drain. */
294 void drainResume() override;
295
296 /**
297 * Commit has reached a safe point to drain a thread.
298 *
299 * Commit calls this method to inform the pipeline that it has
300 * reached a point where it is not executed microcode and is about
301 * to squash uncommitted instructions to fully drain the pipeline.
302 */
303 void commitDrained(ThreadID tid);
304
305 /** Switches out this CPU. */
306 void switchOut() override;
307
308 /** Takes over from another CPU. */
309 void takeOverFrom(BaseCPU *oldCPU) override;
310
311 void verifyMemoryMode() const override;
312
313 /** Get the current instruction sequence number, and increment it. */
314 InstSeqNum getAndIncrementInstSeq()
315 { return globalSeqNum++; }
316
317 /** Traps to handle given fault. */
318 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
319
320 /** Check if a change in renaming is needed for vector registers.
321 * The vecMode variable is updated and propagated to rename maps.
322 *
323 * @param tid ThreadID
324 * @param freelist list of free registers
325 */
326 void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
327
328 /** Returns the Fault for any valid interrupt. */
329 Fault getInterrupts();
330
331 /** Processes any an interrupt fault. */
332 void processInterrupts(const Fault &interrupt);
333
334 /** Halts the CPU. */
335 void halt() { panic("Halt not implemented!\n"); }
336
337 /** Register accessors. Index refers to the physical register index. */
338
339 /** Reads a miscellaneous register. */
340 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
341
342 /** Reads a misc. register, including any side effects the read
343 * might have as defined by the architecture.
344 */
345 RegVal readMiscReg(int misc_reg, ThreadID tid);
346
347 /** Sets a miscellaneous register. */
348 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
349
350 /** Sets a misc. register, including any side effects the write
351 * might have as defined by the architecture.
352 */
353 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
354
355 RegVal readIntReg(PhysRegIdPtr phys_reg);
356
357 RegVal readFloatReg(PhysRegIdPtr phys_reg);
358
359 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
360
361 /**
362 * Read physical vector register for modification.
363 */
364 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
365
366 /** Returns current vector renaming mode */
367 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
368
369 /** Sets the current vector renaming mode */
370 void vecRenameMode(Enums::VecRegRenameMode vec_mode)
371 { vecMode = vec_mode; }
372
373 /**
374 * Read physical vector register lane
375 */
376 template<typename VecElem, int LaneIdx>
377 VecLaneT<VecElem, true>
378 readVecLane(PhysRegIdPtr phys_reg) const
379 {
380 vecRegfileReads++;
381 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
382 }
383
384 /**
385 * Read physical vector register lane
386 */
387 template<typename VecElem>
388 VecLaneT<VecElem, true>
389 readVecLane(PhysRegIdPtr phys_reg) const
390 {
391 vecRegfileReads++;
392 return regFile.readVecLane<VecElem>(phys_reg);
393 }
394
395 /** Write a lane of the destination vector register. */
396 template<typename LD>
397 void
398 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
399 {
400 vecRegfileWrites++;
401 return regFile.setVecLane(phys_reg, val);
402 }
403
404 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
405
406 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
407
408 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
409
410 RegVal readCCReg(PhysRegIdPtr phys_reg);
411
412 void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
413
414 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
415
416 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
417
418 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
419
420 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
421
422 void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
423
424 RegVal readArchIntReg(int reg_idx, ThreadID tid);
425
426 RegVal readArchFloatReg(int reg_idx, ThreadID tid);
427
428 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
429 /** Read architectural vector register for modification. */
430 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
431
432 /** Read architectural vector register lane. */
433 template<typename VecElem>
434 VecLaneT<VecElem, true>
435 readArchVecLane(int reg_idx, int lId, ThreadID tid) const
436 {
437 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
438 RegId(VecRegClass, reg_idx));
439 return readVecLane<VecElem>(phys_reg);
440 }
441
442
443 /** Write a lane of the destination vector register. */
444 template<typename LD>
445 void
446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
447 {
448 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
449 RegId(VecRegClass, reg_idx));
450 setVecLane(phys_reg, val);
451 }
452
453 const VecElem& readArchVecElem(const RegIndex& reg_idx,
454 const ElemIndex& ldx, ThreadID tid) const;
455
456 const VecPredRegContainer& readArchVecPredReg(int reg_idx,
457 ThreadID tid) const;
458
459 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
460
461 RegVal readArchCCReg(int reg_idx, ThreadID tid);
462
463 /** Architectural register accessors. Looks up in the commit
464 * rename table to obtain the true physical index of the
465 * architected register first, then accesses that physical
466 * register.
467 */
468 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
469
470 void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
471
472 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
473 ThreadID tid);
474
475 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
476
477 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
478 const VecElem& val, ThreadID tid);
479
480 void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
481
482 /** Sets the commit PC state of a specific thread. */
483 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
484
485 /** Reads the commit PC state of a specific thread. */
486 TheISA::PCState pcState(ThreadID tid);
487
488 /** Reads the commit PC of a specific thread. */
489 Addr instAddr(ThreadID tid);
490
491 /** Reads the commit micro PC of a specific thread. */
492 MicroPC microPC(ThreadID tid);
493
494 /** Reads the next PC of a specific thread. */
495 Addr nextInstAddr(ThreadID tid);
496
497 /** Initiates a squash of all in-flight instructions for a given
498 * thread. The source of the squash is an external update of
499 * state through the TC.
500 */
501 void squashFromTC(ThreadID tid);
502
503 /** Function to add instruction onto the head of the list of the
504 * instructions. Used when new instructions are fetched.
505 */
506 ListIt addInst(const DynInstPtr &inst);
507
508 /** Function to tell the CPU that an instruction has completed. */
509 void instDone(ThreadID tid, const DynInstPtr &inst);
510
511 /** Remove an instruction from the front end of the list. There's
512 * no restriction on location of the instruction.
513 */
514 void removeFrontInst(const DynInstPtr &inst);
515
516 /** Remove all instructions that are not currently in the ROB.
517 * There's also an option to not squash delay slot instructions.*/
518 void removeInstsNotInROB(ThreadID tid);
519
520 /** Remove all instructions younger than the given sequence number. */
521 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
522
523 /** Removes the instruction pointed to by the iterator. */
524 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
525
526 /** Cleans up all instructions on the remove list. */
527 void cleanUpRemovedInsts();
528
529 /** Debug function to print all instructions on the list. */
530 void dumpInsts();
531
532 public:
533#ifndef NDEBUG
534 /** Count of total number of dynamic instructions in flight. */
535 int instcount;
536#endif
537
538 /** List of all the instructions in flight. */
539 std::list<DynInstPtr> instList;
540
541 /** List of all the instructions that will be removed at the end of this
542 * cycle.
543 */
544 std::queue<ListIt> removeList;
545
546#ifdef DEBUG
547 /** Debug structure to keep track of the sequence numbers still in
548 * flight.
549 */
550 std::set<InstSeqNum> snList;
551#endif
552
553 /** Records if instructions need to be removed this cycle due to
554 * being retired or squashed.
555 */
556 bool removeInstsThisCycle;
557
558 protected:
559 /** The fetch stage. */
560 typename CPUPolicy::Fetch fetch;
561
562 /** The decode stage. */
563 typename CPUPolicy::Decode decode;
564
565 /** The dispatch stage. */
566 typename CPUPolicy::Rename rename;
567
568 /** The issue/execute/writeback stages. */
569 typename CPUPolicy::IEW iew;
570
571 /** The commit stage. */
572 typename CPUPolicy::Commit commit;
573
574 /** The rename mode of the vector registers */
575 Enums::VecRegRenameMode vecMode;
576
577 /** The register file. */
578 PhysRegFile regFile;
579
580 /** The free list. */
581 typename CPUPolicy::FreeList freeList;
582
583 /** The rename map. */
584 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
585
586 /** The commit rename map. */
587 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
588
589 /** The re-order buffer. */
590 typename CPUPolicy::ROB rob;
591
592 /** Active Threads List */
593 std::list<ThreadID> activeThreads;
594
595 /**
596 * This is a list of threads that are trying to exit. Each thread id
597 * is mapped to a boolean value denoting whether the thread is ready
598 * to exit.
599 */
600 std::unordered_map<ThreadID, bool> exitingThreads;
601
602 /** Integer Register Scoreboard */
603 Scoreboard scoreboard;
604
605 std::vector<TheISA::ISA *> isa;
606
607 public:
608 /** Enum to give each stage a specific index, so when calling
609 * activateStage() or deactivateStage(), they can specify which stage
610 * is being activated/deactivated.
611 */
612 enum StageIdx {
613 FetchIdx,
614 DecodeIdx,
615 RenameIdx,
616 IEWIdx,
617 CommitIdx,
618 NumStages };
619
620 /** Typedefs from the Impl to get the structs that each of the
621 * time buffers should use.
622 */
623 typedef typename CPUPolicy::TimeStruct TimeStruct;
624
625 typedef typename CPUPolicy::FetchStruct FetchStruct;
626
627 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
628
629 typedef typename CPUPolicy::RenameStruct RenameStruct;
630
631 typedef typename CPUPolicy::IEWStruct IEWStruct;
632
633 /** The main time buffer to do backwards communication. */
634 TimeBuffer<TimeStruct> timeBuffer;
635
636 /** The fetch stage's instruction queue. */
637 TimeBuffer<FetchStruct> fetchQueue;
638
639 /** The decode stage's instruction queue. */
640 TimeBuffer<DecodeStruct> decodeQueue;
641
642 /** The rename stage's instruction queue. */
643 TimeBuffer<RenameStruct> renameQueue;
644
645 /** The IEW stage's instruction queue. */
646 TimeBuffer<IEWStruct> iewQueue;
647
648 private:
649 /** The activity recorder; used to tell if the CPU has any
650 * activity remaining or if it can go to idle and deschedule
651 * itself.
652 */
653 ActivityRecorder activityRec;
654
655 public:
656 /** Records that there was time buffer activity this cycle. */
657 void activityThisCycle() { activityRec.activity(); }
658
659 /** Changes a stage's status to active within the activity recorder. */
660 void activateStage(const StageIdx idx)
661 { activityRec.activateStage(idx); }
662
663 /** Changes a stage's status to inactive within the activity recorder. */
664 void deactivateStage(const StageIdx idx)
665 { activityRec.deactivateStage(idx); }
666
667 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
668 void wakeCPU();
669
670 virtual void wakeup(ThreadID tid) override;
671
672 /** Gets a free thread id. Use if thread ids change across system. */
673 ThreadID getFreeTid();
674
675 public:
676 /** Returns a pointer to a thread context. */
677 ThreadContext *
678 tcBase(ThreadID tid)
679 {
680 return thread[tid]->getTC();
681 }
682
683 /** The global sequence number counter. */
684 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
685
686 /** Pointer to the checker, which can dynamically verify
687 * instruction results at run time. This can be set to NULL if it
688 * is not being used.
689 */
690 Checker<Impl> *checker;
691
692 /** Pointer to the system. */
693 System *system;
694
695 /** Pointers to all of the threads in the CPU. */
696 std::vector<Thread *> thread;
697
698 /** Threads Scheduled to Enter CPU */
699 std::list<int> cpuWaitList;
700
701 /** The cycle that the CPU was last running, used for statistics. */
702 Cycles lastRunningCycle;
703
704 /** The cycle that the CPU was last activated by a new thread*/
705 Tick lastActivatedCycle;
706
707 /** Mapping for system thread id to cpu id */
708 std::map<ThreadID, unsigned> threadMap;
709
710 /** Available thread ids in the cpu*/
711 std::vector<ThreadID> tids;
712
713 /** CPU pushRequest function, forwards request to LSQ. */
714 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
715 unsigned int size, Addr addr, Request::Flags flags,
| 1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/generic/types.hh"
57#include "arch/types.hh"
58#include "base/statistics.hh"
59#include "config/the_isa.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"
65#include "cpu/base.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/timebuf.hh"
68//#include "cpu/o3/thread_context.hh"
69#include "params/DerivO3CPU.hh"
70#include "sim/process.hh"
71
72template <class>
73class Checker;
74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 using VecElem = TheISA::VecElem;
107 using VecRegContainer = TheISA::VecRegContainer;
108
109 using VecPredRegContainer = TheISA::VecPredRegContainer;
110
111 typedef O3ThreadState<Impl> ImplState;
112 typedef O3ThreadState<Impl> Thread;
113
114 typedef typename std::list<DynInstPtr>::iterator ListIt;
115
116 friend class O3ThreadContext<Impl>;
117
118 public:
119 enum Status {
120 Running,
121 Idle,
122 Halted,
123 Blocked,
124 SwitchedOut
125 };
126
127 BaseTLB *itb;
128 BaseTLB *dtb;
129 using LSQRequest = typename LSQ<Impl>::LSQRequest;
130
131 /** Overall CPU status. */
132 Status _status;
133
134 private:
135
136 /** The tick event used for scheduling CPU ticks. */
137 EventFunctionWrapper tickEvent;
138
139 /** The exit event used for terminating all ready-to-exit threads */
140 EventFunctionWrapper threadExitEvent;
141
142 /** Schedule tick event, regardless of its current state. */
143 void scheduleTickEvent(Cycles delay)
144 {
145 if (tickEvent.squashed())
146 reschedule(tickEvent, clockEdge(delay));
147 else if (!tickEvent.scheduled())
148 schedule(tickEvent, clockEdge(delay));
149 }
150
151 /** Unschedule tick event, regardless of its current state. */
152 void unscheduleTickEvent()
153 {
154 if (tickEvent.scheduled())
155 tickEvent.squash();
156 }
157
158 /**
159 * Check if the pipeline has drained and signal drain done.
160 *
161 * This method checks if a drain has been requested and if the CPU
162 * has drained successfully (i.e., there are no instructions in
163 * the pipeline). If the CPU has drained, it deschedules the tick
164 * event and signals the drain manager.
165 *
166 * @return False if a drain hasn't been requested or the CPU
167 * hasn't drained, true otherwise.
168 */
169 bool tryDrain();
170
171 /**
172 * Perform sanity checks after a drain.
173 *
174 * This method is called from drain() when it has determined that
175 * the CPU is fully drained when gem5 is compiled with the NDEBUG
176 * macro undefined. The intention of this method is to do more
177 * extensive tests than the isDrained() method to weed out any
178 * draining bugs.
179 */
180 void drainSanityCheck() const;
181
182 /** Check if a system is in a drained state. */
183 bool isCpuDrained() const;
184
185 public:
186 /** Constructs a CPU with the given parameters. */
187 FullO3CPU(DerivO3CPUParams *params);
188 /** Destructor. */
189 ~FullO3CPU();
190
191 /** Registers statistics. */
192 void regStats() override;
193
194 ProbePointArg<PacketPtr> *ppInstAccessComplete;
195 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
196
197 /** Register probe points. */
198 void regProbePoints() override;
199
200 void demapPage(Addr vaddr, uint64_t asn)
201 {
202 this->itb->demapPage(vaddr, asn);
203 this->dtb->demapPage(vaddr, asn);
204 }
205
206 void demapInstPage(Addr vaddr, uint64_t asn)
207 {
208 this->itb->demapPage(vaddr, asn);
209 }
210
211 void demapDataPage(Addr vaddr, uint64_t asn)
212 {
213 this->dtb->demapPage(vaddr, asn);
214 }
215
216 /** Ticks CPU, calling tick() on each stage, and checking the overall
217 * activity to see if the CPU should deschedule itself.
218 */
219 void tick();
220
221 /** Initialize the CPU */
222 void init() override;
223
224 void startup() override;
225
226 /** Returns the Number of Active Threads in the CPU */
227 int numActiveThreads()
228 { return activeThreads.size(); }
229
230 /** Add Thread to Active Threads List */
231 void activateThread(ThreadID tid);
232
233 /** Remove Thread from Active Threads List */
234 void deactivateThread(ThreadID tid);
235
236 /** Setup CPU to insert a thread's context */
237 void insertThread(ThreadID tid);
238
239 /** Remove all of a thread's context from CPU */
240 void removeThread(ThreadID tid);
241
242 /** Count the Total Instructions Committed in the CPU. */
243 Counter totalInsts() const override;
244
245 /** Count the Total Ops (including micro ops) committed in the CPU. */
246 Counter totalOps() const override;
247
248 /** Add Thread to Active Threads List. */
249 void activateContext(ThreadID tid) override;
250
251 /** Remove Thread from Active Threads List */
252 void suspendContext(ThreadID tid) override;
253
254 /** Remove Thread from Active Threads List &&
255 * Remove Thread Context from CPU.
256 */
257 void haltContext(ThreadID tid) override;
258
259 /** Update The Order In Which We Process Threads. */
260 void updateThreadPriority();
261
262 /** Is the CPU draining? */
263 bool isDraining() const { return drainState() == DrainState::Draining; }
264
265 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
266 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
267
268 /** Insert tid to the list of threads trying to exit */
269 void addThreadToExitingList(ThreadID tid);
270
271 /** Is the thread trying to exit? */
272 bool isThreadExiting(ThreadID tid) const;
273
274 /**
275 * If a thread is trying to exit and its corresponding trap event
276 * has been completed, schedule an event to terminate the thread.
277 */
278 void scheduleThreadExitEvent(ThreadID tid);
279
280 /** Terminate all threads that are ready to exit */
281 void exitThreads();
282
283 public:
284 /** Executes a syscall.
285 * @todo: Determine if this needs to be virtual.
286 */
287 void syscall(int64_t callnum, ThreadID tid, Fault *fault);
288
289 /** Starts draining the CPU's pipeline of all instructions in
290 * order to stop all memory accesses. */
291 DrainState drain() override;
292
293 /** Resumes execution after a drain. */
294 void drainResume() override;
295
296 /**
297 * Commit has reached a safe point to drain a thread.
298 *
299 * Commit calls this method to inform the pipeline that it has
300 * reached a point where it is not executed microcode and is about
301 * to squash uncommitted instructions to fully drain the pipeline.
302 */
303 void commitDrained(ThreadID tid);
304
305 /** Switches out this CPU. */
306 void switchOut() override;
307
308 /** Takes over from another CPU. */
309 void takeOverFrom(BaseCPU *oldCPU) override;
310
311 void verifyMemoryMode() const override;
312
313 /** Get the current instruction sequence number, and increment it. */
314 InstSeqNum getAndIncrementInstSeq()
315 { return globalSeqNum++; }
316
317 /** Traps to handle given fault. */
318 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
319
320 /** Check if a change in renaming is needed for vector registers.
321 * The vecMode variable is updated and propagated to rename maps.
322 *
323 * @param tid ThreadID
324 * @param freelist list of free registers
325 */
326 void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
327
328 /** Returns the Fault for any valid interrupt. */
329 Fault getInterrupts();
330
331 /** Processes any an interrupt fault. */
332 void processInterrupts(const Fault &interrupt);
333
334 /** Halts the CPU. */
335 void halt() { panic("Halt not implemented!\n"); }
336
337 /** Register accessors. Index refers to the physical register index. */
338
339 /** Reads a miscellaneous register. */
340 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
341
342 /** Reads a misc. register, including any side effects the read
343 * might have as defined by the architecture.
344 */
345 RegVal readMiscReg(int misc_reg, ThreadID tid);
346
347 /** Sets a miscellaneous register. */
348 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
349
350 /** Sets a misc. register, including any side effects the write
351 * might have as defined by the architecture.
352 */
353 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
354
355 RegVal readIntReg(PhysRegIdPtr phys_reg);
356
357 RegVal readFloatReg(PhysRegIdPtr phys_reg);
358
359 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
360
361 /**
362 * Read physical vector register for modification.
363 */
364 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
365
366 /** Returns current vector renaming mode */
367 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
368
369 /** Sets the current vector renaming mode */
370 void vecRenameMode(Enums::VecRegRenameMode vec_mode)
371 { vecMode = vec_mode; }
372
373 /**
374 * Read physical vector register lane
375 */
376 template<typename VecElem, int LaneIdx>
377 VecLaneT<VecElem, true>
378 readVecLane(PhysRegIdPtr phys_reg) const
379 {
380 vecRegfileReads++;
381 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
382 }
383
384 /**
385 * Read physical vector register lane
386 */
387 template<typename VecElem>
388 VecLaneT<VecElem, true>
389 readVecLane(PhysRegIdPtr phys_reg) const
390 {
391 vecRegfileReads++;
392 return regFile.readVecLane<VecElem>(phys_reg);
393 }
394
395 /** Write a lane of the destination vector register. */
396 template<typename LD>
397 void
398 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
399 {
400 vecRegfileWrites++;
401 return regFile.setVecLane(phys_reg, val);
402 }
403
404 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
405
406 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
407
408 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
409
410 RegVal readCCReg(PhysRegIdPtr phys_reg);
411
412 void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
413
414 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
415
416 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
417
418 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
419
420 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
421
422 void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
423
424 RegVal readArchIntReg(int reg_idx, ThreadID tid);
425
426 RegVal readArchFloatReg(int reg_idx, ThreadID tid);
427
428 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
429 /** Read architectural vector register for modification. */
430 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
431
432 /** Read architectural vector register lane. */
433 template<typename VecElem>
434 VecLaneT<VecElem, true>
435 readArchVecLane(int reg_idx, int lId, ThreadID tid) const
436 {
437 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
438 RegId(VecRegClass, reg_idx));
439 return readVecLane<VecElem>(phys_reg);
440 }
441
442
443 /** Write a lane of the destination vector register. */
444 template<typename LD>
445 void
446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
447 {
448 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
449 RegId(VecRegClass, reg_idx));
450 setVecLane(phys_reg, val);
451 }
452
453 const VecElem& readArchVecElem(const RegIndex& reg_idx,
454 const ElemIndex& ldx, ThreadID tid) const;
455
456 const VecPredRegContainer& readArchVecPredReg(int reg_idx,
457 ThreadID tid) const;
458
459 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
460
461 RegVal readArchCCReg(int reg_idx, ThreadID tid);
462
463 /** Architectural register accessors. Looks up in the commit
464 * rename table to obtain the true physical index of the
465 * architected register first, then accesses that physical
466 * register.
467 */
468 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
469
470 void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
471
472 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
473 ThreadID tid);
474
475 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
476
477 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
478 const VecElem& val, ThreadID tid);
479
480 void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
481
482 /** Sets the commit PC state of a specific thread. */
483 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
484
485 /** Reads the commit PC state of a specific thread. */
486 TheISA::PCState pcState(ThreadID tid);
487
488 /** Reads the commit PC of a specific thread. */
489 Addr instAddr(ThreadID tid);
490
491 /** Reads the commit micro PC of a specific thread. */
492 MicroPC microPC(ThreadID tid);
493
494 /** Reads the next PC of a specific thread. */
495 Addr nextInstAddr(ThreadID tid);
496
497 /** Initiates a squash of all in-flight instructions for a given
498 * thread. The source of the squash is an external update of
499 * state through the TC.
500 */
501 void squashFromTC(ThreadID tid);
502
503 /** Function to add instruction onto the head of the list of the
504 * instructions. Used when new instructions are fetched.
505 */
506 ListIt addInst(const DynInstPtr &inst);
507
508 /** Function to tell the CPU that an instruction has completed. */
509 void instDone(ThreadID tid, const DynInstPtr &inst);
510
511 /** Remove an instruction from the front end of the list. There's
512 * no restriction on location of the instruction.
513 */
514 void removeFrontInst(const DynInstPtr &inst);
515
516 /** Remove all instructions that are not currently in the ROB.
517 * There's also an option to not squash delay slot instructions.*/
518 void removeInstsNotInROB(ThreadID tid);
519
520 /** Remove all instructions younger than the given sequence number. */
521 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
522
523 /** Removes the instruction pointed to by the iterator. */
524 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
525
526 /** Cleans up all instructions on the remove list. */
527 void cleanUpRemovedInsts();
528
529 /** Debug function to print all instructions on the list. */
530 void dumpInsts();
531
532 public:
533#ifndef NDEBUG
534 /** Count of total number of dynamic instructions in flight. */
535 int instcount;
536#endif
537
538 /** List of all the instructions in flight. */
539 std::list<DynInstPtr> instList;
540
541 /** List of all the instructions that will be removed at the end of this
542 * cycle.
543 */
544 std::queue<ListIt> removeList;
545
546#ifdef DEBUG
547 /** Debug structure to keep track of the sequence numbers still in
548 * flight.
549 */
550 std::set<InstSeqNum> snList;
551#endif
552
553 /** Records if instructions need to be removed this cycle due to
554 * being retired or squashed.
555 */
556 bool removeInstsThisCycle;
557
558 protected:
559 /** The fetch stage. */
560 typename CPUPolicy::Fetch fetch;
561
562 /** The decode stage. */
563 typename CPUPolicy::Decode decode;
564
565 /** The dispatch stage. */
566 typename CPUPolicy::Rename rename;
567
568 /** The issue/execute/writeback stages. */
569 typename CPUPolicy::IEW iew;
570
571 /** The commit stage. */
572 typename CPUPolicy::Commit commit;
573
574 /** The rename mode of the vector registers */
575 Enums::VecRegRenameMode vecMode;
576
577 /** The register file. */
578 PhysRegFile regFile;
579
580 /** The free list. */
581 typename CPUPolicy::FreeList freeList;
582
583 /** The rename map. */
584 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
585
586 /** The commit rename map. */
587 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
588
589 /** The re-order buffer. */
590 typename CPUPolicy::ROB rob;
591
592 /** Active Threads List */
593 std::list<ThreadID> activeThreads;
594
595 /**
596 * This is a list of threads that are trying to exit. Each thread id
597 * is mapped to a boolean value denoting whether the thread is ready
598 * to exit.
599 */
600 std::unordered_map<ThreadID, bool> exitingThreads;
601
602 /** Integer Register Scoreboard */
603 Scoreboard scoreboard;
604
605 std::vector<TheISA::ISA *> isa;
606
607 public:
608 /** Enum to give each stage a specific index, so when calling
609 * activateStage() or deactivateStage(), they can specify which stage
610 * is being activated/deactivated.
611 */
612 enum StageIdx {
613 FetchIdx,
614 DecodeIdx,
615 RenameIdx,
616 IEWIdx,
617 CommitIdx,
618 NumStages };
619
620 /** Typedefs from the Impl to get the structs that each of the
621 * time buffers should use.
622 */
623 typedef typename CPUPolicy::TimeStruct TimeStruct;
624
625 typedef typename CPUPolicy::FetchStruct FetchStruct;
626
627 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
628
629 typedef typename CPUPolicy::RenameStruct RenameStruct;
630
631 typedef typename CPUPolicy::IEWStruct IEWStruct;
632
633 /** The main time buffer to do backwards communication. */
634 TimeBuffer<TimeStruct> timeBuffer;
635
636 /** The fetch stage's instruction queue. */
637 TimeBuffer<FetchStruct> fetchQueue;
638
639 /** The decode stage's instruction queue. */
640 TimeBuffer<DecodeStruct> decodeQueue;
641
642 /** The rename stage's instruction queue. */
643 TimeBuffer<RenameStruct> renameQueue;
644
645 /** The IEW stage's instruction queue. */
646 TimeBuffer<IEWStruct> iewQueue;
647
648 private:
649 /** The activity recorder; used to tell if the CPU has any
650 * activity remaining or if it can go to idle and deschedule
651 * itself.
652 */
653 ActivityRecorder activityRec;
654
655 public:
656 /** Records that there was time buffer activity this cycle. */
657 void activityThisCycle() { activityRec.activity(); }
658
659 /** Changes a stage's status to active within the activity recorder. */
660 void activateStage(const StageIdx idx)
661 { activityRec.activateStage(idx); }
662
663 /** Changes a stage's status to inactive within the activity recorder. */
664 void deactivateStage(const StageIdx idx)
665 { activityRec.deactivateStage(idx); }
666
667 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
668 void wakeCPU();
669
670 virtual void wakeup(ThreadID tid) override;
671
672 /** Gets a free thread id. Use if thread ids change across system. */
673 ThreadID getFreeTid();
674
675 public:
676 /** Returns a pointer to a thread context. */
677 ThreadContext *
678 tcBase(ThreadID tid)
679 {
680 return thread[tid]->getTC();
681 }
682
683 /** The global sequence number counter. */
684 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
685
686 /** Pointer to the checker, which can dynamically verify
687 * instruction results at run time. This can be set to NULL if it
688 * is not being used.
689 */
690 Checker<Impl> *checker;
691
692 /** Pointer to the system. */
693 System *system;
694
695 /** Pointers to all of the threads in the CPU. */
696 std::vector<Thread *> thread;
697
698 /** Threads Scheduled to Enter CPU */
699 std::list<int> cpuWaitList;
700
701 /** The cycle that the CPU was last running, used for statistics. */
702 Cycles lastRunningCycle;
703
704 /** The cycle that the CPU was last activated by a new thread*/
705 Tick lastActivatedCycle;
706
707 /** Mapping for system thread id to cpu id */
708 std::map<ThreadID, unsigned> threadMap;
709
710 /** Available thread ids in the cpu*/
711 std::vector<ThreadID> tids;
712
713 /** CPU pushRequest function, forwards request to LSQ. */
714 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
715 unsigned int size, Addr addr, Request::Flags flags,
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