1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/generic/types.hh"
57#include "arch/types.hh"
58#include "base/statistics.hh"
59#include "config/the_isa.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"
65#include "cpu/base.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/timebuf.hh"
68//#include "cpu/o3/thread_context.hh"
69#include "params/DerivO3CPU.hh"
70#include "sim/process.hh"
71
72template <class>
73class Checker;
74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class MemObject;
80class Process;
81
82struct BaseCPUParams;
83
84class BaseO3CPU : public BaseCPU
85{
86 //Stuff that's pretty ISA independent will go here.
87 public:
88 BaseO3CPU(BaseCPUParams *params);
89
90 void regStats();
91};
92
93/**
94 * FullO3CPU class, has each of the stages (fetch through commit)
95 * within it, as well as all of the time buffers between stages. The
96 * tick() function for the CPU is defined here.
97 */
98template <class Impl>
99class FullO3CPU : public BaseO3CPU
100{
101 public:
102 // Typedefs from the Impl here.
103 typedef typename Impl::CPUPol CPUPolicy;
104 typedef typename Impl::DynInstPtr DynInstPtr;
105 typedef typename Impl::O3CPU O3CPU;
106
107 using VecElem = TheISA::VecElem;
108 using VecRegContainer = TheISA::VecRegContainer;
109
| 1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/generic/types.hh"
57#include "arch/types.hh"
58#include "base/statistics.hh"
59#include "config/the_isa.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"
65#include "cpu/base.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/timebuf.hh"
68//#include "cpu/o3/thread_context.hh"
69#include "params/DerivO3CPU.hh"
70#include "sim/process.hh"
71
72template <class>
73class Checker;
74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class MemObject;
80class Process;
81
82struct BaseCPUParams;
83
84class BaseO3CPU : public BaseCPU
85{
86 //Stuff that's pretty ISA independent will go here.
87 public:
88 BaseO3CPU(BaseCPUParams *params);
89
90 void regStats();
91};
92
93/**
94 * FullO3CPU class, has each of the stages (fetch through commit)
95 * within it, as well as all of the time buffers between stages. The
96 * tick() function for the CPU is defined here.
97 */
98template <class Impl>
99class FullO3CPU : public BaseO3CPU
100{
101 public:
102 // Typedefs from the Impl here.
103 typedef typename Impl::CPUPol CPUPolicy;
104 typedef typename Impl::DynInstPtr DynInstPtr;
105 typedef typename Impl::O3CPU O3CPU;
106
107 using VecElem = TheISA::VecElem;
108 using VecRegContainer = TheISA::VecRegContainer;
109
|
| 110 using VecPredRegContainer = TheISA::VecPredRegContainer;
111
|
110 typedef O3ThreadState<Impl> ImplState;
111 typedef O3ThreadState<Impl> Thread;
112
113 typedef typename std::list<DynInstPtr>::iterator ListIt;
114
115 friend class O3ThreadContext<Impl>;
116
117 public:
118 enum Status {
119 Running,
120 Idle,
121 Halted,
122 Blocked,
123 SwitchedOut
124 };
125
126 BaseTLB *itb;
127 BaseTLB *dtb;
128 using LSQRequest = typename LSQ<Impl>::LSQRequest;
129
130 /** Overall CPU status. */
131 Status _status;
132
133 private:
134
135 /**
136 * IcachePort class for instruction fetch.
137 */
138 class IcachePort : public MasterPort
139 {
140 protected:
141 /** Pointer to fetch. */
142 DefaultFetch<Impl> *fetch;
143
144 public:
145 /** Default constructor. */
146 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
147 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
148 { }
149
150 protected:
151
152 /** Timing version of receive. Handles setting fetch to the
153 * proper status to start fetching. */
154 virtual bool recvTimingResp(PacketPtr pkt);
155
156 /** Handles doing a retry of a failed fetch. */
157 virtual void recvReqRetry();
158 };
159
160 /**
161 * DcachePort class for the load/store queue.
162 */
163 class DcachePort : public MasterPort
164 {
165 protected:
166
167 /** Pointer to LSQ. */
168 LSQ<Impl> *lsq;
169 FullO3CPU<Impl> *cpu;
170
171 public:
172 /** Default constructor. */
173 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
174 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
175 cpu(_cpu)
176 { }
177
178 protected:
179
180 /** Timing version of receive. Handles writing back and
181 * completing the load or store that has returned from
182 * memory. */
183 virtual bool recvTimingResp(PacketPtr pkt);
184 virtual void recvTimingSnoopReq(PacketPtr pkt);
185
186 virtual void recvFunctionalSnoop(PacketPtr pkt)
187 {
188 // @todo: Is there a need for potential invalidation here?
189 }
190
191 /** Handles doing a retry of the previous send. */
192 virtual void recvReqRetry();
193
194 /**
195 * As this CPU requires snooping to maintain the load store queue
196 * change the behaviour from the base CPU port.
197 *
198 * @return true since we have to snoop
199 */
200 virtual bool isSnooping() const { return true; }
201 };
202
203 /** The tick event used for scheduling CPU ticks. */
204 EventFunctionWrapper tickEvent;
205
206 /** Schedule tick event, regardless of its current state. */
207 void scheduleTickEvent(Cycles delay)
208 {
209 if (tickEvent.squashed())
210 reschedule(tickEvent, clockEdge(delay));
211 else if (!tickEvent.scheduled())
212 schedule(tickEvent, clockEdge(delay));
213 }
214
215 /** Unschedule tick event, regardless of its current state. */
216 void unscheduleTickEvent()
217 {
218 if (tickEvent.scheduled())
219 tickEvent.squash();
220 }
221
222 /**
223 * Check if the pipeline has drained and signal drain done.
224 *
225 * This method checks if a drain has been requested and if the CPU
226 * has drained successfully (i.e., there are no instructions in
227 * the pipeline). If the CPU has drained, it deschedules the tick
228 * event and signals the drain manager.
229 *
230 * @return False if a drain hasn't been requested or the CPU
231 * hasn't drained, true otherwise.
232 */
233 bool tryDrain();
234
235 /**
236 * Perform sanity checks after a drain.
237 *
238 * This method is called from drain() when it has determined that
239 * the CPU is fully drained when gem5 is compiled with the NDEBUG
240 * macro undefined. The intention of this method is to do more
241 * extensive tests than the isDrained() method to weed out any
242 * draining bugs.
243 */
244 void drainSanityCheck() const;
245
246 /** Check if a system is in a drained state. */
247 bool isDrained() const;
248
249 public:
250 /** Constructs a CPU with the given parameters. */
251 FullO3CPU(DerivO3CPUParams *params);
252 /** Destructor. */
253 ~FullO3CPU();
254
255 /** Registers statistics. */
256 void regStats() override;
257
258 ProbePointArg<PacketPtr> *ppInstAccessComplete;
259 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
260
261 /** Register probe points. */
262 void regProbePoints() override;
263
264 void demapPage(Addr vaddr, uint64_t asn)
265 {
266 this->itb->demapPage(vaddr, asn);
267 this->dtb->demapPage(vaddr, asn);
268 }
269
270 void demapInstPage(Addr vaddr, uint64_t asn)
271 {
272 this->itb->demapPage(vaddr, asn);
273 }
274
275 void demapDataPage(Addr vaddr, uint64_t asn)
276 {
277 this->dtb->demapPage(vaddr, asn);
278 }
279
280 /** Ticks CPU, calling tick() on each stage, and checking the overall
281 * activity to see if the CPU should deschedule itself.
282 */
283 void tick();
284
285 /** Initialize the CPU */
286 void init() override;
287
288 void startup() override;
289
290 /** Returns the Number of Active Threads in the CPU */
291 int numActiveThreads()
292 { return activeThreads.size(); }
293
294 /** Add Thread to Active Threads List */
295 void activateThread(ThreadID tid);
296
297 /** Remove Thread from Active Threads List */
298 void deactivateThread(ThreadID tid);
299
300 /** Setup CPU to insert a thread's context */
301 void insertThread(ThreadID tid);
302
303 /** Remove all of a thread's context from CPU */
304 void removeThread(ThreadID tid);
305
306 /** Count the Total Instructions Committed in the CPU. */
307 Counter totalInsts() const override;
308
309 /** Count the Total Ops (including micro ops) committed in the CPU. */
310 Counter totalOps() const override;
311
312 /** Add Thread to Active Threads List. */
313 void activateContext(ThreadID tid) override;
314
315 /** Remove Thread from Active Threads List */
316 void suspendContext(ThreadID tid) override;
317
318 /** Remove Thread from Active Threads List &&
319 * Remove Thread Context from CPU.
320 */
321 void haltContext(ThreadID tid) override;
322
323 /** Update The Order In Which We Process Threads. */
324 void updateThreadPriority();
325
326 /** Is the CPU draining? */
327 bool isDraining() const { return drainState() == DrainState::Draining; }
328
329 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
330 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
331
332 public:
333 /** Executes a syscall.
334 * @todo: Determine if this needs to be virtual.
335 */
336 void syscall(int64_t callnum, ThreadID tid, Fault *fault);
337
338 /** Starts draining the CPU's pipeline of all instructions in
339 * order to stop all memory accesses. */
340 DrainState drain() override;
341
342 /** Resumes execution after a drain. */
343 void drainResume() override;
344
345 /**
346 * Commit has reached a safe point to drain a thread.
347 *
348 * Commit calls this method to inform the pipeline that it has
349 * reached a point where it is not executed microcode and is about
350 * to squash uncommitted instructions to fully drain the pipeline.
351 */
352 void commitDrained(ThreadID tid);
353
354 /** Switches out this CPU. */
355 void switchOut() override;
356
357 /** Takes over from another CPU. */
358 void takeOverFrom(BaseCPU *oldCPU) override;
359
360 void verifyMemoryMode() const override;
361
362 /** Get the current instruction sequence number, and increment it. */
363 InstSeqNum getAndIncrementInstSeq()
364 { return globalSeqNum++; }
365
366 /** Traps to handle given fault. */
367 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
368
369 /** HW return from error interrupt. */
370 Fault hwrei(ThreadID tid);
371
372 bool simPalCheck(int palFunc, ThreadID tid);
373
374 /** Check if a change in renaming is needed for vector registers.
375 * The vecMode variable is updated and propagated to rename maps.
376 *
377 * @param tid ThreadID
378 * @param freelist list of free registers
379 */
380 void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
381
382 /** Returns the Fault for any valid interrupt. */
383 Fault getInterrupts();
384
385 /** Processes any an interrupt fault. */
386 void processInterrupts(const Fault &interrupt);
387
388 /** Halts the CPU. */
389 void halt() { panic("Halt not implemented!\n"); }
390
391 /** Register accessors. Index refers to the physical register index. */
392
393 /** Reads a miscellaneous register. */
394 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
395
396 /** Reads a misc. register, including any side effects the read
397 * might have as defined by the architecture.
398 */
399 RegVal readMiscReg(int misc_reg, ThreadID tid);
400
401 /** Sets a miscellaneous register. */
402 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
403
404 /** Sets a misc. register, including any side effects the write
405 * might have as defined by the architecture.
406 */
407 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
408
409 RegVal readIntReg(PhysRegIdPtr phys_reg);
410
411 RegVal readFloatRegBits(PhysRegIdPtr phys_reg);
412
413 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
414
415 /**
416 * Read physical vector register for modification.
417 */
418 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
419
420 /** Returns current vector renaming mode */
421 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
422
423 /** Sets the current vector renaming mode */
424 void vecRenameMode(Enums::VecRegRenameMode vec_mode)
425 { vecMode = vec_mode; }
426
427 /**
428 * Read physical vector register lane
429 */
430 template<typename VecElem, int LaneIdx>
431 VecLaneT<VecElem, true>
432 readVecLane(PhysRegIdPtr phys_reg) const
433 {
434 vecRegfileReads++;
435 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
436 }
437
438 /**
439 * Read physical vector register lane
440 */
441 template<typename VecElem>
442 VecLaneT<VecElem, true>
443 readVecLane(PhysRegIdPtr phys_reg) const
444 {
445 vecRegfileReads++;
446 return regFile.readVecLane<VecElem>(phys_reg);
447 }
448
449 /** Write a lane of the destination vector register. */
450 template<typename LD>
451 void
452 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
453 {
454 vecRegfileWrites++;
455 return regFile.setVecLane(phys_reg, val);
456 }
457
458 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
459
| 112 typedef O3ThreadState<Impl> ImplState;
113 typedef O3ThreadState<Impl> Thread;
114
115 typedef typename std::list<DynInstPtr>::iterator ListIt;
116
117 friend class O3ThreadContext<Impl>;
118
119 public:
120 enum Status {
121 Running,
122 Idle,
123 Halted,
124 Blocked,
125 SwitchedOut
126 };
127
128 BaseTLB *itb;
129 BaseTLB *dtb;
130 using LSQRequest = typename LSQ<Impl>::LSQRequest;
131
132 /** Overall CPU status. */
133 Status _status;
134
135 private:
136
137 /**
138 * IcachePort class for instruction fetch.
139 */
140 class IcachePort : public MasterPort
141 {
142 protected:
143 /** Pointer to fetch. */
144 DefaultFetch<Impl> *fetch;
145
146 public:
147 /** Default constructor. */
148 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
149 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
150 { }
151
152 protected:
153
154 /** Timing version of receive. Handles setting fetch to the
155 * proper status to start fetching. */
156 virtual bool recvTimingResp(PacketPtr pkt);
157
158 /** Handles doing a retry of a failed fetch. */
159 virtual void recvReqRetry();
160 };
161
162 /**
163 * DcachePort class for the load/store queue.
164 */
165 class DcachePort : public MasterPort
166 {
167 protected:
168
169 /** Pointer to LSQ. */
170 LSQ<Impl> *lsq;
171 FullO3CPU<Impl> *cpu;
172
173 public:
174 /** Default constructor. */
175 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
176 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
177 cpu(_cpu)
178 { }
179
180 protected:
181
182 /** Timing version of receive. Handles writing back and
183 * completing the load or store that has returned from
184 * memory. */
185 virtual bool recvTimingResp(PacketPtr pkt);
186 virtual void recvTimingSnoopReq(PacketPtr pkt);
187
188 virtual void recvFunctionalSnoop(PacketPtr pkt)
189 {
190 // @todo: Is there a need for potential invalidation here?
191 }
192
193 /** Handles doing a retry of the previous send. */
194 virtual void recvReqRetry();
195
196 /**
197 * As this CPU requires snooping to maintain the load store queue
198 * change the behaviour from the base CPU port.
199 *
200 * @return true since we have to snoop
201 */
202 virtual bool isSnooping() const { return true; }
203 };
204
205 /** The tick event used for scheduling CPU ticks. */
206 EventFunctionWrapper tickEvent;
207
208 /** Schedule tick event, regardless of its current state. */
209 void scheduleTickEvent(Cycles delay)
210 {
211 if (tickEvent.squashed())
212 reschedule(tickEvent, clockEdge(delay));
213 else if (!tickEvent.scheduled())
214 schedule(tickEvent, clockEdge(delay));
215 }
216
217 /** Unschedule tick event, regardless of its current state. */
218 void unscheduleTickEvent()
219 {
220 if (tickEvent.scheduled())
221 tickEvent.squash();
222 }
223
224 /**
225 * Check if the pipeline has drained and signal drain done.
226 *
227 * This method checks if a drain has been requested and if the CPU
228 * has drained successfully (i.e., there are no instructions in
229 * the pipeline). If the CPU has drained, it deschedules the tick
230 * event and signals the drain manager.
231 *
232 * @return False if a drain hasn't been requested or the CPU
233 * hasn't drained, true otherwise.
234 */
235 bool tryDrain();
236
237 /**
238 * Perform sanity checks after a drain.
239 *
240 * This method is called from drain() when it has determined that
241 * the CPU is fully drained when gem5 is compiled with the NDEBUG
242 * macro undefined. The intention of this method is to do more
243 * extensive tests than the isDrained() method to weed out any
244 * draining bugs.
245 */
246 void drainSanityCheck() const;
247
248 /** Check if a system is in a drained state. */
249 bool isDrained() const;
250
251 public:
252 /** Constructs a CPU with the given parameters. */
253 FullO3CPU(DerivO3CPUParams *params);
254 /** Destructor. */
255 ~FullO3CPU();
256
257 /** Registers statistics. */
258 void regStats() override;
259
260 ProbePointArg<PacketPtr> *ppInstAccessComplete;
261 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
262
263 /** Register probe points. */
264 void regProbePoints() override;
265
266 void demapPage(Addr vaddr, uint64_t asn)
267 {
268 this->itb->demapPage(vaddr, asn);
269 this->dtb->demapPage(vaddr, asn);
270 }
271
272 void demapInstPage(Addr vaddr, uint64_t asn)
273 {
274 this->itb->demapPage(vaddr, asn);
275 }
276
277 void demapDataPage(Addr vaddr, uint64_t asn)
278 {
279 this->dtb->demapPage(vaddr, asn);
280 }
281
282 /** Ticks CPU, calling tick() on each stage, and checking the overall
283 * activity to see if the CPU should deschedule itself.
284 */
285 void tick();
286
287 /** Initialize the CPU */
288 void init() override;
289
290 void startup() override;
291
292 /** Returns the Number of Active Threads in the CPU */
293 int numActiveThreads()
294 { return activeThreads.size(); }
295
296 /** Add Thread to Active Threads List */
297 void activateThread(ThreadID tid);
298
299 /** Remove Thread from Active Threads List */
300 void deactivateThread(ThreadID tid);
301
302 /** Setup CPU to insert a thread's context */
303 void insertThread(ThreadID tid);
304
305 /** Remove all of a thread's context from CPU */
306 void removeThread(ThreadID tid);
307
308 /** Count the Total Instructions Committed in the CPU. */
309 Counter totalInsts() const override;
310
311 /** Count the Total Ops (including micro ops) committed in the CPU. */
312 Counter totalOps() const override;
313
314 /** Add Thread to Active Threads List. */
315 void activateContext(ThreadID tid) override;
316
317 /** Remove Thread from Active Threads List */
318 void suspendContext(ThreadID tid) override;
319
320 /** Remove Thread from Active Threads List &&
321 * Remove Thread Context from CPU.
322 */
323 void haltContext(ThreadID tid) override;
324
325 /** Update The Order In Which We Process Threads. */
326 void updateThreadPriority();
327
328 /** Is the CPU draining? */
329 bool isDraining() const { return drainState() == DrainState::Draining; }
330
331 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
332 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
333
334 public:
335 /** Executes a syscall.
336 * @todo: Determine if this needs to be virtual.
337 */
338 void syscall(int64_t callnum, ThreadID tid, Fault *fault);
339
340 /** Starts draining the CPU's pipeline of all instructions in
341 * order to stop all memory accesses. */
342 DrainState drain() override;
343
344 /** Resumes execution after a drain. */
345 void drainResume() override;
346
347 /**
348 * Commit has reached a safe point to drain a thread.
349 *
350 * Commit calls this method to inform the pipeline that it has
351 * reached a point where it is not executed microcode and is about
352 * to squash uncommitted instructions to fully drain the pipeline.
353 */
354 void commitDrained(ThreadID tid);
355
356 /** Switches out this CPU. */
357 void switchOut() override;
358
359 /** Takes over from another CPU. */
360 void takeOverFrom(BaseCPU *oldCPU) override;
361
362 void verifyMemoryMode() const override;
363
364 /** Get the current instruction sequence number, and increment it. */
365 InstSeqNum getAndIncrementInstSeq()
366 { return globalSeqNum++; }
367
368 /** Traps to handle given fault. */
369 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
370
371 /** HW return from error interrupt. */
372 Fault hwrei(ThreadID tid);
373
374 bool simPalCheck(int palFunc, ThreadID tid);
375
376 /** Check if a change in renaming is needed for vector registers.
377 * The vecMode variable is updated and propagated to rename maps.
378 *
379 * @param tid ThreadID
380 * @param freelist list of free registers
381 */
382 void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
383
384 /** Returns the Fault for any valid interrupt. */
385 Fault getInterrupts();
386
387 /** Processes any an interrupt fault. */
388 void processInterrupts(const Fault &interrupt);
389
390 /** Halts the CPU. */
391 void halt() { panic("Halt not implemented!\n"); }
392
393 /** Register accessors. Index refers to the physical register index. */
394
395 /** Reads a miscellaneous register. */
396 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
397
398 /** Reads a misc. register, including any side effects the read
399 * might have as defined by the architecture.
400 */
401 RegVal readMiscReg(int misc_reg, ThreadID tid);
402
403 /** Sets a miscellaneous register. */
404 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
405
406 /** Sets a misc. register, including any side effects the write
407 * might have as defined by the architecture.
408 */
409 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
410
411 RegVal readIntReg(PhysRegIdPtr phys_reg);
412
413 RegVal readFloatRegBits(PhysRegIdPtr phys_reg);
414
415 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
416
417 /**
418 * Read physical vector register for modification.
419 */
420 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
421
422 /** Returns current vector renaming mode */
423 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
424
425 /** Sets the current vector renaming mode */
426 void vecRenameMode(Enums::VecRegRenameMode vec_mode)
427 { vecMode = vec_mode; }
428
429 /**
430 * Read physical vector register lane
431 */
432 template<typename VecElem, int LaneIdx>
433 VecLaneT<VecElem, true>
434 readVecLane(PhysRegIdPtr phys_reg) const
435 {
436 vecRegfileReads++;
437 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
438 }
439
440 /**
441 * Read physical vector register lane
442 */
443 template<typename VecElem>
444 VecLaneT<VecElem, true>
445 readVecLane(PhysRegIdPtr phys_reg) const
446 {
447 vecRegfileReads++;
448 return regFile.readVecLane<VecElem>(phys_reg);
449 }
450
451 /** Write a lane of the destination vector register. */
452 template<typename LD>
453 void
454 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
455 {
456 vecRegfileWrites++;
457 return regFile.setVecLane(phys_reg, val);
458 }
459
460 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
461
|
| 462 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
463
464 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
465
|
460 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
461
462 void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
463
464 void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val);
465
466 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
467
468 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
469
| 466 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
467
468 void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
469
470 void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val);
471
472 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
473
474 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
475
|
| 476 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
477
|
470 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
471
472 RegVal readArchIntReg(int reg_idx, ThreadID tid);
473
474 RegVal readArchFloatRegBits(int reg_idx, ThreadID tid);
475
476 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
477 /** Read architectural vector register for modification. */
478 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
479
480 /** Read architectural vector register lane. */
481 template<typename VecElem>
482 VecLaneT<VecElem, true>
483 readArchVecLane(int reg_idx, int lId, ThreadID tid) const
484 {
485 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
486 RegId(VecRegClass, reg_idx));
487 return readVecLane<VecElem>(phys_reg);
488 }
489
490
491 /** Write a lane of the destination vector register. */
492 template<typename LD>
493 void
494 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
495 {
496 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
497 RegId(VecRegClass, reg_idx));
498 setVecLane(phys_reg, val);
499 }
500
501 const VecElem& readArchVecElem(const RegIndex& reg_idx,
502 const ElemIndex& ldx, ThreadID tid) const;
503
| 478 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
479
480 RegVal readArchIntReg(int reg_idx, ThreadID tid);
481
482 RegVal readArchFloatRegBits(int reg_idx, ThreadID tid);
483
484 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
485 /** Read architectural vector register for modification. */
486 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
487
488 /** Read architectural vector register lane. */
489 template<typename VecElem>
490 VecLaneT<VecElem, true>
491 readArchVecLane(int reg_idx, int lId, ThreadID tid) const
492 {
493 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
494 RegId(VecRegClass, reg_idx));
495 return readVecLane<VecElem>(phys_reg);
496 }
497
498
499 /** Write a lane of the destination vector register. */
500 template<typename LD>
501 void
502 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
503 {
504 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
505 RegId(VecRegClass, reg_idx));
506 setVecLane(phys_reg, val);
507 }
508
509 const VecElem& readArchVecElem(const RegIndex& reg_idx,
510 const ElemIndex& ldx, ThreadID tid) const;
511
|
| 512 const VecPredRegContainer& readArchVecPredReg(int reg_idx,
513 ThreadID tid) const;
514
515 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
516
|
504 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
505
506 /** Architectural register accessors. Looks up in the commit
507 * rename table to obtain the true physical index of the
508 * architected register first, then accesses that physical
509 * register.
510 */
511 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
512
513 void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid);
514
| 517 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
518
519 /** Architectural register accessors. Looks up in the commit
520 * rename table to obtain the true physical index of the
521 * architected register first, then accesses that physical
522 * register.
523 */
524 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
525
526 void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid);
527
|
| 528 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
529 ThreadID tid);
530
|
515 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
516
517 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
518 const VecElem& val, ThreadID tid);
519
520 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
521
522 /** Sets the commit PC state of a specific thread. */
523 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
524
525 /** Reads the commit PC state of a specific thread. */
526 TheISA::PCState pcState(ThreadID tid);
527
528 /** Reads the commit PC of a specific thread. */
529 Addr instAddr(ThreadID tid);
530
531 /** Reads the commit micro PC of a specific thread. */
532 MicroPC microPC(ThreadID tid);
533
534 /** Reads the next PC of a specific thread. */
535 Addr nextInstAddr(ThreadID tid);
536
537 /** Initiates a squash of all in-flight instructions for a given
538 * thread. The source of the squash is an external update of
539 * state through the TC.
540 */
541 void squashFromTC(ThreadID tid);
542
543 /** Function to add instruction onto the head of the list of the
544 * instructions. Used when new instructions are fetched.
545 */
546 ListIt addInst(const DynInstPtr &inst);
547
548 /** Function to tell the CPU that an instruction has completed. */
549 void instDone(ThreadID tid, const DynInstPtr &inst);
550
551 /** Remove an instruction from the front end of the list. There's
552 * no restriction on location of the instruction.
553 */
554 void removeFrontInst(const DynInstPtr &inst);
555
556 /** Remove all instructions that are not currently in the ROB.
557 * There's also an option to not squash delay slot instructions.*/
558 void removeInstsNotInROB(ThreadID tid);
559
560 /** Remove all instructions younger than the given sequence number. */
561 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
562
563 /** Removes the instruction pointed to by the iterator. */
564 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
565
566 /** Cleans up all instructions on the remove list. */
567 void cleanUpRemovedInsts();
568
569 /** Debug function to print all instructions on the list. */
570 void dumpInsts();
571
572 public:
573#ifndef NDEBUG
574 /** Count of total number of dynamic instructions in flight. */
575 int instcount;
576#endif
577
578 /** List of all the instructions in flight. */
579 std::list<DynInstPtr> instList;
580
581 /** List of all the instructions that will be removed at the end of this
582 * cycle.
583 */
584 std::queue<ListIt> removeList;
585
586#ifdef DEBUG
587 /** Debug structure to keep track of the sequence numbers still in
588 * flight.
589 */
590 std::set<InstSeqNum> snList;
591#endif
592
593 /** Records if instructions need to be removed this cycle due to
594 * being retired or squashed.
595 */
596 bool removeInstsThisCycle;
597
598 protected:
599 /** The fetch stage. */
600 typename CPUPolicy::Fetch fetch;
601
602 /** The decode stage. */
603 typename CPUPolicy::Decode decode;
604
605 /** The dispatch stage. */
606 typename CPUPolicy::Rename rename;
607
608 /** The issue/execute/writeback stages. */
609 typename CPUPolicy::IEW iew;
610
611 /** The commit stage. */
612 typename CPUPolicy::Commit commit;
613
614 /** The rename mode of the vector registers */
615 Enums::VecRegRenameMode vecMode;
616
617 /** The register file. */
618 PhysRegFile regFile;
619
620 /** The free list. */
621 typename CPUPolicy::FreeList freeList;
622
623 /** The rename map. */
624 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
625
626 /** The commit rename map. */
627 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
628
629 /** The re-order buffer. */
630 typename CPUPolicy::ROB rob;
631
632 /** Active Threads List */
633 std::list<ThreadID> activeThreads;
634
635 /** Integer Register Scoreboard */
636 Scoreboard scoreboard;
637
638 std::vector<TheISA::ISA *> isa;
639
640 /** Instruction port. Note that it has to appear after the fetch stage. */
641 IcachePort icachePort;
642
643 /** Data port. Note that it has to appear after the iew stages */
644 DcachePort dcachePort;
645
646 public:
647 /** Enum to give each stage a specific index, so when calling
648 * activateStage() or deactivateStage(), they can specify which stage
649 * is being activated/deactivated.
650 */
651 enum StageIdx {
652 FetchIdx,
653 DecodeIdx,
654 RenameIdx,
655 IEWIdx,
656 CommitIdx,
657 NumStages };
658
659 /** Typedefs from the Impl to get the structs that each of the
660 * time buffers should use.
661 */
662 typedef typename CPUPolicy::TimeStruct TimeStruct;
663
664 typedef typename CPUPolicy::FetchStruct FetchStruct;
665
666 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
667
668 typedef typename CPUPolicy::RenameStruct RenameStruct;
669
670 typedef typename CPUPolicy::IEWStruct IEWStruct;
671
672 /** The main time buffer to do backwards communication. */
673 TimeBuffer<TimeStruct> timeBuffer;
674
675 /** The fetch stage's instruction queue. */
676 TimeBuffer<FetchStruct> fetchQueue;
677
678 /** The decode stage's instruction queue. */
679 TimeBuffer<DecodeStruct> decodeQueue;
680
681 /** The rename stage's instruction queue. */
682 TimeBuffer<RenameStruct> renameQueue;
683
684 /** The IEW stage's instruction queue. */
685 TimeBuffer<IEWStruct> iewQueue;
686
687 private:
688 /** The activity recorder; used to tell if the CPU has any
689 * activity remaining or if it can go to idle and deschedule
690 * itself.
691 */
692 ActivityRecorder activityRec;
693
694 public:
695 /** Records that there was time buffer activity this cycle. */
696 void activityThisCycle() { activityRec.activity(); }
697
698 /** Changes a stage's status to active within the activity recorder. */
699 void activateStage(const StageIdx idx)
700 { activityRec.activateStage(idx); }
701
702 /** Changes a stage's status to inactive within the activity recorder. */
703 void deactivateStage(const StageIdx idx)
704 { activityRec.deactivateStage(idx); }
705
706 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
707 void wakeCPU();
708
709 virtual void wakeup(ThreadID tid) override;
710
711 /** Gets a free thread id. Use if thread ids change across system. */
712 ThreadID getFreeTid();
713
714 public:
715 /** Returns a pointer to a thread context. */
716 ThreadContext *
717 tcBase(ThreadID tid)
718 {
719 return thread[tid]->getTC();
720 }
721
722 /** The global sequence number counter. */
723 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
724
725 /** Pointer to the checker, which can dynamically verify
726 * instruction results at run time. This can be set to NULL if it
727 * is not being used.
728 */
729 Checker<Impl> *checker;
730
731 /** Pointer to the system. */
732 System *system;
733
734 /** Pointers to all of the threads in the CPU. */
735 std::vector<Thread *> thread;
736
737 /** Threads Scheduled to Enter CPU */
738 std::list<int> cpuWaitList;
739
740 /** The cycle that the CPU was last running, used for statistics. */
741 Cycles lastRunningCycle;
742
743 /** The cycle that the CPU was last activated by a new thread*/
744 Tick lastActivatedCycle;
745
746 /** Mapping for system thread id to cpu id */
747 std::map<ThreadID, unsigned> threadMap;
748
749 /** Available thread ids in the cpu*/
750 std::vector<ThreadID> tids;
751
752 /** CPU pushRequest function, forwards request to LSQ. */
753 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
754 unsigned int size, Addr addr, Request::Flags flags,
755 uint64_t *res)
756 {
757 return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
758 flags, res);
759 }
760
761 /** CPU read function, forwards read to LSQ. */
762 Fault read(LSQRequest* req, int load_idx)
763 {
764 return this->iew.ldstQueue.read(req, load_idx);
765 }
766
767 /** CPU write function, forwards write to LSQ. */
768 Fault write(LSQRequest* req, uint8_t *data, int store_idx)
769 {
770 return this->iew.ldstQueue.write(req, data, store_idx);
771 }
772
773 /** Used by the fetch unit to get a hold of the instruction port. */
774 MasterPort &getInstPort() override { return icachePort; }
775
776 /** Get the dcache port (used to find block size for translations). */
777 MasterPort &getDataPort() override { return dcachePort; }
778
779 /** Stat for total number of times the CPU is descheduled. */
780 Stats::Scalar timesIdled;
781 /** Stat for total number of cycles the CPU spends descheduled. */
782 Stats::Scalar idleCycles;
783 /** Stat for total number of cycles the CPU spends descheduled due to a
784 * quiesce operation or waiting for an interrupt. */
785 Stats::Scalar quiesceCycles;
786 /** Stat for the number of committed instructions per thread. */
787 Stats::Vector committedInsts;
788 /** Stat for the number of committed ops (including micro ops) per thread. */
789 Stats::Vector committedOps;
790 /** Stat for the CPI per thread. */
791 Stats::Formula cpi;
792 /** Stat for the total CPI. */
793 Stats::Formula totalCpi;
794 /** Stat for the IPC per thread. */
795 Stats::Formula ipc;
796 /** Stat for the total IPC. */
797 Stats::Formula totalIpc;
798
799 //number of integer register file accesses
800 Stats::Scalar intRegfileReads;
801 Stats::Scalar intRegfileWrites;
802 //number of float register file accesses
803 Stats::Scalar fpRegfileReads;
804 Stats::Scalar fpRegfileWrites;
805 //number of vector register file accesses
806 mutable Stats::Scalar vecRegfileReads;
807 Stats::Scalar vecRegfileWrites;
| 531 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
532
533 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
534 const VecElem& val, ThreadID tid);
535
536 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
537
538 /** Sets the commit PC state of a specific thread. */
539 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
540
541 /** Reads the commit PC state of a specific thread. */
542 TheISA::PCState pcState(ThreadID tid);
543
544 /** Reads the commit PC of a specific thread. */
545 Addr instAddr(ThreadID tid);
546
547 /** Reads the commit micro PC of a specific thread. */
548 MicroPC microPC(ThreadID tid);
549
550 /** Reads the next PC of a specific thread. */
551 Addr nextInstAddr(ThreadID tid);
552
553 /** Initiates a squash of all in-flight instructions for a given
554 * thread. The source of the squash is an external update of
555 * state through the TC.
556 */
557 void squashFromTC(ThreadID tid);
558
559 /** Function to add instruction onto the head of the list of the
560 * instructions. Used when new instructions are fetched.
561 */
562 ListIt addInst(const DynInstPtr &inst);
563
564 /** Function to tell the CPU that an instruction has completed. */
565 void instDone(ThreadID tid, const DynInstPtr &inst);
566
567 /** Remove an instruction from the front end of the list. There's
568 * no restriction on location of the instruction.
569 */
570 void removeFrontInst(const DynInstPtr &inst);
571
572 /** Remove all instructions that are not currently in the ROB.
573 * There's also an option to not squash delay slot instructions.*/
574 void removeInstsNotInROB(ThreadID tid);
575
576 /** Remove all instructions younger than the given sequence number. */
577 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
578
579 /** Removes the instruction pointed to by the iterator. */
580 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
581
582 /** Cleans up all instructions on the remove list. */
583 void cleanUpRemovedInsts();
584
585 /** Debug function to print all instructions on the list. */
586 void dumpInsts();
587
588 public:
589#ifndef NDEBUG
590 /** Count of total number of dynamic instructions in flight. */
591 int instcount;
592#endif
593
594 /** List of all the instructions in flight. */
595 std::list<DynInstPtr> instList;
596
597 /** List of all the instructions that will be removed at the end of this
598 * cycle.
599 */
600 std::queue<ListIt> removeList;
601
602#ifdef DEBUG
603 /** Debug structure to keep track of the sequence numbers still in
604 * flight.
605 */
606 std::set<InstSeqNum> snList;
607#endif
608
609 /** Records if instructions need to be removed this cycle due to
610 * being retired or squashed.
611 */
612 bool removeInstsThisCycle;
613
614 protected:
615 /** The fetch stage. */
616 typename CPUPolicy::Fetch fetch;
617
618 /** The decode stage. */
619 typename CPUPolicy::Decode decode;
620
621 /** The dispatch stage. */
622 typename CPUPolicy::Rename rename;
623
624 /** The issue/execute/writeback stages. */
625 typename CPUPolicy::IEW iew;
626
627 /** The commit stage. */
628 typename CPUPolicy::Commit commit;
629
630 /** The rename mode of the vector registers */
631 Enums::VecRegRenameMode vecMode;
632
633 /** The register file. */
634 PhysRegFile regFile;
635
636 /** The free list. */
637 typename CPUPolicy::FreeList freeList;
638
639 /** The rename map. */
640 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
641
642 /** The commit rename map. */
643 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
644
645 /** The re-order buffer. */
646 typename CPUPolicy::ROB rob;
647
648 /** Active Threads List */
649 std::list<ThreadID> activeThreads;
650
651 /** Integer Register Scoreboard */
652 Scoreboard scoreboard;
653
654 std::vector<TheISA::ISA *> isa;
655
656 /** Instruction port. Note that it has to appear after the fetch stage. */
657 IcachePort icachePort;
658
659 /** Data port. Note that it has to appear after the iew stages */
660 DcachePort dcachePort;
661
662 public:
663 /** Enum to give each stage a specific index, so when calling
664 * activateStage() or deactivateStage(), they can specify which stage
665 * is being activated/deactivated.
666 */
667 enum StageIdx {
668 FetchIdx,
669 DecodeIdx,
670 RenameIdx,
671 IEWIdx,
672 CommitIdx,
673 NumStages };
674
675 /** Typedefs from the Impl to get the structs that each of the
676 * time buffers should use.
677 */
678 typedef typename CPUPolicy::TimeStruct TimeStruct;
679
680 typedef typename CPUPolicy::FetchStruct FetchStruct;
681
682 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
683
684 typedef typename CPUPolicy::RenameStruct RenameStruct;
685
686 typedef typename CPUPolicy::IEWStruct IEWStruct;
687
688 /** The main time buffer to do backwards communication. */
689 TimeBuffer<TimeStruct> timeBuffer;
690
691 /** The fetch stage's instruction queue. */
692 TimeBuffer<FetchStruct> fetchQueue;
693
694 /** The decode stage's instruction queue. */
695 TimeBuffer<DecodeStruct> decodeQueue;
696
697 /** The rename stage's instruction queue. */
698 TimeBuffer<RenameStruct> renameQueue;
699
700 /** The IEW stage's instruction queue. */
701 TimeBuffer<IEWStruct> iewQueue;
702
703 private:
704 /** The activity recorder; used to tell if the CPU has any
705 * activity remaining or if it can go to idle and deschedule
706 * itself.
707 */
708 ActivityRecorder activityRec;
709
710 public:
711 /** Records that there was time buffer activity this cycle. */
712 void activityThisCycle() { activityRec.activity(); }
713
714 /** Changes a stage's status to active within the activity recorder. */
715 void activateStage(const StageIdx idx)
716 { activityRec.activateStage(idx); }
717
718 /** Changes a stage's status to inactive within the activity recorder. */
719 void deactivateStage(const StageIdx idx)
720 { activityRec.deactivateStage(idx); }
721
722 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
723 void wakeCPU();
724
725 virtual void wakeup(ThreadID tid) override;
726
727 /** Gets a free thread id. Use if thread ids change across system. */
728 ThreadID getFreeTid();
729
730 public:
731 /** Returns a pointer to a thread context. */
732 ThreadContext *
733 tcBase(ThreadID tid)
734 {
735 return thread[tid]->getTC();
736 }
737
738 /** The global sequence number counter. */
739 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
740
741 /** Pointer to the checker, which can dynamically verify
742 * instruction results at run time. This can be set to NULL if it
743 * is not being used.
744 */
745 Checker<Impl> *checker;
746
747 /** Pointer to the system. */
748 System *system;
749
750 /** Pointers to all of the threads in the CPU. */
751 std::vector<Thread *> thread;
752
753 /** Threads Scheduled to Enter CPU */
754 std::list<int> cpuWaitList;
755
756 /** The cycle that the CPU was last running, used for statistics. */
757 Cycles lastRunningCycle;
758
759 /** The cycle that the CPU was last activated by a new thread*/
760 Tick lastActivatedCycle;
761
762 /** Mapping for system thread id to cpu id */
763 std::map<ThreadID, unsigned> threadMap;
764
765 /** Available thread ids in the cpu*/
766 std::vector<ThreadID> tids;
767
768 /** CPU pushRequest function, forwards request to LSQ. */
769 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
770 unsigned int size, Addr addr, Request::Flags flags,
771 uint64_t *res)
772 {
773 return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
774 flags, res);
775 }
776
777 /** CPU read function, forwards read to LSQ. */
778 Fault read(LSQRequest* req, int load_idx)
779 {
780 return this->iew.ldstQueue.read(req, load_idx);
781 }
782
783 /** CPU write function, forwards write to LSQ. */
784 Fault write(LSQRequest* req, uint8_t *data, int store_idx)
785 {
786 return this->iew.ldstQueue.write(req, data, store_idx);
787 }
788
789 /** Used by the fetch unit to get a hold of the instruction port. */
790 MasterPort &getInstPort() override { return icachePort; }
791
792 /** Get the dcache port (used to find block size for translations). */
793 MasterPort &getDataPort() override { return dcachePort; }
794
795 /** Stat for total number of times the CPU is descheduled. */
796 Stats::Scalar timesIdled;
797 /** Stat for total number of cycles the CPU spends descheduled. */
798 Stats::Scalar idleCycles;
799 /** Stat for total number of cycles the CPU spends descheduled due to a
800 * quiesce operation or waiting for an interrupt. */
801 Stats::Scalar quiesceCycles;
802 /** Stat for the number of committed instructions per thread. */
803 Stats::Vector committedInsts;
804 /** Stat for the number of committed ops (including micro ops) per thread. */
805 Stats::Vector committedOps;
806 /** Stat for the CPI per thread. */
807 Stats::Formula cpi;
808 /** Stat for the total CPI. */
809 Stats::Formula totalCpi;
810 /** Stat for the IPC per thread. */
811 Stats::Formula ipc;
812 /** Stat for the total IPC. */
813 Stats::Formula totalIpc;
814
815 //number of integer register file accesses
816 Stats::Scalar intRegfileReads;
817 Stats::Scalar intRegfileWrites;
818 //number of float register file accesses
819 Stats::Scalar fpRegfileReads;
820 Stats::Scalar fpRegfileWrites;
821 //number of vector register file accesses
822 mutable Stats::Scalar vecRegfileReads;
823 Stats::Scalar vecRegfileWrites;
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| 824 //number of predicate register file accesses
825 mutable Stats::Scalar vecPredRegfileReads;
826 Stats::Scalar vecPredRegfileWrites;
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808 //number of CC register file accesses
809 Stats::Scalar ccRegfileReads;
810 Stats::Scalar ccRegfileWrites;
811 //number of misc
812 Stats::Scalar miscRegfileReads;
813 Stats::Scalar miscRegfileWrites;
814};
815
816#endif // __CPU_O3_CPU_HH__
| 827 //number of CC register file accesses
828 Stats::Scalar ccRegfileReads;
829 Stats::Scalar ccRegfileWrites;
830 //number of misc
831 Stats::Scalar miscRegfileReads;
832 Stats::Scalar miscRegfileWrites;
833};
834
835#endif // __CPU_O3_CPU_HH__
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