cpu.hh (10407:a9023811bf9e) cpu.hh (10408:a59c189de383)
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/types.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"
64#include "cpu/base.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/timebuf.hh"
67//#include "cpu/o3/thread_context.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/process.hh"
70
71template <class>
72class Checker;
73class ThreadContext;
74template <class>
75class O3ThreadContext;
76
77class Checkpoint;
78class MemObject;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:
114 enum Status {
115 Running,
116 Idle,
117 Halted,
118 Blocked,
119 SwitchedOut
120 };
121
122 TheISA::TLB * itb;
123 TheISA::TLB * dtb;
124
125 /** Overall CPU status. */
126 Status _status;
127
128 private:
129
130 /**
131 * IcachePort class for instruction fetch.
132 */
133 class IcachePort : public MasterPort
134 {
135 protected:
136 /** Pointer to fetch. */
137 DefaultFetch<Impl> *fetch;
138
139 public:
140 /** Default constructor. */
141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
143 { }
144
145 protected:
146
147 /** Timing version of receive. Handles setting fetch to the
148 * proper status to start fetching. */
149 virtual bool recvTimingResp(PacketPtr pkt);
150 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
151
152 /** Handles doing a retry of a failed fetch. */
153 virtual void recvRetry();
154 };
155
156 /**
157 * DcachePort class for the load/store queue.
158 */
159 class DcachePort : public MasterPort
160 {
161 protected:
162
163 /** Pointer to LSQ. */
164 LSQ<Impl> *lsq;
165
166 public:
167 /** Default constructor. */
168 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
169 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
170 { }
171
172 protected:
173
174 /** Timing version of receive. Handles writing back and
175 * completing the load or store that has returned from
176 * memory. */
177 virtual bool recvTimingResp(PacketPtr pkt);
178 virtual void recvTimingSnoopReq(PacketPtr pkt);
179
180 virtual void recvFunctionalSnoop(PacketPtr pkt)
181 {
182 // @todo: Is there a need for potential invalidation here?
183 }
184
185 /** Handles doing a retry of the previous send. */
186 virtual void recvRetry();
187
188 /**
189 * As this CPU requires snooping to maintain the load store queue
190 * change the behaviour from the base CPU port.
191 *
192 * @return true since we have to snoop
193 */
194 virtual bool isSnooping() const { return true; }
195 };
196
197 class TickEvent : public Event
198 {
199 private:
200 /** Pointer to the CPU. */
201 FullO3CPU<Impl> *cpu;
202
203 public:
204 /** Constructs a tick event. */
205 TickEvent(FullO3CPU<Impl> *c);
206
207 /** Processes a tick event, calling tick() on the CPU. */
208 void process();
209 /** Returns the description of the tick event. */
210 const char *description() const;
211 };
212
213 /** The tick event used for scheduling CPU ticks. */
214 TickEvent tickEvent;
215
216 /** Schedule tick event, regardless of its current state. */
217 void scheduleTickEvent(Cycles delay)
218 {
219 if (tickEvent.squashed())
220 reschedule(tickEvent, clockEdge(delay));
221 else if (!tickEvent.scheduled())
222 schedule(tickEvent, clockEdge(delay));
223 }
224
225 /** Unschedule tick event, regardless of its current state. */
226 void unscheduleTickEvent()
227 {
228 if (tickEvent.scheduled())
229 tickEvent.squash();
230 }
231
232 /**
233 * Check if the pipeline has drained and signal the DrainManager.
234 *
235 * This method checks if a drain has been requested and if the CPU
236 * has drained successfully (i.e., there are no instructions in
237 * the pipeline). If the CPU has drained, it deschedules the tick
238 * event and signals the drain manager.
239 *
240 * @return False if a drain hasn't been requested or the CPU
241 * hasn't drained, true otherwise.
242 */
243 bool tryDrain();
244
245 /**
246 * Perform sanity checks after a drain.
247 *
248 * This method is called from drain() when it has determined that
249 * the CPU is fully drained when gem5 is compiled with the NDEBUG
250 * macro undefined. The intention of this method is to do more
251 * extensive tests than the isDrained() method to weed out any
252 * draining bugs.
253 */
254 void drainSanityCheck() const;
255
256 /** Check if a system is in a drained state. */
257 bool isDrained() const;
258
259 public:
260 /** Constructs a CPU with the given parameters. */
261 FullO3CPU(DerivO3CPUParams *params);
262 /** Destructor. */
263 ~FullO3CPU();
264
265 /** Registers statistics. */
266 void regStats();
267
268 ProbePointArg<PacketPtr> *ppInstAccessComplete;
269 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
270
271 /** Register probe points. */
272 void regProbePoints();
273
274 void demapPage(Addr vaddr, uint64_t asn)
275 {
276 this->itb->demapPage(vaddr, asn);
277 this->dtb->demapPage(vaddr, asn);
278 }
279
280 void demapInstPage(Addr vaddr, uint64_t asn)
281 {
282 this->itb->demapPage(vaddr, asn);
283 }
284
285 void demapDataPage(Addr vaddr, uint64_t asn)
286 {
287 this->dtb->demapPage(vaddr, asn);
288 }
289
290 /** Ticks CPU, calling tick() on each stage, and checking the overall
291 * activity to see if the CPU should deschedule itself.
292 */
293 void tick();
294
295 /** Initialize the CPU */
296 void init();
297
298 void startup();
299
300 /** Returns the Number of Active Threads in the CPU */
301 int numActiveThreads()
302 { return activeThreads.size(); }
303
304 /** Add Thread to Active Threads List */
305 void activateThread(ThreadID tid);
306
307 /** Remove Thread from Active Threads List */
308 void deactivateThread(ThreadID tid);
309
310 /** Setup CPU to insert a thread's context */
311 void insertThread(ThreadID tid);
312
313 /** Remove all of a thread's context from CPU */
314 void removeThread(ThreadID tid);
315
316 /** Count the Total Instructions Committed in the CPU. */
317 virtual Counter totalInsts() const;
318
319 /** Count the Total Ops (including micro ops) committed in the CPU. */
320 virtual Counter totalOps() const;
321
322 /** Add Thread to Active Threads List. */
323 void activateContext(ThreadID tid);
324
325 /** Remove Thread from Active Threads List */
326 void suspendContext(ThreadID tid);
327
328 /** Remove Thread from Active Threads List &&
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/types.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"
64#include "cpu/base.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/timebuf.hh"
67//#include "cpu/o3/thread_context.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/process.hh"
70
71template <class>
72class Checker;
73class ThreadContext;
74template <class>
75class O3ThreadContext;
76
77class Checkpoint;
78class MemObject;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:
114 enum Status {
115 Running,
116 Idle,
117 Halted,
118 Blocked,
119 SwitchedOut
120 };
121
122 TheISA::TLB * itb;
123 TheISA::TLB * dtb;
124
125 /** Overall CPU status. */
126 Status _status;
127
128 private:
129
130 /**
131 * IcachePort class for instruction fetch.
132 */
133 class IcachePort : public MasterPort
134 {
135 protected:
136 /** Pointer to fetch. */
137 DefaultFetch<Impl> *fetch;
138
139 public:
140 /** Default constructor. */
141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
143 { }
144
145 protected:
146
147 /** Timing version of receive. Handles setting fetch to the
148 * proper status to start fetching. */
149 virtual bool recvTimingResp(PacketPtr pkt);
150 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
151
152 /** Handles doing a retry of a failed fetch. */
153 virtual void recvRetry();
154 };
155
156 /**
157 * DcachePort class for the load/store queue.
158 */
159 class DcachePort : public MasterPort
160 {
161 protected:
162
163 /** Pointer to LSQ. */
164 LSQ<Impl> *lsq;
165
166 public:
167 /** Default constructor. */
168 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
169 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
170 { }
171
172 protected:
173
174 /** Timing version of receive. Handles writing back and
175 * completing the load or store that has returned from
176 * memory. */
177 virtual bool recvTimingResp(PacketPtr pkt);
178 virtual void recvTimingSnoopReq(PacketPtr pkt);
179
180 virtual void recvFunctionalSnoop(PacketPtr pkt)
181 {
182 // @todo: Is there a need for potential invalidation here?
183 }
184
185 /** Handles doing a retry of the previous send. */
186 virtual void recvRetry();
187
188 /**
189 * As this CPU requires snooping to maintain the load store queue
190 * change the behaviour from the base CPU port.
191 *
192 * @return true since we have to snoop
193 */
194 virtual bool isSnooping() const { return true; }
195 };
196
197 class TickEvent : public Event
198 {
199 private:
200 /** Pointer to the CPU. */
201 FullO3CPU<Impl> *cpu;
202
203 public:
204 /** Constructs a tick event. */
205 TickEvent(FullO3CPU<Impl> *c);
206
207 /** Processes a tick event, calling tick() on the CPU. */
208 void process();
209 /** Returns the description of the tick event. */
210 const char *description() const;
211 };
212
213 /** The tick event used for scheduling CPU ticks. */
214 TickEvent tickEvent;
215
216 /** Schedule tick event, regardless of its current state. */
217 void scheduleTickEvent(Cycles delay)
218 {
219 if (tickEvent.squashed())
220 reschedule(tickEvent, clockEdge(delay));
221 else if (!tickEvent.scheduled())
222 schedule(tickEvent, clockEdge(delay));
223 }
224
225 /** Unschedule tick event, regardless of its current state. */
226 void unscheduleTickEvent()
227 {
228 if (tickEvent.scheduled())
229 tickEvent.squash();
230 }
231
232 /**
233 * Check if the pipeline has drained and signal the DrainManager.
234 *
235 * This method checks if a drain has been requested and if the CPU
236 * has drained successfully (i.e., there are no instructions in
237 * the pipeline). If the CPU has drained, it deschedules the tick
238 * event and signals the drain manager.
239 *
240 * @return False if a drain hasn't been requested or the CPU
241 * hasn't drained, true otherwise.
242 */
243 bool tryDrain();
244
245 /**
246 * Perform sanity checks after a drain.
247 *
248 * This method is called from drain() when it has determined that
249 * the CPU is fully drained when gem5 is compiled with the NDEBUG
250 * macro undefined. The intention of this method is to do more
251 * extensive tests than the isDrained() method to weed out any
252 * draining bugs.
253 */
254 void drainSanityCheck() const;
255
256 /** Check if a system is in a drained state. */
257 bool isDrained() const;
258
259 public:
260 /** Constructs a CPU with the given parameters. */
261 FullO3CPU(DerivO3CPUParams *params);
262 /** Destructor. */
263 ~FullO3CPU();
264
265 /** Registers statistics. */
266 void regStats();
267
268 ProbePointArg<PacketPtr> *ppInstAccessComplete;
269 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
270
271 /** Register probe points. */
272 void regProbePoints();
273
274 void demapPage(Addr vaddr, uint64_t asn)
275 {
276 this->itb->demapPage(vaddr, asn);
277 this->dtb->demapPage(vaddr, asn);
278 }
279
280 void demapInstPage(Addr vaddr, uint64_t asn)
281 {
282 this->itb->demapPage(vaddr, asn);
283 }
284
285 void demapDataPage(Addr vaddr, uint64_t asn)
286 {
287 this->dtb->demapPage(vaddr, asn);
288 }
289
290 /** Ticks CPU, calling tick() on each stage, and checking the overall
291 * activity to see if the CPU should deschedule itself.
292 */
293 void tick();
294
295 /** Initialize the CPU */
296 void init();
297
298 void startup();
299
300 /** Returns the Number of Active Threads in the CPU */
301 int numActiveThreads()
302 { return activeThreads.size(); }
303
304 /** Add Thread to Active Threads List */
305 void activateThread(ThreadID tid);
306
307 /** Remove Thread from Active Threads List */
308 void deactivateThread(ThreadID tid);
309
310 /** Setup CPU to insert a thread's context */
311 void insertThread(ThreadID tid);
312
313 /** Remove all of a thread's context from CPU */
314 void removeThread(ThreadID tid);
315
316 /** Count the Total Instructions Committed in the CPU. */
317 virtual Counter totalInsts() const;
318
319 /** Count the Total Ops (including micro ops) committed in the CPU. */
320 virtual Counter totalOps() const;
321
322 /** Add Thread to Active Threads List. */
323 void activateContext(ThreadID tid);
324
325 /** Remove Thread from Active Threads List */
326 void suspendContext(ThreadID tid);
327
328 /** Remove Thread from Active Threads List &&
329 * Possibly Remove Thread Context from CPU.
330 */
331 void deallocateContext(ThreadID tid, bool remove);
332
333 /** Remove Thread from Active Threads List &&
334 * Remove Thread Context from CPU.
335 */
336 void haltContext(ThreadID tid);
337
338 /** Update The Order In Which We Process Threads. */
339 void updateThreadPriority();
340
341 /** Is the CPU draining? */
342 bool isDraining() const { return getDrainState() == Drainable::Draining; }
343
344 void serializeThread(std::ostream &os, ThreadID tid);
345
346 void unserializeThread(Checkpoint *cp, const std::string &section,
347 ThreadID tid);
348
349 public:
350 /** Executes a syscall.
351 * @todo: Determine if this needs to be virtual.
352 */
353 void syscall(int64_t callnum, ThreadID tid);
354
355 /** Starts draining the CPU's pipeline of all instructions in
356 * order to stop all memory accesses. */
357 unsigned int drain(DrainManager *drain_manager);
358
359 /** Resumes execution after a drain. */
360 void drainResume();
361
362 /**
363 * Commit has reached a safe point to drain a thread.
364 *
365 * Commit calls this method to inform the pipeline that it has
366 * reached a point where it is not executed microcode and is about
367 * to squash uncommitted instructions to fully drain the pipeline.
368 */
369 void commitDrained(ThreadID tid);
370
371 /** Switches out this CPU. */
372 virtual void switchOut();
373
374 /** Takes over from another CPU. */
375 virtual void takeOverFrom(BaseCPU *oldCPU);
376
377 void verifyMemoryMode() const;
378
379 /** Get the current instruction sequence number, and increment it. */
380 InstSeqNum getAndIncrementInstSeq()
381 { return globalSeqNum++; }
382
383 /** Traps to handle given fault. */
384 void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
385
386 /** HW return from error interrupt. */
387 Fault hwrei(ThreadID tid);
388
389 bool simPalCheck(int palFunc, ThreadID tid);
390
391 /** Returns the Fault for any valid interrupt. */
392 Fault getInterrupts();
393
394 /** Processes any an interrupt fault. */
395 void processInterrupts(const Fault &interrupt);
396
397 /** Halts the CPU. */
398 void halt() { panic("Halt not implemented!\n"); }
399
400 /** Check if this address is a valid instruction address. */
401 bool validInstAddr(Addr addr) { return true; }
402
403 /** Check if this address is a valid data address. */
404 bool validDataAddr(Addr addr) { return true; }
405
406 /** Register accessors. Index refers to the physical register index. */
407
408 /** Reads a miscellaneous register. */
409 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
410
411 /** Reads a misc. register, including any side effects the read
412 * might have as defined by the architecture.
413 */
414 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
415
416 /** Sets a miscellaneous register. */
417 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
418 ThreadID tid);
419
420 /** Sets a misc. register, including any side effects the write
421 * might have as defined by the architecture.
422 */
423 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
424 ThreadID tid);
425
426 uint64_t readIntReg(int reg_idx);
427
428 TheISA::FloatReg readFloatReg(int reg_idx);
429
430 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
431
432 TheISA::CCReg readCCReg(int reg_idx);
433
434 void setIntReg(int reg_idx, uint64_t val);
435
436 void setFloatReg(int reg_idx, TheISA::FloatReg val);
437
438 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
439
440 void setCCReg(int reg_idx, TheISA::CCReg val);
441
442 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
443
444 float readArchFloatReg(int reg_idx, ThreadID tid);
445
446 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
447
448 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
449
450 /** Architectural register accessors. Looks up in the commit
451 * rename table to obtain the true physical index of the
452 * architected register first, then accesses that physical
453 * register.
454 */
455 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
456
457 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
458
459 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
460
461 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
462
463 /** Sets the commit PC state of a specific thread. */
464 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
465
466 /** Reads the commit PC state of a specific thread. */
467 TheISA::PCState pcState(ThreadID tid);
468
469 /** Reads the commit PC of a specific thread. */
470 Addr instAddr(ThreadID tid);
471
472 /** Reads the commit micro PC of a specific thread. */
473 MicroPC microPC(ThreadID tid);
474
475 /** Reads the next PC of a specific thread. */
476 Addr nextInstAddr(ThreadID tid);
477
478 /** Initiates a squash of all in-flight instructions for a given
479 * thread. The source of the squash is an external update of
480 * state through the TC.
481 */
482 void squashFromTC(ThreadID tid);
483
484 /** Function to add instruction onto the head of the list of the
485 * instructions. Used when new instructions are fetched.
486 */
487 ListIt addInst(DynInstPtr &inst);
488
489 /** Function to tell the CPU that an instruction has completed. */
490 void instDone(ThreadID tid, DynInstPtr &inst);
491
492 /** Remove an instruction from the front end of the list. There's
493 * no restriction on location of the instruction.
494 */
495 void removeFrontInst(DynInstPtr &inst);
496
497 /** Remove all instructions that are not currently in the ROB.
498 * There's also an option to not squash delay slot instructions.*/
499 void removeInstsNotInROB(ThreadID tid);
500
501 /** Remove all instructions younger than the given sequence number. */
502 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
503
504 /** Removes the instruction pointed to by the iterator. */
505 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
506
507 /** Cleans up all instructions on the remove list. */
508 void cleanUpRemovedInsts();
509
510 /** Debug function to print all instructions on the list. */
511 void dumpInsts();
512
513 public:
514#ifndef NDEBUG
515 /** Count of total number of dynamic instructions in flight. */
516 int instcount;
517#endif
518
519 /** List of all the instructions in flight. */
520 std::list<DynInstPtr> instList;
521
522 /** List of all the instructions that will be removed at the end of this
523 * cycle.
524 */
525 std::queue<ListIt> removeList;
526
527#ifdef DEBUG
528 /** Debug structure to keep track of the sequence numbers still in
529 * flight.
530 */
531 std::set<InstSeqNum> snList;
532#endif
533
534 /** Records if instructions need to be removed this cycle due to
535 * being retired or squashed.
536 */
537 bool removeInstsThisCycle;
538
539 protected:
540 /** The fetch stage. */
541 typename CPUPolicy::Fetch fetch;
542
543 /** The decode stage. */
544 typename CPUPolicy::Decode decode;
545
546 /** The dispatch stage. */
547 typename CPUPolicy::Rename rename;
548
549 /** The issue/execute/writeback stages. */
550 typename CPUPolicy::IEW iew;
551
552 /** The commit stage. */
553 typename CPUPolicy::Commit commit;
554
555 /** The register file. */
556 PhysRegFile regFile;
557
558 /** The free list. */
559 typename CPUPolicy::FreeList freeList;
560
561 /** The rename map. */
562 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
563
564 /** The commit rename map. */
565 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
566
567 /** The re-order buffer. */
568 typename CPUPolicy::ROB rob;
569
570 /** Active Threads List */
571 std::list<ThreadID> activeThreads;
572
573 /** Integer Register Scoreboard */
574 Scoreboard scoreboard;
575
576 std::vector<TheISA::ISA *> isa;
577
578 /** Instruction port. Note that it has to appear after the fetch stage. */
579 IcachePort icachePort;
580
581 /** Data port. Note that it has to appear after the iew stages */
582 DcachePort dcachePort;
583
584 public:
585 /** Enum to give each stage a specific index, so when calling
586 * activateStage() or deactivateStage(), they can specify which stage
587 * is being activated/deactivated.
588 */
589 enum StageIdx {
590 FetchIdx,
591 DecodeIdx,
592 RenameIdx,
593 IEWIdx,
594 CommitIdx,
595 NumStages };
596
597 /** Typedefs from the Impl to get the structs that each of the
598 * time buffers should use.
599 */
600 typedef typename CPUPolicy::TimeStruct TimeStruct;
601
602 typedef typename CPUPolicy::FetchStruct FetchStruct;
603
604 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
605
606 typedef typename CPUPolicy::RenameStruct RenameStruct;
607
608 typedef typename CPUPolicy::IEWStruct IEWStruct;
609
610 /** The main time buffer to do backwards communication. */
611 TimeBuffer<TimeStruct> timeBuffer;
612
613 /** The fetch stage's instruction queue. */
614 TimeBuffer<FetchStruct> fetchQueue;
615
616 /** The decode stage's instruction queue. */
617 TimeBuffer<DecodeStruct> decodeQueue;
618
619 /** The rename stage's instruction queue. */
620 TimeBuffer<RenameStruct> renameQueue;
621
622 /** The IEW stage's instruction queue. */
623 TimeBuffer<IEWStruct> iewQueue;
624
625 private:
626 /** The activity recorder; used to tell if the CPU has any
627 * activity remaining or if it can go to idle and deschedule
628 * itself.
629 */
630 ActivityRecorder activityRec;
631
632 public:
633 /** Records that there was time buffer activity this cycle. */
634 void activityThisCycle() { activityRec.activity(); }
635
636 /** Changes a stage's status to active within the activity recorder. */
637 void activateStage(const StageIdx idx)
638 { activityRec.activateStage(idx); }
639
640 /** Changes a stage's status to inactive within the activity recorder. */
641 void deactivateStage(const StageIdx idx)
642 { activityRec.deactivateStage(idx); }
643
644 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
645 void wakeCPU();
646
647 virtual void wakeup();
648
649 /** Gets a free thread id. Use if thread ids change across system. */
650 ThreadID getFreeTid();
651
652 public:
653 /** Returns a pointer to a thread context. */
654 ThreadContext *
655 tcBase(ThreadID tid)
656 {
657 return thread[tid]->getTC();
658 }
659
660 /** The global sequence number counter. */
661 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
662
663 /** Pointer to the checker, which can dynamically verify
664 * instruction results at run time. This can be set to NULL if it
665 * is not being used.
666 */
667 Checker<Impl> *checker;
668
669 /** Pointer to the system. */
670 System *system;
671
672 /** DrainManager to notify when draining has completed. */
673 DrainManager *drainManager;
674
675 /** Pointers to all of the threads in the CPU. */
676 std::vector<Thread *> thread;
677
678 /** Threads Scheduled to Enter CPU */
679 std::list<int> cpuWaitList;
680
681 /** The cycle that the CPU was last running, used for statistics. */
682 Cycles lastRunningCycle;
683
684 /** The cycle that the CPU was last activated by a new thread*/
685 Tick lastActivatedCycle;
686
687 /** Mapping for system thread id to cpu id */
688 std::map<ThreadID, unsigned> threadMap;
689
690 /** Available thread ids in the cpu*/
691 std::vector<ThreadID> tids;
692
693 /** CPU read function, forwards read to LSQ. */
694 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
695 uint8_t *data, int load_idx)
696 {
697 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
698 data, load_idx);
699 }
700
701 /** CPU write function, forwards write to LSQ. */
702 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
703 uint8_t *data, int store_idx)
704 {
705 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
706 data, store_idx);
707 }
708
709 /** Used by the fetch unit to get a hold of the instruction port. */
710 virtual MasterPort &getInstPort() { return icachePort; }
711
712 /** Get the dcache port (used to find block size for translations). */
713 virtual MasterPort &getDataPort() { return dcachePort; }
714
715 /** Stat for total number of times the CPU is descheduled. */
716 Stats::Scalar timesIdled;
717 /** Stat for total number of cycles the CPU spends descheduled. */
718 Stats::Scalar idleCycles;
719 /** Stat for total number of cycles the CPU spends descheduled due to a
720 * quiesce operation or waiting for an interrupt. */
721 Stats::Scalar quiesceCycles;
722 /** Stat for the number of committed instructions per thread. */
723 Stats::Vector committedInsts;
724 /** Stat for the number of committed ops (including micro ops) per thread. */
725 Stats::Vector committedOps;
726 /** Stat for the CPI per thread. */
727 Stats::Formula cpi;
728 /** Stat for the total CPI. */
729 Stats::Formula totalCpi;
730 /** Stat for the IPC per thread. */
731 Stats::Formula ipc;
732 /** Stat for the total IPC. */
733 Stats::Formula totalIpc;
734
735 //number of integer register file accesses
736 Stats::Scalar intRegfileReads;
737 Stats::Scalar intRegfileWrites;
738 //number of float register file accesses
739 Stats::Scalar fpRegfileReads;
740 Stats::Scalar fpRegfileWrites;
741 //number of CC register file accesses
742 Stats::Scalar ccRegfileReads;
743 Stats::Scalar ccRegfileWrites;
744 //number of misc
745 Stats::Scalar miscRegfileReads;
746 Stats::Scalar miscRegfileWrites;
747};
748
749#endif // __CPU_O3_CPU_HH__
329 * Remove Thread Context from CPU.
330 */
331 void haltContext(ThreadID tid);
332
333 /** Update The Order In Which We Process Threads. */
334 void updateThreadPriority();
335
336 /** Is the CPU draining? */
337 bool isDraining() const { return getDrainState() == Drainable::Draining; }
338
339 void serializeThread(std::ostream &os, ThreadID tid);
340
341 void unserializeThread(Checkpoint *cp, const std::string &section,
342 ThreadID tid);
343
344 public:
345 /** Executes a syscall.
346 * @todo: Determine if this needs to be virtual.
347 */
348 void syscall(int64_t callnum, ThreadID tid);
349
350 /** Starts draining the CPU's pipeline of all instructions in
351 * order to stop all memory accesses. */
352 unsigned int drain(DrainManager *drain_manager);
353
354 /** Resumes execution after a drain. */
355 void drainResume();
356
357 /**
358 * Commit has reached a safe point to drain a thread.
359 *
360 * Commit calls this method to inform the pipeline that it has
361 * reached a point where it is not executed microcode and is about
362 * to squash uncommitted instructions to fully drain the pipeline.
363 */
364 void commitDrained(ThreadID tid);
365
366 /** Switches out this CPU. */
367 virtual void switchOut();
368
369 /** Takes over from another CPU. */
370 virtual void takeOverFrom(BaseCPU *oldCPU);
371
372 void verifyMemoryMode() const;
373
374 /** Get the current instruction sequence number, and increment it. */
375 InstSeqNum getAndIncrementInstSeq()
376 { return globalSeqNum++; }
377
378 /** Traps to handle given fault. */
379 void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
380
381 /** HW return from error interrupt. */
382 Fault hwrei(ThreadID tid);
383
384 bool simPalCheck(int palFunc, ThreadID tid);
385
386 /** Returns the Fault for any valid interrupt. */
387 Fault getInterrupts();
388
389 /** Processes any an interrupt fault. */
390 void processInterrupts(const Fault &interrupt);
391
392 /** Halts the CPU. */
393 void halt() { panic("Halt not implemented!\n"); }
394
395 /** Check if this address is a valid instruction address. */
396 bool validInstAddr(Addr addr) { return true; }
397
398 /** Check if this address is a valid data address. */
399 bool validDataAddr(Addr addr) { return true; }
400
401 /** Register accessors. Index refers to the physical register index. */
402
403 /** Reads a miscellaneous register. */
404 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
405
406 /** Reads a misc. register, including any side effects the read
407 * might have as defined by the architecture.
408 */
409 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
410
411 /** Sets a miscellaneous register. */
412 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
413 ThreadID tid);
414
415 /** Sets a misc. register, including any side effects the write
416 * might have as defined by the architecture.
417 */
418 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
419 ThreadID tid);
420
421 uint64_t readIntReg(int reg_idx);
422
423 TheISA::FloatReg readFloatReg(int reg_idx);
424
425 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
426
427 TheISA::CCReg readCCReg(int reg_idx);
428
429 void setIntReg(int reg_idx, uint64_t val);
430
431 void setFloatReg(int reg_idx, TheISA::FloatReg val);
432
433 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
434
435 void setCCReg(int reg_idx, TheISA::CCReg val);
436
437 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
438
439 float readArchFloatReg(int reg_idx, ThreadID tid);
440
441 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
442
443 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
444
445 /** Architectural register accessors. Looks up in the commit
446 * rename table to obtain the true physical index of the
447 * architected register first, then accesses that physical
448 * register.
449 */
450 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
451
452 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
453
454 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
455
456 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
457
458 /** Sets the commit PC state of a specific thread. */
459 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
460
461 /** Reads the commit PC state of a specific thread. */
462 TheISA::PCState pcState(ThreadID tid);
463
464 /** Reads the commit PC of a specific thread. */
465 Addr instAddr(ThreadID tid);
466
467 /** Reads the commit micro PC of a specific thread. */
468 MicroPC microPC(ThreadID tid);
469
470 /** Reads the next PC of a specific thread. */
471 Addr nextInstAddr(ThreadID tid);
472
473 /** Initiates a squash of all in-flight instructions for a given
474 * thread. The source of the squash is an external update of
475 * state through the TC.
476 */
477 void squashFromTC(ThreadID tid);
478
479 /** Function to add instruction onto the head of the list of the
480 * instructions. Used when new instructions are fetched.
481 */
482 ListIt addInst(DynInstPtr &inst);
483
484 /** Function to tell the CPU that an instruction has completed. */
485 void instDone(ThreadID tid, DynInstPtr &inst);
486
487 /** Remove an instruction from the front end of the list. There's
488 * no restriction on location of the instruction.
489 */
490 void removeFrontInst(DynInstPtr &inst);
491
492 /** Remove all instructions that are not currently in the ROB.
493 * There's also an option to not squash delay slot instructions.*/
494 void removeInstsNotInROB(ThreadID tid);
495
496 /** Remove all instructions younger than the given sequence number. */
497 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
498
499 /** Removes the instruction pointed to by the iterator. */
500 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
501
502 /** Cleans up all instructions on the remove list. */
503 void cleanUpRemovedInsts();
504
505 /** Debug function to print all instructions on the list. */
506 void dumpInsts();
507
508 public:
509#ifndef NDEBUG
510 /** Count of total number of dynamic instructions in flight. */
511 int instcount;
512#endif
513
514 /** List of all the instructions in flight. */
515 std::list<DynInstPtr> instList;
516
517 /** List of all the instructions that will be removed at the end of this
518 * cycle.
519 */
520 std::queue<ListIt> removeList;
521
522#ifdef DEBUG
523 /** Debug structure to keep track of the sequence numbers still in
524 * flight.
525 */
526 std::set<InstSeqNum> snList;
527#endif
528
529 /** Records if instructions need to be removed this cycle due to
530 * being retired or squashed.
531 */
532 bool removeInstsThisCycle;
533
534 protected:
535 /** The fetch stage. */
536 typename CPUPolicy::Fetch fetch;
537
538 /** The decode stage. */
539 typename CPUPolicy::Decode decode;
540
541 /** The dispatch stage. */
542 typename CPUPolicy::Rename rename;
543
544 /** The issue/execute/writeback stages. */
545 typename CPUPolicy::IEW iew;
546
547 /** The commit stage. */
548 typename CPUPolicy::Commit commit;
549
550 /** The register file. */
551 PhysRegFile regFile;
552
553 /** The free list. */
554 typename CPUPolicy::FreeList freeList;
555
556 /** The rename map. */
557 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
558
559 /** The commit rename map. */
560 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
561
562 /** The re-order buffer. */
563 typename CPUPolicy::ROB rob;
564
565 /** Active Threads List */
566 std::list<ThreadID> activeThreads;
567
568 /** Integer Register Scoreboard */
569 Scoreboard scoreboard;
570
571 std::vector<TheISA::ISA *> isa;
572
573 /** Instruction port. Note that it has to appear after the fetch stage. */
574 IcachePort icachePort;
575
576 /** Data port. Note that it has to appear after the iew stages */
577 DcachePort dcachePort;
578
579 public:
580 /** Enum to give each stage a specific index, so when calling
581 * activateStage() or deactivateStage(), they can specify which stage
582 * is being activated/deactivated.
583 */
584 enum StageIdx {
585 FetchIdx,
586 DecodeIdx,
587 RenameIdx,
588 IEWIdx,
589 CommitIdx,
590 NumStages };
591
592 /** Typedefs from the Impl to get the structs that each of the
593 * time buffers should use.
594 */
595 typedef typename CPUPolicy::TimeStruct TimeStruct;
596
597 typedef typename CPUPolicy::FetchStruct FetchStruct;
598
599 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
600
601 typedef typename CPUPolicy::RenameStruct RenameStruct;
602
603 typedef typename CPUPolicy::IEWStruct IEWStruct;
604
605 /** The main time buffer to do backwards communication. */
606 TimeBuffer<TimeStruct> timeBuffer;
607
608 /** The fetch stage's instruction queue. */
609 TimeBuffer<FetchStruct> fetchQueue;
610
611 /** The decode stage's instruction queue. */
612 TimeBuffer<DecodeStruct> decodeQueue;
613
614 /** The rename stage's instruction queue. */
615 TimeBuffer<RenameStruct> renameQueue;
616
617 /** The IEW stage's instruction queue. */
618 TimeBuffer<IEWStruct> iewQueue;
619
620 private:
621 /** The activity recorder; used to tell if the CPU has any
622 * activity remaining or if it can go to idle and deschedule
623 * itself.
624 */
625 ActivityRecorder activityRec;
626
627 public:
628 /** Records that there was time buffer activity this cycle. */
629 void activityThisCycle() { activityRec.activity(); }
630
631 /** Changes a stage's status to active within the activity recorder. */
632 void activateStage(const StageIdx idx)
633 { activityRec.activateStage(idx); }
634
635 /** Changes a stage's status to inactive within the activity recorder. */
636 void deactivateStage(const StageIdx idx)
637 { activityRec.deactivateStage(idx); }
638
639 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
640 void wakeCPU();
641
642 virtual void wakeup();
643
644 /** Gets a free thread id. Use if thread ids change across system. */
645 ThreadID getFreeTid();
646
647 public:
648 /** Returns a pointer to a thread context. */
649 ThreadContext *
650 tcBase(ThreadID tid)
651 {
652 return thread[tid]->getTC();
653 }
654
655 /** The global sequence number counter. */
656 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
657
658 /** Pointer to the checker, which can dynamically verify
659 * instruction results at run time. This can be set to NULL if it
660 * is not being used.
661 */
662 Checker<Impl> *checker;
663
664 /** Pointer to the system. */
665 System *system;
666
667 /** DrainManager to notify when draining has completed. */
668 DrainManager *drainManager;
669
670 /** Pointers to all of the threads in the CPU. */
671 std::vector<Thread *> thread;
672
673 /** Threads Scheduled to Enter CPU */
674 std::list<int> cpuWaitList;
675
676 /** The cycle that the CPU was last running, used for statistics. */
677 Cycles lastRunningCycle;
678
679 /** The cycle that the CPU was last activated by a new thread*/
680 Tick lastActivatedCycle;
681
682 /** Mapping for system thread id to cpu id */
683 std::map<ThreadID, unsigned> threadMap;
684
685 /** Available thread ids in the cpu*/
686 std::vector<ThreadID> tids;
687
688 /** CPU read function, forwards read to LSQ. */
689 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
690 uint8_t *data, int load_idx)
691 {
692 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
693 data, load_idx);
694 }
695
696 /** CPU write function, forwards write to LSQ. */
697 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
698 uint8_t *data, int store_idx)
699 {
700 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
701 data, store_idx);
702 }
703
704 /** Used by the fetch unit to get a hold of the instruction port. */
705 virtual MasterPort &getInstPort() { return icachePort; }
706
707 /** Get the dcache port (used to find block size for translations). */
708 virtual MasterPort &getDataPort() { return dcachePort; }
709
710 /** Stat for total number of times the CPU is descheduled. */
711 Stats::Scalar timesIdled;
712 /** Stat for total number of cycles the CPU spends descheduled. */
713 Stats::Scalar idleCycles;
714 /** Stat for total number of cycles the CPU spends descheduled due to a
715 * quiesce operation or waiting for an interrupt. */
716 Stats::Scalar quiesceCycles;
717 /** Stat for the number of committed instructions per thread. */
718 Stats::Vector committedInsts;
719 /** Stat for the number of committed ops (including micro ops) per thread. */
720 Stats::Vector committedOps;
721 /** Stat for the CPI per thread. */
722 Stats::Formula cpi;
723 /** Stat for the total CPI. */
724 Stats::Formula totalCpi;
725 /** Stat for the IPC per thread. */
726 Stats::Formula ipc;
727 /** Stat for the total IPC. */
728 Stats::Formula totalIpc;
729
730 //number of integer register file accesses
731 Stats::Scalar intRegfileReads;
732 Stats::Scalar intRegfileWrites;
733 //number of float register file accesses
734 Stats::Scalar fpRegfileReads;
735 Stats::Scalar fpRegfileWrites;
736 //number of CC register file accesses
737 Stats::Scalar ccRegfileReads;
738 Stats::Scalar ccRegfileWrites;
739 //number of misc
740 Stats::Scalar miscRegfileReads;
741 Stats::Scalar miscRegfileWrites;
742};
743
744#endif // __CPU_O3_CPU_HH__