1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "config/use_checker.hh"
46#include "cpu/activity.hh"
47#include "cpu/base.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/o3/comm.hh"
50#include "cpu/o3/cpu_policy.hh"
51#include "cpu/o3/scoreboard.hh"
52#include "cpu/o3/thread_state.hh"
53//#include "cpu/o3/thread_context.hh"
54#include "sim/process.hh"
55
56template <class>
57class Checker;
58class ThreadContext;
59template <class>
60class O3ThreadContext;
61
62class Checkpoint;
63class MemObject;
64class Process;
65
66class BaseO3CPU : public BaseCPU
67{
68 //Stuff that's pretty ISA independent will go here.
69 public:
70 typedef BaseCPU::Params Params;
71
72 BaseO3CPU(Params *params);
73
74 void regStats();
75
76 /** Sets this CPU's ID. */
77 void setCpuId(int id) { cpu_id = id; }
78
79 /** Reads this CPU's ID. */
80 int readCpuId() { return cpu_id; }
81
82 protected:
83 int cpu_id;
84};
85
86/**
87 * FullO3CPU class, has each of the stages (fetch through commit)
88 * within it, as well as all of the time buffers between stages. The
89 * tick() function for the CPU is defined here.
90 */
91template <class Impl>
92class FullO3CPU : public BaseO3CPU
93{
94 public:
95 // Typedefs from the Impl here.
96 typedef typename Impl::CPUPol CPUPolicy;
97 typedef typename Impl::Params Params;
98 typedef typename Impl::DynInstPtr DynInstPtr;
99 typedef typename Impl::O3CPU O3CPU;
100
101 typedef O3ThreadState<Impl> Thread;
102
103 typedef typename std::list<DynInstPtr>::iterator ListIt;
104
105 friend class O3ThreadContext<Impl>;
106
107 public:
108 enum Status {
109 Running,
110 Idle,
111 Halted,
112 Blocked,
113 SwitchedOut
114 };
115
116#if FULL_SYSTEM
117 TheISA::ITB * itb;
118 TheISA::DTB * dtb;
119#endif
120
121 /** Overall CPU status. */
122 Status _status;
123
124 /** Per-thread status in CPU, used for SMT. */
125 Status _threadStatus[Impl::MaxThreads];
126
127 private:
128 class TickEvent : public Event
129 {
130 private:
131 /** Pointer to the CPU. */
132 FullO3CPU<Impl> *cpu;
133
134 public:
135 /** Constructs a tick event. */
136 TickEvent(FullO3CPU<Impl> *c);
137
138 /** Processes a tick event, calling tick() on the CPU. */
139 void process();
140 /** Returns the description of the tick event. */
141 const char *description();
142 };
143
144 /** The tick event used for scheduling CPU ticks. */
145 TickEvent tickEvent;
146
147 /** Schedule tick event, regardless of its current state. */
148 void scheduleTickEvent(int delay)
149 {
150 if (tickEvent.squashed())
151 tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
152 else if (!tickEvent.scheduled())
153 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
154 }
155
156 /** Unschedule tick event, regardless of its current state. */
157 void unscheduleTickEvent()
158 {
159 if (tickEvent.scheduled())
160 tickEvent.squash();
161 }
162
163 class ActivateThreadEvent : public Event
164 {
165 private:
166 /** Number of Thread to Activate */
167 int tid;
168
169 /** Pointer to the CPU. */
170 FullO3CPU<Impl> *cpu;
171
172 public:
173 /** Constructs the event. */
174 ActivateThreadEvent();
175
176 /** Initialize Event */
177 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
178
179 /** Processes the event, calling activateThread() on the CPU. */
180 void process();
181
182 /** Returns the description of the event. */
183 const char *description();
184 };
185
186 /** Schedule thread to activate , regardless of its current state. */
187 void scheduleActivateThreadEvent(int tid, int delay)
188 {
189 // Schedule thread to activate, regardless of its current state.
190 if (activateThreadEvent[tid].squashed())
191 activateThreadEvent[tid].
192 reschedule(nextCycle(curTick + cycles(delay)));
193 else if (!activateThreadEvent[tid].scheduled())
194 activateThreadEvent[tid].
195 schedule(nextCycle(curTick + cycles(delay)));
196 }
197
198 /** Unschedule actiavte thread event, regardless of its current state. */
199 void unscheduleActivateThreadEvent(int tid)
200 {
201 if (activateThreadEvent[tid].scheduled())
202 activateThreadEvent[tid].squash();
203 }
204
205 /** The tick event used for scheduling CPU ticks. */
206 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
207
208 class DeallocateContextEvent : public Event
209 {
210 private:
211 /** Number of Thread to deactivate */
212 int tid;
213
214 /** Should the thread be removed from the CPU? */
215 bool remove;
216
217 /** Pointer to the CPU. */
218 FullO3CPU<Impl> *cpu;
219
220 public:
221 /** Constructs the event. */
222 DeallocateContextEvent();
223
224 /** Initialize Event */
225 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
226
227 /** Processes the event, calling activateThread() on the CPU. */
228 void process();
229
230 /** Sets whether the thread should also be removed from the CPU. */
231 void setRemove(bool _remove) { remove = _remove; }
232
233 /** Returns the description of the event. */
234 const char *description();
235 };
236
237 /** Schedule cpu to deallocate thread context.*/
238 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
239 {
240 // Schedule thread to activate, regardless of its current state.
241 if (deallocateContextEvent[tid].squashed())
242 deallocateContextEvent[tid].
243 reschedule(nextCycle(curTick + cycles(delay)));
244 else if (!deallocateContextEvent[tid].scheduled())
245 deallocateContextEvent[tid].
246 schedule(nextCycle(curTick + cycles(delay)));
247 }
248
249 /** Unschedule thread deallocation in CPU */
250 void unscheduleDeallocateContextEvent(int tid)
251 {
252 if (deallocateContextEvent[tid].scheduled())
253 deallocateContextEvent[tid].squash();
254 }
255
256 /** The tick event used for scheduling CPU ticks. */
257 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
258
259 public:
260 /** Constructs a CPU with the given parameters. */
261 FullO3CPU(O3CPU *o3_cpu, Params *params);
262 /** Destructor. */
263 ~FullO3CPU();
264
265 /** Registers statistics. */
266 void fullCPURegStats();
267
268 /** Returns a specific port. */
269 Port *getPort(const std::string &if_name, int idx);
270
271 /** Ticks CPU, calling tick() on each stage, and checking the overall
272 * activity to see if the CPU should deschedule itself.
273 */
274 void tick();
275
276 /** Initialize the CPU */
277 void init();
278
279 /** Returns the Number of Active Threads in the CPU */
280 int numActiveThreads()
281 { return activeThreads.size(); }
282
283 /** Add Thread to Active Threads List */
284 void activateThread(unsigned tid);
285
286 /** Remove Thread from Active Threads List */
287 void deactivateThread(unsigned tid);
288
289 /** Setup CPU to insert a thread's context */
290 void insertThread(unsigned tid);
291
292 /** Remove all of a thread's context from CPU */
293 void removeThread(unsigned tid);
294
295 /** Count the Total Instructions Committed in the CPU. */
296 virtual Counter totalInstructions() const
297 {
298 Counter total(0);
299
300 for (int i=0; i < thread.size(); i++)
301 total += thread[i]->numInst;
302
303 return total;
304 }
305
306 /** Add Thread to Active Threads List. */
307 void activateContext(int tid, int delay);
308
309 /** Remove Thread from Active Threads List */
310 void suspendContext(int tid);
311
312 /** Remove Thread from Active Threads List &&
313 * Possibly Remove Thread Context from CPU.
314 */
315 bool deallocateContext(int tid, bool remove, int delay = 1);
316
317 /** Remove Thread from Active Threads List &&
318 * Remove Thread Context from CPU.
319 */
320 void haltContext(int tid);
321
322 /** Activate a Thread When CPU Resources are Available. */
323 void activateWhenReady(int tid);
324
325 /** Add or Remove a Thread Context in the CPU. */
326 void doContextSwitch();
327
328 /** Update The Order In Which We Process Threads. */
329 void updateThreadPriority();
330
331 /** Serialize state. */
332 virtual void serialize(std::ostream &os);
333
334 /** Unserialize from a checkpoint. */
335 virtual void unserialize(Checkpoint *cp, const std::string §ion);
336
337 public:
338 /** Executes a syscall on this cycle.
339 * ---------------------------------------
340 * Note: this is a virtual function. CPU-Specific
341 * functionality defined in derived classes
342 */
343 virtual void syscall(int tid) { panic("Unimplemented!"); }
344
345 /** Starts draining the CPU's pipeline of all instructions in
346 * order to stop all memory accesses. */
347 virtual unsigned int drain(Event *drain_event);
348
349 /** Resumes execution after a drain. */
350 virtual void resume();
351
352 /** Signals to this CPU that a stage has completed switching out. */
353 void signalDrained();
354
355 /** Switches out this CPU. */
356 virtual void switchOut();
357
358 /** Takes over from another CPU. */
359 virtual void takeOverFrom(BaseCPU *oldCPU);
360
361 /** Get the current instruction sequence number, and increment it. */
362 InstSeqNum getAndIncrementInstSeq()
363 { return globalSeqNum++; }
364
365#if FULL_SYSTEM
366 /** Update the Virt and Phys ports of all ThreadContexts to
367 * reflect change in memory connections. */
368 void updateMemPorts();
369
370 /** Check if this address is a valid instruction address. */
371 bool validInstAddr(Addr addr) { return true; }
372
373 /** Check if this address is a valid data address. */
374 bool validDataAddr(Addr addr) { return true; }
375
376 /** Get instruction asid. */
377 int getInstAsid(unsigned tid)
378 { return regFile.miscRegs[tid].getInstAsid(); }
379
380 /** Get data asid. */
381 int getDataAsid(unsigned tid)
382 { return regFile.miscRegs[tid].getDataAsid(); }
383#else
384 /** Get instruction asid. */
385 int getInstAsid(unsigned tid)
386 { return thread[tid]->getInstAsid(); }
387
388 /** Get data asid. */
389 int getDataAsid(unsigned tid)
390 { return thread[tid]->getDataAsid(); }
391
392#endif
393
394 /** Register accessors. Index refers to the physical register index. */
395 uint64_t readIntReg(int reg_idx);
396
397 TheISA::FloatReg readFloatReg(int reg_idx);
398
399 TheISA::FloatReg readFloatReg(int reg_idx, int width);
400
401 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
402
403 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
404
405 void setIntReg(int reg_idx, uint64_t val);
406
407 void setFloatReg(int reg_idx, TheISA::FloatReg val);
408
409 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
410
411 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
412
413 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
414
415 uint64_t readArchIntReg(int reg_idx, unsigned tid);
416
417 float readArchFloatRegSingle(int reg_idx, unsigned tid);
418
419 double readArchFloatRegDouble(int reg_idx, unsigned tid);
420
421 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
422
423 /** Architectural register accessors. Looks up in the commit
424 * rename table to obtain the true physical index of the
425 * architected register first, then accesses that physical
426 * register.
427 */
428 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
429
430 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
431
432 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
433
434 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
435
436 /** Reads the commit PC of a specific thread. */
437 Addr readPC(unsigned tid);
438
439 /** Sets the commit PC of a specific thread. */
440 void setPC(Addr new_PC, unsigned tid);
441
442 /** Reads the commit micro PC of a specific thread. */
443 Addr readMicroPC(unsigned tid);
444
445 /** Sets the commmit micro PC of a specific thread. */
446 void setMicroPC(Addr new_microPC, unsigned tid);
447
448 /** Reads the next PC of a specific thread. */
449 Addr readNextPC(unsigned tid);
450
451 /** Sets the next PC of a specific thread. */
452 void setNextPC(Addr val, unsigned tid);
453
454 /** Reads the next NPC of a specific thread. */
455 Addr readNextNPC(unsigned tid);
456
457 /** Sets the next NPC of a specific thread. */
458 void setNextNPC(Addr val, unsigned tid);
459
460 /** Reads the commit next micro PC of a specific thread. */
461 Addr readNextMicroPC(unsigned tid);
462
463 /** Sets the commit next micro PC of a specific thread. */
464 void setNextMicroPC(Addr val, unsigned tid);
465
466 /** Function to add instruction onto the head of the list of the
467 * instructions. Used when new instructions are fetched.
468 */
469 ListIt addInst(DynInstPtr &inst);
470
471 /** Function to tell the CPU that an instruction has completed. */
472 void instDone(unsigned tid);
473
474 /** Add Instructions to the CPU Remove List*/
475 void addToRemoveList(DynInstPtr &inst);
476
477 /** Remove an instruction from the front end of the list. There's
478 * no restriction on location of the instruction.
479 */
480 void removeFrontInst(DynInstPtr &inst);
481
482 /** Remove all instructions that are not currently in the ROB.
483 * There's also an option to not squash delay slot instructions.*/
484 void removeInstsNotInROB(unsigned tid);
485
486 /** Remove all instructions younger than the given sequence number. */
487 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
488
489 /** Removes the instruction pointed to by the iterator. */
490 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
491
492 /** Cleans up all instructions on the remove list. */
493 void cleanUpRemovedInsts();
494
495 /** Debug function to print all instructions on the list. */
496 void dumpInsts();
497
498 public:
499 /** List of all the instructions in flight. */
500 std::list<DynInstPtr> instList;
501
502 /** List of all the instructions that will be removed at the end of this
503 * cycle.
504 */
505 std::queue<ListIt> removeList;
506
507#ifdef DEBUG
508 /** Debug structure to keep track of the sequence numbers still in
509 * flight.
510 */
511 std::set<InstSeqNum> snList;
512#endif
513
514 /** Records if instructions need to be removed this cycle due to
515 * being retired or squashed.
516 */
517 bool removeInstsThisCycle;
518
519 protected:
520 /** The fetch stage. */
521 typename CPUPolicy::Fetch fetch;
522
523 /** The decode stage. */
524 typename CPUPolicy::Decode decode;
525
526 /** The dispatch stage. */
527 typename CPUPolicy::Rename rename;
528
529 /** The issue/execute/writeback stages. */
530 typename CPUPolicy::IEW iew;
531
532 /** The commit stage. */
533 typename CPUPolicy::Commit commit;
534
535 /** The register file. */
536 typename CPUPolicy::RegFile regFile;
537
538 /** The free list. */
539 typename CPUPolicy::FreeList freeList;
540
541 /** The rename map. */
542 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
543
544 /** The commit rename map. */
545 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
546
547 /** The re-order buffer. */
548 typename CPUPolicy::ROB rob;
549
550 /** Active Threads List */
551 std::list<unsigned> activeThreads;
552
553 /** Integer Register Scoreboard */
554 Scoreboard scoreboard;
555
556 public:
557 /** Enum to give each stage a specific index, so when calling
558 * activateStage() or deactivateStage(), they can specify which stage
559 * is being activated/deactivated.
560 */
561 enum StageIdx {
562 FetchIdx,
563 DecodeIdx,
564 RenameIdx,
565 IEWIdx,
566 CommitIdx,
567 NumStages };
568
569 /** Typedefs from the Impl to get the structs that each of the
570 * time buffers should use.
571 */
572 typedef typename CPUPolicy::TimeStruct TimeStruct;
573
574 typedef typename CPUPolicy::FetchStruct FetchStruct;
575
576 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
577
578 typedef typename CPUPolicy::RenameStruct RenameStruct;
579
580 typedef typename CPUPolicy::IEWStruct IEWStruct;
581
582 /** The main time buffer to do backwards communication. */
583 TimeBuffer<TimeStruct> timeBuffer;
584
585 /** The fetch stage's instruction queue. */
586 TimeBuffer<FetchStruct> fetchQueue;
587
588 /** The decode stage's instruction queue. */
589 TimeBuffer<DecodeStruct> decodeQueue;
590
591 /** The rename stage's instruction queue. */
592 TimeBuffer<RenameStruct> renameQueue;
593
594 /** The IEW stage's instruction queue. */
595 TimeBuffer<IEWStruct> iewQueue;
596
597 private:
598 /** The activity recorder; used to tell if the CPU has any
599 * activity remaining or if it can go to idle and deschedule
600 * itself.
601 */
602 ActivityRecorder activityRec;
603
604 public:
605 /** Records that there was time buffer activity this cycle. */
606 void activityThisCycle() { activityRec.activity(); }
607
608 /** Changes a stage's status to active within the activity recorder. */
609 void activateStage(const StageIdx idx)
610 { activityRec.activateStage(idx); }
611
612 /** Changes a stage's status to inactive within the activity recorder. */
613 void deactivateStage(const StageIdx idx)
614 { activityRec.deactivateStage(idx); }
615
616 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
617 void wakeCPU();
618
619 /** Gets a free thread id. Use if thread ids change across system. */
620 int getFreeTid();
621
622 public:
623 /** Returns a pointer to a thread context. */
624 ThreadContext *tcBase(unsigned tid)
625 {
626 return thread[tid]->getTC();
627 }
628
629 /** The global sequence number counter. */
630 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
631
632#if USE_CHECKER
633 /** Pointer to the checker, which can dynamically verify
634 * instruction results at run time. This can be set to NULL if it
635 * is not being used.
636 */
637 Checker<DynInstPtr> *checker;
638#endif
639
640#if FULL_SYSTEM
641 /** Pointer to the system. */
642 System *system;
643
644 /** Pointer to physical memory. */
645 PhysicalMemory *physmem;
646#endif
647
648 /** Event to call process() on once draining has completed. */
649 Event *drainEvent;
650
651 /** Counter of how many stages have completed draining. */
652 int drainCount;
653
654 /** Pointers to all of the threads in the CPU. */
655 std::vector<Thread *> thread;
656
657 /** Whether or not the CPU should defer its registration. */
658 bool deferRegistration;
659
660 /** Is there a context switch pending? */
661 bool contextSwitch;
662
663 /** Threads Scheduled to Enter CPU */
664 std::list<int> cpuWaitList;
665
666 /** The cycle that the CPU was last running, used for statistics. */
667 Tick lastRunningCycle;
668
669 /** The cycle that the CPU was last activated by a new thread*/
670 Tick lastActivatedCycle;
671
672 /** Number of Threads CPU can process */
673 unsigned numThreads;
674
675 /** Mapping for system thread id to cpu id */
676 std::map<unsigned,unsigned> threadMap;
677
678 /** Available thread ids in the cpu*/
679 std::vector<unsigned> tids;
680
681 /** Stat for total number of times the CPU is descheduled. */
682 Stats::Scalar<> timesIdled;
683 /** Stat for total number of cycles the CPU spends descheduled. */
684 Stats::Scalar<> idleCycles;
685 /** Stat for the number of committed instructions per thread. */
686 Stats::Vector<> committedInsts;
687 /** Stat for the total number of committed instructions. */
688 Stats::Scalar<> totalCommittedInsts;
689 /** Stat for the CPI per thread. */
690 Stats::Formula cpi;
691 /** Stat for the total CPI. */
692 Stats::Formula totalCpi;
693 /** Stat for the IPC per thread. */
694 Stats::Formula ipc;
695 /** Stat for the total IPC. */
696 Stats::Formula totalIpc;
697};
698
699#endif // __CPU_O3_CPU_HH__
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "config/use_checker.hh"
46#include "cpu/activity.hh"
47#include "cpu/base.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/o3/comm.hh"
50#include "cpu/o3/cpu_policy.hh"
51#include "cpu/o3/scoreboard.hh"
52#include "cpu/o3/thread_state.hh"
53//#include "cpu/o3/thread_context.hh"
54#include "sim/process.hh"
55
56template <class>
57class Checker;
58class ThreadContext;
59template <class>
60class O3ThreadContext;
61
62class Checkpoint;
63class MemObject;
64class Process;
65
66class BaseO3CPU : public BaseCPU
67{
68 //Stuff that's pretty ISA independent will go here.
69 public:
70 typedef BaseCPU::Params Params;
71
72 BaseO3CPU(Params *params);
73
74 void regStats();
75
76 /** Sets this CPU's ID. */
77 void setCpuId(int id) { cpu_id = id; }
78
79 /** Reads this CPU's ID. */
80 int readCpuId() { return cpu_id; }
81
82 protected:
83 int cpu_id;
84};
85
86/**
87 * FullO3CPU class, has each of the stages (fetch through commit)
88 * within it, as well as all of the time buffers between stages. The
89 * tick() function for the CPU is defined here.
90 */
91template <class Impl>
92class FullO3CPU : public BaseO3CPU
93{
94 public:
95 // Typedefs from the Impl here.
96 typedef typename Impl::CPUPol CPUPolicy;
97 typedef typename Impl::Params Params;
98 typedef typename Impl::DynInstPtr DynInstPtr;
99 typedef typename Impl::O3CPU O3CPU;
100
101 typedef O3ThreadState<Impl> Thread;
102
103 typedef typename std::list<DynInstPtr>::iterator ListIt;
104
105 friend class O3ThreadContext<Impl>;
106
107 public:
108 enum Status {
109 Running,
110 Idle,
111 Halted,
112 Blocked,
113 SwitchedOut
114 };
115
116#if FULL_SYSTEM
117 TheISA::ITB * itb;
118 TheISA::DTB * dtb;
119#endif
120
121 /** Overall CPU status. */
122 Status _status;
123
124 /** Per-thread status in CPU, used for SMT. */
125 Status _threadStatus[Impl::MaxThreads];
126
127 private:
128 class TickEvent : public Event
129 {
130 private:
131 /** Pointer to the CPU. */
132 FullO3CPU<Impl> *cpu;
133
134 public:
135 /** Constructs a tick event. */
136 TickEvent(FullO3CPU<Impl> *c);
137
138 /** Processes a tick event, calling tick() on the CPU. */
139 void process();
140 /** Returns the description of the tick event. */
141 const char *description();
142 };
143
144 /** The tick event used for scheduling CPU ticks. */
145 TickEvent tickEvent;
146
147 /** Schedule tick event, regardless of its current state. */
148 void scheduleTickEvent(int delay)
149 {
150 if (tickEvent.squashed())
151 tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
152 else if (!tickEvent.scheduled())
153 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
154 }
155
156 /** Unschedule tick event, regardless of its current state. */
157 void unscheduleTickEvent()
158 {
159 if (tickEvent.scheduled())
160 tickEvent.squash();
161 }
162
163 class ActivateThreadEvent : public Event
164 {
165 private:
166 /** Number of Thread to Activate */
167 int tid;
168
169 /** Pointer to the CPU. */
170 FullO3CPU<Impl> *cpu;
171
172 public:
173 /** Constructs the event. */
174 ActivateThreadEvent();
175
176 /** Initialize Event */
177 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
178
179 /** Processes the event, calling activateThread() on the CPU. */
180 void process();
181
182 /** Returns the description of the event. */
183 const char *description();
184 };
185
186 /** Schedule thread to activate , regardless of its current state. */
187 void scheduleActivateThreadEvent(int tid, int delay)
188 {
189 // Schedule thread to activate, regardless of its current state.
190 if (activateThreadEvent[tid].squashed())
191 activateThreadEvent[tid].
192 reschedule(nextCycle(curTick + cycles(delay)));
193 else if (!activateThreadEvent[tid].scheduled())
194 activateThreadEvent[tid].
195 schedule(nextCycle(curTick + cycles(delay)));
196 }
197
198 /** Unschedule actiavte thread event, regardless of its current state. */
199 void unscheduleActivateThreadEvent(int tid)
200 {
201 if (activateThreadEvent[tid].scheduled())
202 activateThreadEvent[tid].squash();
203 }
204
205 /** The tick event used for scheduling CPU ticks. */
206 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
207
208 class DeallocateContextEvent : public Event
209 {
210 private:
211 /** Number of Thread to deactivate */
212 int tid;
213
214 /** Should the thread be removed from the CPU? */
215 bool remove;
216
217 /** Pointer to the CPU. */
218 FullO3CPU<Impl> *cpu;
219
220 public:
221 /** Constructs the event. */
222 DeallocateContextEvent();
223
224 /** Initialize Event */
225 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
226
227 /** Processes the event, calling activateThread() on the CPU. */
228 void process();
229
230 /** Sets whether the thread should also be removed from the CPU. */
231 void setRemove(bool _remove) { remove = _remove; }
232
233 /** Returns the description of the event. */
234 const char *description();
235 };
236
237 /** Schedule cpu to deallocate thread context.*/
238 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
239 {
240 // Schedule thread to activate, regardless of its current state.
241 if (deallocateContextEvent[tid].squashed())
242 deallocateContextEvent[tid].
243 reschedule(nextCycle(curTick + cycles(delay)));
244 else if (!deallocateContextEvent[tid].scheduled())
245 deallocateContextEvent[tid].
246 schedule(nextCycle(curTick + cycles(delay)));
247 }
248
249 /** Unschedule thread deallocation in CPU */
250 void unscheduleDeallocateContextEvent(int tid)
251 {
252 if (deallocateContextEvent[tid].scheduled())
253 deallocateContextEvent[tid].squash();
254 }
255
256 /** The tick event used for scheduling CPU ticks. */
257 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
258
259 public:
260 /** Constructs a CPU with the given parameters. */
261 FullO3CPU(O3CPU *o3_cpu, Params *params);
262 /** Destructor. */
263 ~FullO3CPU();
264
265 /** Registers statistics. */
266 void fullCPURegStats();
267
268 /** Returns a specific port. */
269 Port *getPort(const std::string &if_name, int idx);
270
271 /** Ticks CPU, calling tick() on each stage, and checking the overall
272 * activity to see if the CPU should deschedule itself.
273 */
274 void tick();
275
276 /** Initialize the CPU */
277 void init();
278
279 /** Returns the Number of Active Threads in the CPU */
280 int numActiveThreads()
281 { return activeThreads.size(); }
282
283 /** Add Thread to Active Threads List */
284 void activateThread(unsigned tid);
285
286 /** Remove Thread from Active Threads List */
287 void deactivateThread(unsigned tid);
288
289 /** Setup CPU to insert a thread's context */
290 void insertThread(unsigned tid);
291
292 /** Remove all of a thread's context from CPU */
293 void removeThread(unsigned tid);
294
295 /** Count the Total Instructions Committed in the CPU. */
296 virtual Counter totalInstructions() const
297 {
298 Counter total(0);
299
300 for (int i=0; i < thread.size(); i++)
301 total += thread[i]->numInst;
302
303 return total;
304 }
305
306 /** Add Thread to Active Threads List. */
307 void activateContext(int tid, int delay);
308
309 /** Remove Thread from Active Threads List */
310 void suspendContext(int tid);
311
312 /** Remove Thread from Active Threads List &&
313 * Possibly Remove Thread Context from CPU.
314 */
315 bool deallocateContext(int tid, bool remove, int delay = 1);
316
317 /** Remove Thread from Active Threads List &&
318 * Remove Thread Context from CPU.
319 */
320 void haltContext(int tid);
321
322 /** Activate a Thread When CPU Resources are Available. */
323 void activateWhenReady(int tid);
324
325 /** Add or Remove a Thread Context in the CPU. */
326 void doContextSwitch();
327
328 /** Update The Order In Which We Process Threads. */
329 void updateThreadPriority();
330
331 /** Serialize state. */
332 virtual void serialize(std::ostream &os);
333
334 /** Unserialize from a checkpoint. */
335 virtual void unserialize(Checkpoint *cp, const std::string §ion);
336
337 public:
338 /** Executes a syscall on this cycle.
339 * ---------------------------------------
340 * Note: this is a virtual function. CPU-Specific
341 * functionality defined in derived classes
342 */
343 virtual void syscall(int tid) { panic("Unimplemented!"); }
344
345 /** Starts draining the CPU's pipeline of all instructions in
346 * order to stop all memory accesses. */
347 virtual unsigned int drain(Event *drain_event);
348
349 /** Resumes execution after a drain. */
350 virtual void resume();
351
352 /** Signals to this CPU that a stage has completed switching out. */
353 void signalDrained();
354
355 /** Switches out this CPU. */
356 virtual void switchOut();
357
358 /** Takes over from another CPU. */
359 virtual void takeOverFrom(BaseCPU *oldCPU);
360
361 /** Get the current instruction sequence number, and increment it. */
362 InstSeqNum getAndIncrementInstSeq()
363 { return globalSeqNum++; }
364
365#if FULL_SYSTEM
366 /** Update the Virt and Phys ports of all ThreadContexts to
367 * reflect change in memory connections. */
368 void updateMemPorts();
369
370 /** Check if this address is a valid instruction address. */
371 bool validInstAddr(Addr addr) { return true; }
372
373 /** Check if this address is a valid data address. */
374 bool validDataAddr(Addr addr) { return true; }
375
376 /** Get instruction asid. */
377 int getInstAsid(unsigned tid)
378 { return regFile.miscRegs[tid].getInstAsid(); }
379
380 /** Get data asid. */
381 int getDataAsid(unsigned tid)
382 { return regFile.miscRegs[tid].getDataAsid(); }
383#else
384 /** Get instruction asid. */
385 int getInstAsid(unsigned tid)
386 { return thread[tid]->getInstAsid(); }
387
388 /** Get data asid. */
389 int getDataAsid(unsigned tid)
390 { return thread[tid]->getDataAsid(); }
391
392#endif
393
394 /** Register accessors. Index refers to the physical register index. */
395 uint64_t readIntReg(int reg_idx);
396
397 TheISA::FloatReg readFloatReg(int reg_idx);
398
399 TheISA::FloatReg readFloatReg(int reg_idx, int width);
400
401 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
402
403 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
404
405 void setIntReg(int reg_idx, uint64_t val);
406
407 void setFloatReg(int reg_idx, TheISA::FloatReg val);
408
409 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
410
411 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
412
413 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
414
415 uint64_t readArchIntReg(int reg_idx, unsigned tid);
416
417 float readArchFloatRegSingle(int reg_idx, unsigned tid);
418
419 double readArchFloatRegDouble(int reg_idx, unsigned tid);
420
421 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
422
423 /** Architectural register accessors. Looks up in the commit
424 * rename table to obtain the true physical index of the
425 * architected register first, then accesses that physical
426 * register.
427 */
428 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
429
430 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
431
432 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
433
434 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
435
436 /** Reads the commit PC of a specific thread. */
437 Addr readPC(unsigned tid);
438
439 /** Sets the commit PC of a specific thread. */
440 void setPC(Addr new_PC, unsigned tid);
441
442 /** Reads the commit micro PC of a specific thread. */
443 Addr readMicroPC(unsigned tid);
444
445 /** Sets the commmit micro PC of a specific thread. */
446 void setMicroPC(Addr new_microPC, unsigned tid);
447
448 /** Reads the next PC of a specific thread. */
449 Addr readNextPC(unsigned tid);
450
451 /** Sets the next PC of a specific thread. */
452 void setNextPC(Addr val, unsigned tid);
453
454 /** Reads the next NPC of a specific thread. */
455 Addr readNextNPC(unsigned tid);
456
457 /** Sets the next NPC of a specific thread. */
458 void setNextNPC(Addr val, unsigned tid);
459
460 /** Reads the commit next micro PC of a specific thread. */
461 Addr readNextMicroPC(unsigned tid);
462
463 /** Sets the commit next micro PC of a specific thread. */
464 void setNextMicroPC(Addr val, unsigned tid);
465
466 /** Function to add instruction onto the head of the list of the
467 * instructions. Used when new instructions are fetched.
468 */
469 ListIt addInst(DynInstPtr &inst);
470
471 /** Function to tell the CPU that an instruction has completed. */
472 void instDone(unsigned tid);
473
474 /** Add Instructions to the CPU Remove List*/
475 void addToRemoveList(DynInstPtr &inst);
476
477 /** Remove an instruction from the front end of the list. There's
478 * no restriction on location of the instruction.
479 */
480 void removeFrontInst(DynInstPtr &inst);
481
482 /** Remove all instructions that are not currently in the ROB.
483 * There's also an option to not squash delay slot instructions.*/
484 void removeInstsNotInROB(unsigned tid);
485
486 /** Remove all instructions younger than the given sequence number. */
487 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
488
489 /** Removes the instruction pointed to by the iterator. */
490 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
491
492 /** Cleans up all instructions on the remove list. */
493 void cleanUpRemovedInsts();
494
495 /** Debug function to print all instructions on the list. */
496 void dumpInsts();
497
498 public:
499 /** List of all the instructions in flight. */
500 std::list<DynInstPtr> instList;
501
502 /** List of all the instructions that will be removed at the end of this
503 * cycle.
504 */
505 std::queue<ListIt> removeList;
506
507#ifdef DEBUG
508 /** Debug structure to keep track of the sequence numbers still in
509 * flight.
510 */
511 std::set<InstSeqNum> snList;
512#endif
513
514 /** Records if instructions need to be removed this cycle due to
515 * being retired or squashed.
516 */
517 bool removeInstsThisCycle;
518
519 protected:
520 /** The fetch stage. */
521 typename CPUPolicy::Fetch fetch;
522
523 /** The decode stage. */
524 typename CPUPolicy::Decode decode;
525
526 /** The dispatch stage. */
527 typename CPUPolicy::Rename rename;
528
529 /** The issue/execute/writeback stages. */
530 typename CPUPolicy::IEW iew;
531
532 /** The commit stage. */
533 typename CPUPolicy::Commit commit;
534
535 /** The register file. */
536 typename CPUPolicy::RegFile regFile;
537
538 /** The free list. */
539 typename CPUPolicy::FreeList freeList;
540
541 /** The rename map. */
542 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
543
544 /** The commit rename map. */
545 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
546
547 /** The re-order buffer. */
548 typename CPUPolicy::ROB rob;
549
550 /** Active Threads List */
551 std::list<unsigned> activeThreads;
552
553 /** Integer Register Scoreboard */
554 Scoreboard scoreboard;
555
556 public:
557 /** Enum to give each stage a specific index, so when calling
558 * activateStage() or deactivateStage(), they can specify which stage
559 * is being activated/deactivated.
560 */
561 enum StageIdx {
562 FetchIdx,
563 DecodeIdx,
564 RenameIdx,
565 IEWIdx,
566 CommitIdx,
567 NumStages };
568
569 /** Typedefs from the Impl to get the structs that each of the
570 * time buffers should use.
571 */
572 typedef typename CPUPolicy::TimeStruct TimeStruct;
573
574 typedef typename CPUPolicy::FetchStruct FetchStruct;
575
576 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
577
578 typedef typename CPUPolicy::RenameStruct RenameStruct;
579
580 typedef typename CPUPolicy::IEWStruct IEWStruct;
581
582 /** The main time buffer to do backwards communication. */
583 TimeBuffer<TimeStruct> timeBuffer;
584
585 /** The fetch stage's instruction queue. */
586 TimeBuffer<FetchStruct> fetchQueue;
587
588 /** The decode stage's instruction queue. */
589 TimeBuffer<DecodeStruct> decodeQueue;
590
591 /** The rename stage's instruction queue. */
592 TimeBuffer<RenameStruct> renameQueue;
593
594 /** The IEW stage's instruction queue. */
595 TimeBuffer<IEWStruct> iewQueue;
596
597 private:
598 /** The activity recorder; used to tell if the CPU has any
599 * activity remaining or if it can go to idle and deschedule
600 * itself.
601 */
602 ActivityRecorder activityRec;
603
604 public:
605 /** Records that there was time buffer activity this cycle. */
606 void activityThisCycle() { activityRec.activity(); }
607
608 /** Changes a stage's status to active within the activity recorder. */
609 void activateStage(const StageIdx idx)
610 { activityRec.activateStage(idx); }
611
612 /** Changes a stage's status to inactive within the activity recorder. */
613 void deactivateStage(const StageIdx idx)
614 { activityRec.deactivateStage(idx); }
615
616 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
617 void wakeCPU();
618
619 /** Gets a free thread id. Use if thread ids change across system. */
620 int getFreeTid();
621
622 public:
623 /** Returns a pointer to a thread context. */
624 ThreadContext *tcBase(unsigned tid)
625 {
626 return thread[tid]->getTC();
627 }
628
629 /** The global sequence number counter. */
630 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
631
632#if USE_CHECKER
633 /** Pointer to the checker, which can dynamically verify
634 * instruction results at run time. This can be set to NULL if it
635 * is not being used.
636 */
637 Checker<DynInstPtr> *checker;
638#endif
639
640#if FULL_SYSTEM
641 /** Pointer to the system. */
642 System *system;
643
644 /** Pointer to physical memory. */
645 PhysicalMemory *physmem;
646#endif
647
648 /** Event to call process() on once draining has completed. */
649 Event *drainEvent;
650
651 /** Counter of how many stages have completed draining. */
652 int drainCount;
653
654 /** Pointers to all of the threads in the CPU. */
655 std::vector<Thread *> thread;
656
657 /** Whether or not the CPU should defer its registration. */
658 bool deferRegistration;
659
660 /** Is there a context switch pending? */
661 bool contextSwitch;
662
663 /** Threads Scheduled to Enter CPU */
664 std::list<int> cpuWaitList;
665
666 /** The cycle that the CPU was last running, used for statistics. */
667 Tick lastRunningCycle;
668
669 /** The cycle that the CPU was last activated by a new thread*/
670 Tick lastActivatedCycle;
671
672 /** Number of Threads CPU can process */
673 unsigned numThreads;
674
675 /** Mapping for system thread id to cpu id */
676 std::map<unsigned,unsigned> threadMap;
677
678 /** Available thread ids in the cpu*/
679 std::vector<unsigned> tids;
680
681 /** Stat for total number of times the CPU is descheduled. */
682 Stats::Scalar<> timesIdled;
683 /** Stat for total number of cycles the CPU spends descheduled. */
684 Stats::Scalar<> idleCycles;
685 /** Stat for the number of committed instructions per thread. */
686 Stats::Vector<> committedInsts;
687 /** Stat for the total number of committed instructions. */
688 Stats::Scalar<> totalCommittedInsts;
689 /** Stat for the CPI per thread. */
690 Stats::Formula cpi;
691 /** Stat for the total CPI. */
692 Stats::Formula totalCpi;
693 /** Stat for the IPC per thread. */
694 Stats::Formula ipc;
695 /** Stat for the total IPC. */
696 Stats::Formula totalIpc;
697};
698
699#endif // __CPU_O3_CPU_HH__