1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_CPU_HH__
30#define __CPU_O3_CPU_HH__
31
32#include <iostream>
33#include <list>
34#include <queue>
35#include <set>
36#include <vector>
37
38#include "base/statistics.hh"
39#include "base/timebuf.hh"
40#include "config/full_system.hh"
41#include "cpu/activity.hh"
42#include "cpu/base.hh"
43#include "cpu/cpu_exec_context.hh"
44#include "cpu/o3/comm.hh"
45#include "cpu/o3/cpu_policy.hh"
46#include "cpu/o3/scoreboard.hh"
47#include "cpu/o3/thread_state.hh"
48#include "sim/process.hh"
49
50template <class>
51class Checker;
52class ExecContext;
53class MemInterface;
54class Process;
55
56class BaseFullCPU : public BaseCPU
57{
58 //Stuff that's pretty ISA independent will go here.
59 public:
60 typedef BaseCPU::Params Params;
61
62 BaseFullCPU(Params *params);
63
64 void regStats();
65
66 protected:
67 int cpu_id;
68};
69
70template <class Impl>
71class FullO3CPU : public BaseFullCPU
72{
73 public:
74 // Typedefs from the Impl here.
75 typedef typename Impl::CPUPol CPUPolicy;
76 typedef typename Impl::Params Params;
77 typedef typename Impl::DynInstPtr DynInstPtr;
78
79 typedef O3ThreadState<Impl> Thread;
80
81 typedef typename std::list<DynInstPtr>::iterator ListIt;
82
83 public:
84 enum Status {
85 Running,
86 Idle,
87 Halted,
88 Blocked,
89 SwitchedOut
90 };
91
92 /** Overall CPU status. */
93 Status _status;
94
95 private:
96 class TickEvent : public Event
97 {
98 private:
99 /** Pointer to the CPU. */
100 FullO3CPU<Impl> *cpu;
101
102 public:
103 /** Constructs a tick event. */
104 TickEvent(FullO3CPU<Impl> *c);
105
106 /** Processes a tick event, calling tick() on the CPU. */
107 void process();
108 /** Returns the description of the tick event. */
109 const char *description();
110 };
111
112 /** The tick event used for scheduling CPU ticks. */
113 TickEvent tickEvent;
114
115 /** Schedule tick event, regardless of its current state. */
116 void scheduleTickEvent(int delay)
117 {
118 if (tickEvent.squashed())
119 tickEvent.reschedule(curTick + cycles(delay));
120 else if (!tickEvent.scheduled())
121 tickEvent.schedule(curTick + cycles(delay));
122 }
123
124 /** Unschedule tick event, regardless of its current state. */
125 void unscheduleTickEvent()
126 {
127 if (tickEvent.scheduled())
128 tickEvent.squash();
129 }
130
131 public:
132 /** Constructs a CPU with the given parameters. */
133 FullO3CPU(Params *params);
134 /** Destructor. */
135 ~FullO3CPU();
136
137 /** Registers statistics. */
138 void fullCPURegStats();
139
140 /** Ticks CPU, calling tick() on each stage, and checking the overall
141 * activity to see if the CPU should deschedule itself.
142 */
143 void tick();
144
145 /** Initialize the CPU */
146 void init();
147
148 /** Setup CPU to insert a thread's context */
149 void insertThread(unsigned tid);
150
151 /** Remove all of a thread's context from CPU */
152 void removeThread(unsigned tid);
153
154 /** Count the Total Instructions Committed in the CPU. */
155 virtual Counter totalInstructions() const
156 {
157 Counter total(0);
158
159 for (int i=0; i < thread.size(); i++)
160 total += thread[i]->numInst;
161
162 return total;
163 }
164
165 /** Add Thread to Active Threads List. */
166 void activateContext(int tid, int delay);
167
168 /** Remove Thread from Active Threads List */
169 void suspendContext(int tid);
170
171 /** Remove Thread from Active Threads List &&
172 * Remove Thread Context from CPU.
173 */
174 void deallocateContext(int tid);
175
176 /** Remove Thread from Active Threads List &&
177 * Remove Thread Context from CPU.
178 */
179 void haltContext(int tid);
180
181 /** Activate a Thread When CPU Resources are Available. */
182 void activateWhenReady(int tid);
183
184 /** Add or Remove a Thread Context in the CPU. */
185 void doContextSwitch();
186
187 /** Update The Order In Which We Process Threads. */
188 void updateThreadPriority();
189
190 /** Executes a syscall on this cycle.
191 * ---------------------------------------
192 * Note: this is a virtual function. CPU-Specific
193 * functionality defined in derived classes
194 */
195 virtual void syscall(int tid) { panic("Unimplemented!"); }
196
197 /** Check if there are any system calls pending. */
198 void checkSyscalls();
199
200 /** Switches out this CPU.
201 */
202 void switchOut(Sampler *sampler);
203
204 void signalSwitched();
205
206 /** Takes over from another CPU.
207 */
208 void takeOverFrom(BaseCPU *oldCPU);
209
210 /** Get the current instruction sequence number, and increment it. */
211 InstSeqNum getAndIncrementInstSeq()
212 { return globalSeqNum++; }
213
214#if FULL_SYSTEM
215 /** Check if this address is a valid instruction address. */
216 bool validInstAddr(Addr addr) { return true; }
217
218 /** Check if this address is a valid data address. */
219 bool validDataAddr(Addr addr) { return true; }
220
221 /** Get instruction asid. */
222 int getInstAsid(unsigned tid)
223 { return regFile.miscRegs[tid].getInstAsid(); }
224
225 /** Get data asid. */
226 int getDataAsid(unsigned tid)
227 { return regFile.miscRegs[tid].getDataAsid(); }
228#else
229 /** Check if this address is a valid instruction address. */
230 bool validInstAddr(Addr addr,unsigned tid)
231 { return thread[tid]->validInstAddr(addr); }
232
233 /** Check if this address is a valid data address. */
234 bool validDataAddr(Addr addr,unsigned tid)
235 { return thread[tid]->validDataAddr(addr); }
236
237 /** Get instruction asid. */
238 int getInstAsid(unsigned tid)
239 { return thread[tid]->asid; }
240
241 /** Get data asid. */
242 int getDataAsid(unsigned tid)
243 { return thread[tid]->asid; }
244
245#endif
246
247 //
248 // New accessors for new decoder.
249 //
250 uint64_t readIntReg(int reg_idx);
251
252 FloatReg readFloatReg(int reg_idx);
253
254 FloatReg readFloatReg(int reg_idx, int width);
255
256 FloatRegBits readFloatRegBits(int reg_idx);
257
258 FloatRegBits readFloatRegBits(int reg_idx, int width);
259
260 void setIntReg(int reg_idx, uint64_t val);
261
262 void setFloatReg(int reg_idx, FloatReg val, int width);
263
264 void setFloatReg(int reg_idx, FloatReg val, int width);
265
266 void setFloatRegBits(int reg_idx, FloatRegBits val);
267
268 void setFloatRegBits(int reg_idx, FloatRegBits val);
269
270 uint64_t readArchIntReg(int reg_idx, unsigned tid);
271
272 float readArchFloatRegSingle(int reg_idx, unsigned tid);
273
274 double readArchFloatRegDouble(int reg_idx, unsigned tid);
275
276 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
277
278 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
279
280 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
281
282 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
283
284 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
285
286 uint64_t readPC(unsigned tid);
287
288 void setPC(Addr new_PC,unsigned tid);
289
290 uint64_t readNextPC(unsigned tid);
291
292 void setNextPC(uint64_t val,unsigned tid);
293
294 /** Function to add instruction onto the head of the list of the
295 * instructions. Used when new instructions are fetched.
296 */
297 ListIt addInst(DynInstPtr &inst);
298
299 /** Function to tell the CPU that an instruction has completed. */
300 void instDone(unsigned tid);
301
302 /** Add Instructions to the CPU Remove List*/
303 void addToRemoveList(DynInstPtr &inst);
304
305 /** Remove an instruction from the front end of the list. There's
306 * no restriction on location of the instruction.
307 */
308 void removeFrontInst(DynInstPtr &inst);
309
310 /** Remove all instructions that are not currently in the ROB. */
311 void removeInstsNotInROB(unsigned tid);
312
313 /** Remove all instructions younger than the given sequence number. */
314 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
315
316 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
317
318 void cleanUpRemovedInsts();
319
320 /** Remove all instructions from the list. */
321// void removeAllInsts();
322
323 void dumpInsts();
324
325 /** Basically a wrapper function so that instructions executed at
326 * commit can tell the instruction queue that they have
327 * completed. Eventually this hack should be removed.
328 */
329// void wakeDependents(DynInstPtr &inst);
330
331 public:
332 /** List of all the instructions in flight. */
333 std::list<DynInstPtr> instList;
334
335 /** List of all the instructions that will be removed at the end of this
336 * cycle.
337 */
338 std::queue<ListIt> removeList;
339
340#ifdef DEBUG
341 std::set<InstSeqNum> snList;
342#endif
343
344 /** Records if instructions need to be removed this cycle due to
345 * being retired or squashed.
346 */
347 bool removeInstsThisCycle;
348
349 protected:
350 /** The fetch stage. */
351 typename CPUPolicy::Fetch fetch;
352
353 /** The decode stage. */
354 typename CPUPolicy::Decode decode;
355
356 /** The dispatch stage. */
357 typename CPUPolicy::Rename rename;
358
359 /** The issue/execute/writeback stages. */
360 typename CPUPolicy::IEW iew;
361
362 /** The commit stage. */
363 typename CPUPolicy::Commit commit;
364
365 /** The register file. */
366 typename CPUPolicy::RegFile regFile;
367
368 /** The free list. */
369 typename CPUPolicy::FreeList freeList;
370
371 /** The rename map. */
372 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
373
374 /** The commit rename map. */
375 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
376
377 /** The re-order buffer. */
378 typename CPUPolicy::ROB rob;
379
380 /** Active Threads List */
381 std::list<unsigned> activeThreads;
382
383 /** Integer Register Scoreboard */
384 Scoreboard scoreboard;
385
386 public:
387 /** Enum to give each stage a specific index, so when calling
388 * activateStage() or deactivateStage(), they can specify which stage
389 * is being activated/deactivated.
390 */
391 enum StageIdx {
392 FetchIdx,
393 DecodeIdx,
394 RenameIdx,
395 IEWIdx,
396 CommitIdx,
397 NumStages };
398
399 /** Typedefs from the Impl to get the structs that each of the
400 * time buffers should use.
401 */
402 typedef typename CPUPolicy::TimeStruct TimeStruct;
403
404 typedef typename CPUPolicy::FetchStruct FetchStruct;
405
406 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
407
408 typedef typename CPUPolicy::RenameStruct RenameStruct;
409
410 typedef typename CPUPolicy::IEWStruct IEWStruct;
411
412 /** The main time buffer to do backwards communication. */
413 TimeBuffer<TimeStruct> timeBuffer;
414
415 /** The fetch stage's instruction queue. */
416 TimeBuffer<FetchStruct> fetchQueue;
417
418 /** The decode stage's instruction queue. */
419 TimeBuffer<DecodeStruct> decodeQueue;
420
421 /** The rename stage's instruction queue. */
422 TimeBuffer<RenameStruct> renameQueue;
423
424 /** The IEW stage's instruction queue. */
425 TimeBuffer<IEWStruct> iewQueue;
426
427 public:
428 ActivityRecorder activityRec;
429
430 void activityThisCycle() { activityRec.activity(); }
431
432 void activateStage(const StageIdx idx)
433 { activityRec.activateStage(idx); }
434
435 void deactivateStage(const StageIdx idx)
436 { activityRec.deactivateStage(idx); }
437
438 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
439 void wakeCPU();
440
441 /** Gets a free thread id. Use if thread ids change across system. */
442 int getFreeTid();
443
444 public:
445 /** Temporary function to get pointer to exec context. */
446 ExecContext *xcBase(unsigned tid)
447 {
448 return thread[tid]->getXCProxy();
449 }
450
451 /** The global sequence number counter. */
452 InstSeqNum globalSeqNum;
453
454 Checker<DynInstPtr> *checker;
455
456#if FULL_SYSTEM
457 /** Pointer to the system. */
458 System *system;
459
460 /** Pointer to the memory controller. */
461 MemoryController *memCtrl;
462 /** Pointer to physical memory. */
463 PhysicalMemory *physmem;
464#endif
465
466 /** Pointer to memory. */
467 FunctionalMemory *mem;
468
469 Sampler *sampler;
470
471 int switchCount;
472
473 // List of all ExecContexts.
474 std::vector<Thread *> thread;
475
476#if 0
477 /** Page table pointer. */
478 PageTable *pTable;
479#endif
480
481 /** Pointer to the icache interface. */
482 MemInterface *icacheInterface;
483 /** Pointer to the dcache interface. */
484 MemInterface *dcacheInterface;
485
486 /** Whether or not the CPU should defer its registration. */
487 bool deferRegistration;
488
489 /** Is there a context switch pending? */
490 bool contextSwitch;
491
492 /** Threads Scheduled to Enter CPU */
493 std::list<int> cpuWaitList;
494
495 /** The cycle that the CPU was last running, used for statistics. */
496 Tick lastRunningCycle;
497
498 /** Number of Threads CPU can process */
499 unsigned numThreads;
500
501 /** Mapping for system thread id to cpu id */
502 std::map<unsigned,unsigned> threadMap;
503
504 /** Available thread ids in the cpu*/
505 std::vector<unsigned> tids;
506
507 /** Stat for total number of times the CPU is descheduled. */
508 Stats::Scalar<> timesIdled;
509 /** Stat for total number of cycles the CPU spends descheduled. */
510 Stats::Scalar<> idleCycles;
511 /** Stat for the number of committed instructions per thread. */
512 Stats::Vector<> committedInsts;
513 /** Stat for the total number of committed instructions. */
514 Stats::Scalar<> totalCommittedInsts;
515 /** Stat for the CPI per thread. */
516 Stats::Formula cpi;
517 /** Stat for the total CPI. */
518 Stats::Formula totalCpi;
519 /** Stat for the IPC per thread. */
520 Stats::Formula ipc;
521 /** Stat for the total IPC. */
522 Stats::Formula totalIpc;
523};
524
525#endif // __CPU_O3_CPU_HH__