1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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144 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
145 { }
146
147 protected:
148
149 /** Timing version of receive. Handles setting fetch to the
150 * proper status to start fetching. */
151 virtual bool recvTiming(PacketPtr pkt);
152
153 /** Handles doing a retry of a failed fetch. */
154 virtual void recvRetry();
155 };
156
157 /**
158 * DcachePort class for the load/store queue.
159 */

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171 { }
172
173 protected:
174
175 /** Timing version of receive. Handles writing back and
176 * completing the load or store that has returned from
177 * memory. */
178 virtual bool recvTiming(PacketPtr pkt);
179
180 /** Handles doing a retry of the previous send. */
181 virtual void recvRetry();
182
183 /**
184 * As this CPU requires snooping to maintain the load store queue
185 * change the behaviour from the base CPU port.
186 *

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