1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

--- 103 unchanged lines hidden (view full) ---

113
114 /** Overall CPU status. */
115 Status _status;
116
117 /** Per-thread status in CPU, used for SMT. */
118 Status _threadStatus[Impl::MaxThreads];
119
120 private:
121 class TickEvent : public Event
122 {
123 private:
124 /** Pointer to the CPU. */
125 FullO3CPU<Impl> *cpu;
126
127 public:
128 /** Constructs a tick event. */

--- 432 unchanged lines hidden (view full) ---

561 /** Active Threads List */
562 std::list<ThreadID> activeThreads;
563
564 /** Integer Register Scoreboard */
565 Scoreboard scoreboard;
566
567 TheISA::ISA isa[Impl::MaxThreads];
568
569 public:
570 /** Enum to give each stage a specific index, so when calling
571 * activateStage() or deactivateStage(), they can specify which stage
572 * is being activated/deactivated.
573 */
574 enum StageIdx {
575 FetchIdx,
576 DecodeIdx,

--- 122 unchanged lines hidden (view full) ---

699 /** CPU write function, forwards write to LSQ. */
700 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
701 uint8_t *data, int store_idx)
702 {
703 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
704 data, store_idx);
705 }
706
707 /** Get the dcache port (used to find block size for translations). */
708 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
709
710 Addr lockAddr;
711
712 /** Temporary fix for the lock flag, works in the UP case. */
713 bool lockFlag;
714
715 /** Stat for total number of times the CPU is descheduled. */
716 Stats::Scalar timesIdled;

--- 30 unchanged lines hidden ---