1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60class MemObject;
61class Process;
62
63class BaseO3CPU : public BaseCPU
64{
65 //Stuff that's pretty ISA independent will go here.
66 public:
67 typedef BaseCPU::Params Params;

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104 friend class O3ThreadContext<Impl>;
105
106 public:
107 enum Status {
108 Running,
109 Idle,
110 Halted,
111 Blocked,
112 SwitchedOut
113 };
114
115 /** Overall CPU status. */
116 Status _status;
117
118 /** Per-thread status in CPU, used for SMT. */
119 Status _threadStatus[Impl::MaxThreads];

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265
266 /** Executes a syscall on this cycle.
267 * ---------------------------------------
268 * Note: this is a virtual function. CPU-Specific
269 * functionality defined in derived classes
270 */
271 virtual void syscall(int tid) { panic("Unimplemented!"); }
272
273 /** Switches out this CPU. */
274 void switchOut();
275
276 /** Signals to this CPU that a stage has completed switching out. */
277 void signalSwitched();
278
279 /** Takes over from another CPU. */
280 void takeOverFrom(BaseCPU *oldCPU);
281
282 /** Get the current instruction sequence number, and increment it. */
283 InstSeqNum getAndIncrementInstSeq()
284 { return globalSeqNum++; }
285
286#if FULL_SYSTEM
287 /** Check if this address is a valid instruction address. */
288 bool validInstAddr(Addr addr) { return true; }

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545
546 /** Pointer to physical memory. */
547 PhysicalMemory *physmem;
548#endif
549
550 /** Pointer to memory. */
551 MemObject *mem;
552
553 /** Counter of how many stages have completed switching out. */
554 int switchCount;
555
556 /** Pointers to all of the threads in the CPU. */
557 std::vector<Thread *> thread;
558
559 /** Pointer to the icache interface. */
560 MemInterface *icacheInterface;
561 /** Pointer to the dcache interface. */
562 MemInterface *dcacheInterface;
563

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