1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44#include "config/full_system.hh"
45#include "cpu/activity.hh"
46#include "cpu/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52#include "sim/process.hh"
53
54template <class>
55class Checker;
56class ThreadContext;
57class MemObject;
58class Process;
59
60class BaseO3CPU : public BaseCPU
61{
62 //Stuff that's pretty ISA independent will go here.
63 public:
64 typedef BaseCPU::Params Params;
65
66 BaseO3CPU(Params *params);
67
68 void regStats();
69
70 int readCpuId() { return cpu_id; }
71
72 protected:
73 int cpu_id;
74};
75
76/**
77 * FullO3CPU class, has each of the stages (fetch through commit)

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89 typedef typename Impl::CPUPol CPUPolicy;
90 typedef typename Impl::Params Params;
91 typedef typename Impl::DynInstPtr DynInstPtr;
92
93 typedef O3ThreadState<Impl> Thread;
94
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 public:
98 enum Status {
99 Running,
100 Idle,
101 Halted,
102 Blocked,
103 SwitchedOut
104 };

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