1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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102 // Typedefs from the Impl here.
103 typedef typename Impl::CPUPol CPUPolicy;
104 typedef typename Impl::DynInstPtr DynInstPtr;
105 typedef typename Impl::O3CPU O3CPU;
106
107 using VecElem = TheISA::VecElem;
108 using VecRegContainer = TheISA::VecRegContainer;
109
110 typedef O3ThreadState<Impl> ImplState;
111 typedef O3ThreadState<Impl> Thread;
112
113 typedef typename std::list<DynInstPtr>::iterator ListIt;
114
115 friend class O3ThreadContext<Impl>;
116
117 public:

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452 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
453 {
454 vecRegfileWrites++;
455 return regFile.setVecLane(phys_reg, val);
456 }
457
458 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
459
460 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
461
462 void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
463
464 void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val);
465
466 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
467
468 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
469
470 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
471
472 RegVal readArchIntReg(int reg_idx, ThreadID tid);
473
474 RegVal readArchFloatRegBits(int reg_idx, ThreadID tid);
475
476 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
477 /** Read architectural vector register for modification. */

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496 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
497 RegId(VecRegClass, reg_idx));
498 setVecLane(phys_reg, val);
499 }
500
501 const VecElem& readArchVecElem(const RegIndex& reg_idx,
502 const ElemIndex& ldx, ThreadID tid) const;
503
504 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
505
506 /** Architectural register accessors. Looks up in the commit
507 * rename table to obtain the true physical index of the
508 * architected register first, then accesses that physical
509 * register.
510 */
511 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
512
513 void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid);
514
515 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
516
517 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
518 const VecElem& val, ThreadID tid);
519
520 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
521
522 /** Sets the commit PC state of a specific thread. */

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800 Stats::Scalar intRegfileReads;
801 Stats::Scalar intRegfileWrites;
802 //number of float register file accesses
803 Stats::Scalar fpRegfileReads;
804 Stats::Scalar fpRegfileWrites;
805 //number of vector register file accesses
806 mutable Stats::Scalar vecRegfileReads;
807 Stats::Scalar vecRegfileWrites;
808 //number of CC register file accesses
809 Stats::Scalar ccRegfileReads;
810 Stats::Scalar ccRegfileWrites;
811 //number of misc
812 Stats::Scalar miscRegfileReads;
813 Stats::Scalar miscRegfileWrites;
814};
815
816#endif // __CPU_O3_CPU_HH__