1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/types.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"

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98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:

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412 ThreadID tid);
413
414 uint64_t readIntReg(PhysRegIdPtr phys_reg);
415
416 TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg);
417
418 TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
419
420 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
421
422 void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
423
424 void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val);
425
426 void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
427
428 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
429
430 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
431
432 float readArchFloatReg(int reg_idx, ThreadID tid);
433
434 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
435
436 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
437
438 /** Architectural register accessors. Looks up in the commit
439 * rename table to obtain the true physical index of the
440 * architected register first, then accesses that physical
441 * register.
442 */
443 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
444
445 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
446
447 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
448
449 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
450
451 /** Sets the commit PC state of a specific thread. */
452 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
453
454 /** Reads the commit PC state of a specific thread. */
455 TheISA::PCState pcState(ThreadID tid);
456

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535 typename CPUPolicy::Rename rename;
536
537 /** The issue/execute/writeback stages. */
538 typename CPUPolicy::IEW iew;
539
540 /** The commit stage. */
541 typename CPUPolicy::Commit commit;
542
543 /** The register file. */
544 PhysRegFile regFile;
545
546 /** The free list. */
547 typename CPUPolicy::FreeList freeList;
548
549 /** The rename map. */
550 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];

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717 Stats::Formula totalIpc;
718
719 //number of integer register file accesses
720 Stats::Scalar intRegfileReads;
721 Stats::Scalar intRegfileWrites;
722 //number of float register file accesses
723 Stats::Scalar fpRegfileReads;
724 Stats::Scalar fpRegfileWrites;
725 //number of CC register file accesses
726 Stats::Scalar ccRegfileReads;
727 Stats::Scalar ccRegfileWrites;
728 //number of misc
729 Stats::Scalar miscRegfileReads;
730 Stats::Scalar miscRegfileWrites;
731};
732
733#endif // __CPU_O3_CPU_HH__