1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/types.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"
64#include "cpu/base.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/timebuf.hh"
67//#include "cpu/o3/thread_context.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/process.hh"
70
71template <class>
72class Checker;
73class ThreadContext;
74template <class>
75class O3ThreadContext;
76
77class Checkpoint;
78class MemObject;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:
114 enum Status {
115 Running,
116 Idle,
117 Halted,
118 Blocked,
119 SwitchedOut
120 };
121
122 TheISA::TLB * itb;
123 TheISA::TLB * dtb;
124
125 /** Overall CPU status. */
126 Status _status;
127
128 private:
129
130 /**
131 * IcachePort class for instruction fetch.
132 */
133 class IcachePort : public MasterPort
134 {
135 protected:
136 /** Pointer to fetch. */
137 DefaultFetch<Impl> *fetch;
138
139 public:
140 /** Default constructor. */
141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
143 { }
144
145 protected:
146
147 /** Timing version of receive. Handles setting fetch to the
148 * proper status to start fetching. */
149 virtual bool recvTimingResp(PacketPtr pkt);
150 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
151
152 /** Handles doing a retry of a failed fetch. */
153 virtual void recvRetry();
154 };
155
156 /**
157 * DcachePort class for the load/store queue.
158 */
159 class DcachePort : public MasterPort
160 {
161 protected:
162
163 /** Pointer to LSQ. */
164 LSQ<Impl> *lsq;
165
166 public:
167 /** Default constructor. */
168 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
169 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
170 { }
171
172 protected:
173
174 /** Timing version of receive. Handles writing back and
175 * completing the load or store that has returned from
176 * memory. */
177 virtual bool recvTimingResp(PacketPtr pkt);
178 virtual void recvTimingSnoopReq(PacketPtr pkt);
179
180 virtual void recvFunctionalSnoop(PacketPtr pkt)
181 {
182 // @todo: Is there a need for potential invalidation here?
183 }
184
185 /** Handles doing a retry of the previous send. */
186 virtual void recvRetry();
187
188 /**
189 * As this CPU requires snooping to maintain the load store queue
190 * change the behaviour from the base CPU port.
191 *
192 * @return true since we have to snoop
193 */
194 virtual bool isSnooping() const { return true; }
195 };
196
197 class TickEvent : public Event
198 {
199 private:
200 /** Pointer to the CPU. */
201 FullO3CPU<Impl> *cpu;
202
203 public:
204 /** Constructs a tick event. */
205 TickEvent(FullO3CPU<Impl> *c);
206
207 /** Processes a tick event, calling tick() on the CPU. */
208 void process();
209 /** Returns the description of the tick event. */
210 const char *description() const;
211 };
212
213 /** The tick event used for scheduling CPU ticks. */
214 TickEvent tickEvent;
215
216 /** Schedule tick event, regardless of its current state. */
217 void scheduleTickEvent(Cycles delay)
218 {
219 if (tickEvent.squashed())
220 reschedule(tickEvent, clockEdge(delay));
221 else if (!tickEvent.scheduled())
222 schedule(tickEvent, clockEdge(delay));
223 }
224
225 /** Unschedule tick event, regardless of its current state. */
226 void unscheduleTickEvent()
227 {
228 if (tickEvent.scheduled())
229 tickEvent.squash();
230 }
231
232 class ActivateThreadEvent : public Event
233 {
234 private:
235 /** Number of Thread to Activate */
236 ThreadID tid;
237
238 /** Pointer to the CPU. */
239 FullO3CPU<Impl> *cpu;
240
241 public:
242 /** Constructs the event. */
243 ActivateThreadEvent();
244
245 /** Initialize Event */
246 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
247
248 /** Processes the event, calling activateThread() on the CPU. */
249 void process();
250
251 /** Returns the description of the event. */
252 const char *description() const;
253 };
254
255 /** Schedule thread to activate , regardless of its current state. */
256 void
257 scheduleActivateThreadEvent(ThreadID tid, Cycles delay)
258 {
259 // Schedule thread to activate, regardless of its current state.
260 if (activateThreadEvent[tid].squashed())
261 reschedule(activateThreadEvent[tid],
262 clockEdge(delay));
263 else if (!activateThreadEvent[tid].scheduled()) {
264 Tick when = clockEdge(delay);
265
266 // Check if the deallocateEvent is also scheduled, and make
267 // sure they do not happen at same time causing a sleep that
268 // is never woken from.
269 if (deallocateContextEvent[tid].scheduled() &&
270 deallocateContextEvent[tid].when() == when) {
271 when++;
272 }
273
274 schedule(activateThreadEvent[tid], when);
275 }
276 }
277
278 /** Unschedule actiavte thread event, regardless of its current state. */
279 void
280 unscheduleActivateThreadEvent(ThreadID tid)
281 {
282 if (activateThreadEvent[tid].scheduled())
283 activateThreadEvent[tid].squash();
284 }
285
286 /** The tick event used for scheduling CPU ticks. */
287 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
288
289 class DeallocateContextEvent : public Event
290 {
291 private:
292 /** Number of Thread to deactivate */
293 ThreadID tid;
294
295 /** Should the thread be removed from the CPU? */
296 bool remove;
297
298 /** Pointer to the CPU. */
299 FullO3CPU<Impl> *cpu;
300
301 public:
302 /** Constructs the event. */
303 DeallocateContextEvent();
304
305 /** Initialize Event */
306 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
307
308 /** Processes the event, calling activateThread() on the CPU. */
309 void process();
310
311 /** Sets whether the thread should also be removed from the CPU. */
312 void setRemove(bool _remove) { remove = _remove; }
313
314 /** Returns the description of the event. */
315 const char *description() const;
316 };
317
318 /** Schedule cpu to deallocate thread context.*/
319 void
320 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay)
321 {
322 // Schedule thread to activate, regardless of its current state.
323 if (deallocateContextEvent[tid].squashed())
324 reschedule(deallocateContextEvent[tid],
325 clockEdge(delay));
326 else if (!deallocateContextEvent[tid].scheduled())
327 schedule(deallocateContextEvent[tid],
328 clockEdge(delay));
329 }
330
331 /** Unschedule thread deallocation in CPU */
332 void
333 unscheduleDeallocateContextEvent(ThreadID tid)
334 {
335 if (deallocateContextEvent[tid].scheduled())
336 deallocateContextEvent[tid].squash();
337 }
338
339 /** The tick event used for scheduling CPU ticks. */
340 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
341
342 /**
343 * Check if the pipeline has drained and signal the DrainManager.
344 *
345 * This method checks if a drain has been requested and if the CPU
346 * has drained successfully (i.e., there are no instructions in
347 * the pipeline). If the CPU has drained, it deschedules the tick
348 * event and signals the drain manager.
349 *
350 * @return False if a drain hasn't been requested or the CPU
351 * hasn't drained, true otherwise.
352 */
353 bool tryDrain();
354
355 /**
356 * Perform sanity checks after a drain.
357 *
358 * This method is called from drain() when it has determined that
359 * the CPU is fully drained when gem5 is compiled with the NDEBUG
360 * macro undefined. The intention of this method is to do more
361 * extensive tests than the isDrained() method to weed out any
362 * draining bugs.
363 */
364 void drainSanityCheck() const;
365
366 /** Check if a system is in a drained state. */
367 bool isDrained() const;
368
369 public:
370 /** Constructs a CPU with the given parameters. */
371 FullO3CPU(DerivO3CPUParams *params);
372 /** Destructor. */
373 ~FullO3CPU();
374
375 /** Registers statistics. */
376 void regStats();
377
378 void demapPage(Addr vaddr, uint64_t asn)
379 {
380 this->itb->demapPage(vaddr, asn);
381 this->dtb->demapPage(vaddr, asn);
382 }
383
384 void demapInstPage(Addr vaddr, uint64_t asn)
385 {
386 this->itb->demapPage(vaddr, asn);
387 }
388
389 void demapDataPage(Addr vaddr, uint64_t asn)
390 {
391 this->dtb->demapPage(vaddr, asn);
392 }
393
394 /** Ticks CPU, calling tick() on each stage, and checking the overall
395 * activity to see if the CPU should deschedule itself.
396 */
397 void tick();
398
399 /** Initialize the CPU */
400 void init();
401
402 void startup();
403
404 /** Returns the Number of Active Threads in the CPU */
405 int numActiveThreads()
406 { return activeThreads.size(); }
407
408 /** Add Thread to Active Threads List */
409 void activateThread(ThreadID tid);
410
411 /** Remove Thread from Active Threads List */
412 void deactivateThread(ThreadID tid);
413
414 /** Setup CPU to insert a thread's context */
415 void insertThread(ThreadID tid);
416
417 /** Remove all of a thread's context from CPU */
418 void removeThread(ThreadID tid);
419
420 /** Count the Total Instructions Committed in the CPU. */
421 virtual Counter totalInsts() const;
422
423 /** Count the Total Ops (including micro ops) committed in the CPU. */
424 virtual Counter totalOps() const;
425
426 /** Add Thread to Active Threads List. */
427 void activateContext(ThreadID tid, Cycles delay);
428
429 /** Remove Thread from Active Threads List */
430 void suspendContext(ThreadID tid);
431
432 /** Remove Thread from Active Threads List &&
433 * Possibly Remove Thread Context from CPU.
434 */
435 bool scheduleDeallocateContext(ThreadID tid, bool remove,
436 Cycles delay = Cycles(1));
437
438 /** Remove Thread from Active Threads List &&
439 * Remove Thread Context from CPU.
440 */
441 void haltContext(ThreadID tid);
442
443 /** Activate a Thread When CPU Resources are Available. */
444 void activateWhenReady(ThreadID tid);
445
446 /** Add or Remove a Thread Context in the CPU. */
447 void doContextSwitch();
448
449 /** Update The Order In Which We Process Threads. */
450 void updateThreadPriority();
451
452 /** Is the CPU draining? */
453 bool isDraining() const { return getDrainState() == Drainable::Draining; }
454
455 void serializeThread(std::ostream &os, ThreadID tid);
456
457 void unserializeThread(Checkpoint *cp, const std::string §ion,
458 ThreadID tid);
459
460 public:
461 /** Executes a syscall.
462 * @todo: Determine if this needs to be virtual.
463 */
464 void syscall(int64_t callnum, ThreadID tid);
465
466 /** Starts draining the CPU's pipeline of all instructions in
467 * order to stop all memory accesses. */
468 unsigned int drain(DrainManager *drain_manager);
469
470 /** Resumes execution after a drain. */
471 void drainResume();
472
473 /**
474 * Commit has reached a safe point to drain a thread.
475 *
476 * Commit calls this method to inform the pipeline that it has
477 * reached a point where it is not executed microcode and is about
478 * to squash uncommitted instructions to fully drain the pipeline.
479 */
480 void commitDrained(ThreadID tid);
481
482 /** Switches out this CPU. */
483 virtual void switchOut();
484
485 /** Takes over from another CPU. */
486 virtual void takeOverFrom(BaseCPU *oldCPU);
487
488 void verifyMemoryMode() const;
489
490 /** Get the current instruction sequence number, and increment it. */
491 InstSeqNum getAndIncrementInstSeq()
492 { return globalSeqNum++; }
493
494 /** Traps to handle given fault. */
495 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
496
497 /** HW return from error interrupt. */
498 Fault hwrei(ThreadID tid);
499
500 bool simPalCheck(int palFunc, ThreadID tid);
501
502 /** Returns the Fault for any valid interrupt. */
503 Fault getInterrupts();
504
505 /** Processes any an interrupt fault. */
506 void processInterrupts(Fault interrupt);
507
508 /** Halts the CPU. */
509 void halt() { panic("Halt not implemented!\n"); }
510
511 /** Check if this address is a valid instruction address. */
512 bool validInstAddr(Addr addr) { return true; }
513
514 /** Check if this address is a valid data address. */
515 bool validDataAddr(Addr addr) { return true; }
516
517 /** Register accessors. Index refers to the physical register index. */
518
519 /** Reads a miscellaneous register. */
520 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
521
522 /** Reads a misc. register, including any side effects the read
523 * might have as defined by the architecture.
524 */
525 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
526
527 /** Sets a miscellaneous register. */
528 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
529 ThreadID tid);
530
531 /** Sets a misc. register, including any side effects the write
532 * might have as defined by the architecture.
533 */
534 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
535 ThreadID tid);
536
537 uint64_t readIntReg(int reg_idx);
538
539 TheISA::FloatReg readFloatReg(int reg_idx);
540
541 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
542
543 void setIntReg(int reg_idx, uint64_t val);
544
545 void setFloatReg(int reg_idx, TheISA::FloatReg val);
546
547 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
548
549 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
550
551 float readArchFloatReg(int reg_idx, ThreadID tid);
552
553 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
554
555 /** Architectural register accessors. Looks up in the commit
556 * rename table to obtain the true physical index of the
557 * architected register first, then accesses that physical
558 * register.
559 */
560 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
561
562 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
563
564 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
565
566 /** Sets the commit PC state of a specific thread. */
567 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
568
569 /** Reads the commit PC state of a specific thread. */
570 TheISA::PCState pcState(ThreadID tid);
571
572 /** Reads the commit PC of a specific thread. */
573 Addr instAddr(ThreadID tid);
574
575 /** Reads the commit micro PC of a specific thread. */
576 MicroPC microPC(ThreadID tid);
577
578 /** Reads the next PC of a specific thread. */
579 Addr nextInstAddr(ThreadID tid);
580
581 /** Initiates a squash of all in-flight instructions for a given
582 * thread. The source of the squash is an external update of
583 * state through the TC.
584 */
585 void squashFromTC(ThreadID tid);
586
587 /** Function to add instruction onto the head of the list of the
588 * instructions. Used when new instructions are fetched.
589 */
590 ListIt addInst(DynInstPtr &inst);
591
592 /** Function to tell the CPU that an instruction has completed. */
593 void instDone(ThreadID tid, DynInstPtr &inst);
594
595 /** Remove an instruction from the front end of the list. There's
596 * no restriction on location of the instruction.
597 */
598 void removeFrontInst(DynInstPtr &inst);
599
600 /** Remove all instructions that are not currently in the ROB.
601 * There's also an option to not squash delay slot instructions.*/
602 void removeInstsNotInROB(ThreadID tid);
603
604 /** Remove all instructions younger than the given sequence number. */
605 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
606
607 /** Removes the instruction pointed to by the iterator. */
608 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
609
610 /** Cleans up all instructions on the remove list. */
611 void cleanUpRemovedInsts();
612
613 /** Debug function to print all instructions on the list. */
614 void dumpInsts();
615
616 public:
617#ifndef NDEBUG
618 /** Count of total number of dynamic instructions in flight. */
619 int instcount;
620#endif
621
622 /** List of all the instructions in flight. */
623 std::list<DynInstPtr> instList;
624
625 /** List of all the instructions that will be removed at the end of this
626 * cycle.
627 */
628 std::queue<ListIt> removeList;
629
630#ifdef DEBUG
631 /** Debug structure to keep track of the sequence numbers still in
632 * flight.
633 */
634 std::set<InstSeqNum> snList;
635#endif
636
637 /** Records if instructions need to be removed this cycle due to
638 * being retired or squashed.
639 */
640 bool removeInstsThisCycle;
641
642 protected:
643 /** The fetch stage. */
644 typename CPUPolicy::Fetch fetch;
645
646 /** The decode stage. */
647 typename CPUPolicy::Decode decode;
648
649 /** The dispatch stage. */
650 typename CPUPolicy::Rename rename;
651
652 /** The issue/execute/writeback stages. */
653 typename CPUPolicy::IEW iew;
654
655 /** The commit stage. */
656 typename CPUPolicy::Commit commit;
657
658 /** The register file. */
659 PhysRegFile regFile;
660
661 /** The free list. */
662 typename CPUPolicy::FreeList freeList;
663
664 /** The rename map. */
665 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
666
667 /** The commit rename map. */
668 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
669
670 /** The re-order buffer. */
671 typename CPUPolicy::ROB rob;
672
673 /** Active Threads List */
674 std::list<ThreadID> activeThreads;
675
676 /** Integer Register Scoreboard */
677 Scoreboard scoreboard;
678
679 std::vector<TheISA::ISA *> isa;
680
681 /** Instruction port. Note that it has to appear after the fetch stage. */
682 IcachePort icachePort;
683
684 /** Data port. Note that it has to appear after the iew stages */
685 DcachePort dcachePort;
686
687 public:
688 /** Enum to give each stage a specific index, so when calling
689 * activateStage() or deactivateStage(), they can specify which stage
690 * is being activated/deactivated.
691 */
692 enum StageIdx {
693 FetchIdx,
694 DecodeIdx,
695 RenameIdx,
696 IEWIdx,
697 CommitIdx,
698 NumStages };
699
700 /** Typedefs from the Impl to get the structs that each of the
701 * time buffers should use.
702 */
703 typedef typename CPUPolicy::TimeStruct TimeStruct;
704
705 typedef typename CPUPolicy::FetchStruct FetchStruct;
706
707 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
708
709 typedef typename CPUPolicy::RenameStruct RenameStruct;
710
711 typedef typename CPUPolicy::IEWStruct IEWStruct;
712
713 /** The main time buffer to do backwards communication. */
714 TimeBuffer<TimeStruct> timeBuffer;
715
716 /** The fetch stage's instruction queue. */
717 TimeBuffer<FetchStruct> fetchQueue;
718
719 /** The decode stage's instruction queue. */
720 TimeBuffer<DecodeStruct> decodeQueue;
721
722 /** The rename stage's instruction queue. */
723 TimeBuffer<RenameStruct> renameQueue;
724
725 /** The IEW stage's instruction queue. */
726 TimeBuffer<IEWStruct> iewQueue;
727
728 private:
729 /** The activity recorder; used to tell if the CPU has any
730 * activity remaining or if it can go to idle and deschedule
731 * itself.
732 */
733 ActivityRecorder activityRec;
734
735 public:
736 /** Records that there was time buffer activity this cycle. */
737 void activityThisCycle() { activityRec.activity(); }
738
739 /** Changes a stage's status to active within the activity recorder. */
740 void activateStage(const StageIdx idx)
741 { activityRec.activateStage(idx); }
742
743 /** Changes a stage's status to inactive within the activity recorder. */
744 void deactivateStage(const StageIdx idx)
745 { activityRec.deactivateStage(idx); }
746
747 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
748 void wakeCPU();
749
750 virtual void wakeup();
751
752 /** Gets a free thread id. Use if thread ids change across system. */
753 ThreadID getFreeTid();
754
755 public:
756 /** Returns a pointer to a thread context. */
757 ThreadContext *
758 tcBase(ThreadID tid)
759 {
760 return thread[tid]->getTC();
761 }
762
763 /** The global sequence number counter. */
764 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
765
766 /** Pointer to the checker, which can dynamically verify
767 * instruction results at run time. This can be set to NULL if it
768 * is not being used.
769 */
770 Checker<Impl> *checker;
771
772 /** Pointer to the system. */
773 System *system;
774
775 /** DrainManager to notify when draining has completed. */
776 DrainManager *drainManager;
777
778 /** Pointers to all of the threads in the CPU. */
779 std::vector<Thread *> thread;
780
781 /** Is there a context switch pending? */
782 bool contextSwitch;
783
784 /** Threads Scheduled to Enter CPU */
785 std::list<int> cpuWaitList;
786
787 /** The cycle that the CPU was last running, used for statistics. */
788 Cycles lastRunningCycle;
789
790 /** The cycle that the CPU was last activated by a new thread*/
791 Tick lastActivatedCycle;
792
793 /** Mapping for system thread id to cpu id */
794 std::map<ThreadID, unsigned> threadMap;
795
796 /** Available thread ids in the cpu*/
797 std::vector<ThreadID> tids;
798
799 /** CPU read function, forwards read to LSQ. */
800 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
801 uint8_t *data, int load_idx)
802 {
803 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
804 data, load_idx);
805 }
806
807 /** CPU write function, forwards write to LSQ. */
808 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
809 uint8_t *data, int store_idx)
810 {
811 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
812 data, store_idx);
813 }
814
815 /** Used by the fetch unit to get a hold of the instruction port. */
816 virtual MasterPort &getInstPort() { return icachePort; }
817
818 /** Get the dcache port (used to find block size for translations). */
819 virtual MasterPort &getDataPort() { return dcachePort; }
820
821 /** Stat for total number of times the CPU is descheduled. */
822 Stats::Scalar timesIdled;
823 /** Stat for total number of cycles the CPU spends descheduled. */
824 Stats::Scalar idleCycles;
825 /** Stat for total number of cycles the CPU spends descheduled due to a
826 * quiesce operation or waiting for an interrupt. */
827 Stats::Scalar quiesceCycles;
828 /** Stat for the number of committed instructions per thread. */
829 Stats::Vector committedInsts;
830 /** Stat for the number of committed ops (including micro ops) per thread. */
831 Stats::Vector committedOps;
832 /** Stat for the total number of committed instructions. */
833 Stats::Scalar totalCommittedInsts;
834 /** Stat for the CPI per thread. */
835 Stats::Formula cpi;
836 /** Stat for the total CPI. */
837 Stats::Formula totalCpi;
838 /** Stat for the IPC per thread. */
839 Stats::Formula ipc;
840 /** Stat for the total IPC. */
841 Stats::Formula totalIpc;
842
843 //number of integer register file accesses
844 Stats::Scalar intRegfileReads;
845 Stats::Scalar intRegfileWrites;
846 //number of float register file accesses
847 Stats::Scalar fpRegfileReads;
848 Stats::Scalar fpRegfileWrites;
849 //number of misc
850 Stats::Scalar miscRegfileReads;
851 Stats::Scalar miscRegfileWrites;
852};
853
854#endif // __CPU_O3_CPU_HH__
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/types.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"
64#include "cpu/base.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/timebuf.hh"
67//#include "cpu/o3/thread_context.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/process.hh"
70
71template <class>
72class Checker;
73class ThreadContext;
74template <class>
75class O3ThreadContext;
76
77class Checkpoint;
78class MemObject;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:
114 enum Status {
115 Running,
116 Idle,
117 Halted,
118 Blocked,
119 SwitchedOut
120 };
121
122 TheISA::TLB * itb;
123 TheISA::TLB * dtb;
124
125 /** Overall CPU status. */
126 Status _status;
127
128 private:
129
130 /**
131 * IcachePort class for instruction fetch.
132 */
133 class IcachePort : public MasterPort
134 {
135 protected:
136 /** Pointer to fetch. */
137 DefaultFetch<Impl> *fetch;
138
139 public:
140 /** Default constructor. */
141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
143 { }
144
145 protected:
146
147 /** Timing version of receive. Handles setting fetch to the
148 * proper status to start fetching. */
149 virtual bool recvTimingResp(PacketPtr pkt);
150 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
151
152 /** Handles doing a retry of a failed fetch. */
153 virtual void recvRetry();
154 };
155
156 /**
157 * DcachePort class for the load/store queue.
158 */
159 class DcachePort : public MasterPort
160 {
161 protected:
162
163 /** Pointer to LSQ. */
164 LSQ<Impl> *lsq;
165
166 public:
167 /** Default constructor. */
168 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
169 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
170 { }
171
172 protected:
173
174 /** Timing version of receive. Handles writing back and
175 * completing the load or store that has returned from
176 * memory. */
177 virtual bool recvTimingResp(PacketPtr pkt);
178 virtual void recvTimingSnoopReq(PacketPtr pkt);
179
180 virtual void recvFunctionalSnoop(PacketPtr pkt)
181 {
182 // @todo: Is there a need for potential invalidation here?
183 }
184
185 /** Handles doing a retry of the previous send. */
186 virtual void recvRetry();
187
188 /**
189 * As this CPU requires snooping to maintain the load store queue
190 * change the behaviour from the base CPU port.
191 *
192 * @return true since we have to snoop
193 */
194 virtual bool isSnooping() const { return true; }
195 };
196
197 class TickEvent : public Event
198 {
199 private:
200 /** Pointer to the CPU. */
201 FullO3CPU<Impl> *cpu;
202
203 public:
204 /** Constructs a tick event. */
205 TickEvent(FullO3CPU<Impl> *c);
206
207 /** Processes a tick event, calling tick() on the CPU. */
208 void process();
209 /** Returns the description of the tick event. */
210 const char *description() const;
211 };
212
213 /** The tick event used for scheduling CPU ticks. */
214 TickEvent tickEvent;
215
216 /** Schedule tick event, regardless of its current state. */
217 void scheduleTickEvent(Cycles delay)
218 {
219 if (tickEvent.squashed())
220 reschedule(tickEvent, clockEdge(delay));
221 else if (!tickEvent.scheduled())
222 schedule(tickEvent, clockEdge(delay));
223 }
224
225 /** Unschedule tick event, regardless of its current state. */
226 void unscheduleTickEvent()
227 {
228 if (tickEvent.scheduled())
229 tickEvent.squash();
230 }
231
232 class ActivateThreadEvent : public Event
233 {
234 private:
235 /** Number of Thread to Activate */
236 ThreadID tid;
237
238 /** Pointer to the CPU. */
239 FullO3CPU<Impl> *cpu;
240
241 public:
242 /** Constructs the event. */
243 ActivateThreadEvent();
244
245 /** Initialize Event */
246 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
247
248 /** Processes the event, calling activateThread() on the CPU. */
249 void process();
250
251 /** Returns the description of the event. */
252 const char *description() const;
253 };
254
255 /** Schedule thread to activate , regardless of its current state. */
256 void
257 scheduleActivateThreadEvent(ThreadID tid, Cycles delay)
258 {
259 // Schedule thread to activate, regardless of its current state.
260 if (activateThreadEvent[tid].squashed())
261 reschedule(activateThreadEvent[tid],
262 clockEdge(delay));
263 else if (!activateThreadEvent[tid].scheduled()) {
264 Tick when = clockEdge(delay);
265
266 // Check if the deallocateEvent is also scheduled, and make
267 // sure they do not happen at same time causing a sleep that
268 // is never woken from.
269 if (deallocateContextEvent[tid].scheduled() &&
270 deallocateContextEvent[tid].when() == when) {
271 when++;
272 }
273
274 schedule(activateThreadEvent[tid], when);
275 }
276 }
277
278 /** Unschedule actiavte thread event, regardless of its current state. */
279 void
280 unscheduleActivateThreadEvent(ThreadID tid)
281 {
282 if (activateThreadEvent[tid].scheduled())
283 activateThreadEvent[tid].squash();
284 }
285
286 /** The tick event used for scheduling CPU ticks. */
287 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
288
289 class DeallocateContextEvent : public Event
290 {
291 private:
292 /** Number of Thread to deactivate */
293 ThreadID tid;
294
295 /** Should the thread be removed from the CPU? */
296 bool remove;
297
298 /** Pointer to the CPU. */
299 FullO3CPU<Impl> *cpu;
300
301 public:
302 /** Constructs the event. */
303 DeallocateContextEvent();
304
305 /** Initialize Event */
306 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
307
308 /** Processes the event, calling activateThread() on the CPU. */
309 void process();
310
311 /** Sets whether the thread should also be removed from the CPU. */
312 void setRemove(bool _remove) { remove = _remove; }
313
314 /** Returns the description of the event. */
315 const char *description() const;
316 };
317
318 /** Schedule cpu to deallocate thread context.*/
319 void
320 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay)
321 {
322 // Schedule thread to activate, regardless of its current state.
323 if (deallocateContextEvent[tid].squashed())
324 reschedule(deallocateContextEvent[tid],
325 clockEdge(delay));
326 else if (!deallocateContextEvent[tid].scheduled())
327 schedule(deallocateContextEvent[tid],
328 clockEdge(delay));
329 }
330
331 /** Unschedule thread deallocation in CPU */
332 void
333 unscheduleDeallocateContextEvent(ThreadID tid)
334 {
335 if (deallocateContextEvent[tid].scheduled())
336 deallocateContextEvent[tid].squash();
337 }
338
339 /** The tick event used for scheduling CPU ticks. */
340 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
341
342 /**
343 * Check if the pipeline has drained and signal the DrainManager.
344 *
345 * This method checks if a drain has been requested and if the CPU
346 * has drained successfully (i.e., there are no instructions in
347 * the pipeline). If the CPU has drained, it deschedules the tick
348 * event and signals the drain manager.
349 *
350 * @return False if a drain hasn't been requested or the CPU
351 * hasn't drained, true otherwise.
352 */
353 bool tryDrain();
354
355 /**
356 * Perform sanity checks after a drain.
357 *
358 * This method is called from drain() when it has determined that
359 * the CPU is fully drained when gem5 is compiled with the NDEBUG
360 * macro undefined. The intention of this method is to do more
361 * extensive tests than the isDrained() method to weed out any
362 * draining bugs.
363 */
364 void drainSanityCheck() const;
365
366 /** Check if a system is in a drained state. */
367 bool isDrained() const;
368
369 public:
370 /** Constructs a CPU with the given parameters. */
371 FullO3CPU(DerivO3CPUParams *params);
372 /** Destructor. */
373 ~FullO3CPU();
374
375 /** Registers statistics. */
376 void regStats();
377
378 void demapPage(Addr vaddr, uint64_t asn)
379 {
380 this->itb->demapPage(vaddr, asn);
381 this->dtb->demapPage(vaddr, asn);
382 }
383
384 void demapInstPage(Addr vaddr, uint64_t asn)
385 {
386 this->itb->demapPage(vaddr, asn);
387 }
388
389 void demapDataPage(Addr vaddr, uint64_t asn)
390 {
391 this->dtb->demapPage(vaddr, asn);
392 }
393
394 /** Ticks CPU, calling tick() on each stage, and checking the overall
395 * activity to see if the CPU should deschedule itself.
396 */
397 void tick();
398
399 /** Initialize the CPU */
400 void init();
401
402 void startup();
403
404 /** Returns the Number of Active Threads in the CPU */
405 int numActiveThreads()
406 { return activeThreads.size(); }
407
408 /** Add Thread to Active Threads List */
409 void activateThread(ThreadID tid);
410
411 /** Remove Thread from Active Threads List */
412 void deactivateThread(ThreadID tid);
413
414 /** Setup CPU to insert a thread's context */
415 void insertThread(ThreadID tid);
416
417 /** Remove all of a thread's context from CPU */
418 void removeThread(ThreadID tid);
419
420 /** Count the Total Instructions Committed in the CPU. */
421 virtual Counter totalInsts() const;
422
423 /** Count the Total Ops (including micro ops) committed in the CPU. */
424 virtual Counter totalOps() const;
425
426 /** Add Thread to Active Threads List. */
427 void activateContext(ThreadID tid, Cycles delay);
428
429 /** Remove Thread from Active Threads List */
430 void suspendContext(ThreadID tid);
431
432 /** Remove Thread from Active Threads List &&
433 * Possibly Remove Thread Context from CPU.
434 */
435 bool scheduleDeallocateContext(ThreadID tid, bool remove,
436 Cycles delay = Cycles(1));
437
438 /** Remove Thread from Active Threads List &&
439 * Remove Thread Context from CPU.
440 */
441 void haltContext(ThreadID tid);
442
443 /** Activate a Thread When CPU Resources are Available. */
444 void activateWhenReady(ThreadID tid);
445
446 /** Add or Remove a Thread Context in the CPU. */
447 void doContextSwitch();
448
449 /** Update The Order In Which We Process Threads. */
450 void updateThreadPriority();
451
452 /** Is the CPU draining? */
453 bool isDraining() const { return getDrainState() == Drainable::Draining; }
454
455 void serializeThread(std::ostream &os, ThreadID tid);
456
457 void unserializeThread(Checkpoint *cp, const std::string §ion,
458 ThreadID tid);
459
460 public:
461 /** Executes a syscall.
462 * @todo: Determine if this needs to be virtual.
463 */
464 void syscall(int64_t callnum, ThreadID tid);
465
466 /** Starts draining the CPU's pipeline of all instructions in
467 * order to stop all memory accesses. */
468 unsigned int drain(DrainManager *drain_manager);
469
470 /** Resumes execution after a drain. */
471 void drainResume();
472
473 /**
474 * Commit has reached a safe point to drain a thread.
475 *
476 * Commit calls this method to inform the pipeline that it has
477 * reached a point where it is not executed microcode and is about
478 * to squash uncommitted instructions to fully drain the pipeline.
479 */
480 void commitDrained(ThreadID tid);
481
482 /** Switches out this CPU. */
483 virtual void switchOut();
484
485 /** Takes over from another CPU. */
486 virtual void takeOverFrom(BaseCPU *oldCPU);
487
488 void verifyMemoryMode() const;
489
490 /** Get the current instruction sequence number, and increment it. */
491 InstSeqNum getAndIncrementInstSeq()
492 { return globalSeqNum++; }
493
494 /** Traps to handle given fault. */
495 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
496
497 /** HW return from error interrupt. */
498 Fault hwrei(ThreadID tid);
499
500 bool simPalCheck(int palFunc, ThreadID tid);
501
502 /** Returns the Fault for any valid interrupt. */
503 Fault getInterrupts();
504
505 /** Processes any an interrupt fault. */
506 void processInterrupts(Fault interrupt);
507
508 /** Halts the CPU. */
509 void halt() { panic("Halt not implemented!\n"); }
510
511 /** Check if this address is a valid instruction address. */
512 bool validInstAddr(Addr addr) { return true; }
513
514 /** Check if this address is a valid data address. */
515 bool validDataAddr(Addr addr) { return true; }
516
517 /** Register accessors. Index refers to the physical register index. */
518
519 /** Reads a miscellaneous register. */
520 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
521
522 /** Reads a misc. register, including any side effects the read
523 * might have as defined by the architecture.
524 */
525 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
526
527 /** Sets a miscellaneous register. */
528 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
529 ThreadID tid);
530
531 /** Sets a misc. register, including any side effects the write
532 * might have as defined by the architecture.
533 */
534 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
535 ThreadID tid);
536
537 uint64_t readIntReg(int reg_idx);
538
539 TheISA::FloatReg readFloatReg(int reg_idx);
540
541 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
542
543 void setIntReg(int reg_idx, uint64_t val);
544
545 void setFloatReg(int reg_idx, TheISA::FloatReg val);
546
547 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
548
549 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
550
551 float readArchFloatReg(int reg_idx, ThreadID tid);
552
553 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
554
555 /** Architectural register accessors. Looks up in the commit
556 * rename table to obtain the true physical index of the
557 * architected register first, then accesses that physical
558 * register.
559 */
560 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
561
562 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
563
564 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
565
566 /** Sets the commit PC state of a specific thread. */
567 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
568
569 /** Reads the commit PC state of a specific thread. */
570 TheISA::PCState pcState(ThreadID tid);
571
572 /** Reads the commit PC of a specific thread. */
573 Addr instAddr(ThreadID tid);
574
575 /** Reads the commit micro PC of a specific thread. */
576 MicroPC microPC(ThreadID tid);
577
578 /** Reads the next PC of a specific thread. */
579 Addr nextInstAddr(ThreadID tid);
580
581 /** Initiates a squash of all in-flight instructions for a given
582 * thread. The source of the squash is an external update of
583 * state through the TC.
584 */
585 void squashFromTC(ThreadID tid);
586
587 /** Function to add instruction onto the head of the list of the
588 * instructions. Used when new instructions are fetched.
589 */
590 ListIt addInst(DynInstPtr &inst);
591
592 /** Function to tell the CPU that an instruction has completed. */
593 void instDone(ThreadID tid, DynInstPtr &inst);
594
595 /** Remove an instruction from the front end of the list. There's
596 * no restriction on location of the instruction.
597 */
598 void removeFrontInst(DynInstPtr &inst);
599
600 /** Remove all instructions that are not currently in the ROB.
601 * There's also an option to not squash delay slot instructions.*/
602 void removeInstsNotInROB(ThreadID tid);
603
604 /** Remove all instructions younger than the given sequence number. */
605 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
606
607 /** Removes the instruction pointed to by the iterator. */
608 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
609
610 /** Cleans up all instructions on the remove list. */
611 void cleanUpRemovedInsts();
612
613 /** Debug function to print all instructions on the list. */
614 void dumpInsts();
615
616 public:
617#ifndef NDEBUG
618 /** Count of total number of dynamic instructions in flight. */
619 int instcount;
620#endif
621
622 /** List of all the instructions in flight. */
623 std::list<DynInstPtr> instList;
624
625 /** List of all the instructions that will be removed at the end of this
626 * cycle.
627 */
628 std::queue<ListIt> removeList;
629
630#ifdef DEBUG
631 /** Debug structure to keep track of the sequence numbers still in
632 * flight.
633 */
634 std::set<InstSeqNum> snList;
635#endif
636
637 /** Records if instructions need to be removed this cycle due to
638 * being retired or squashed.
639 */
640 bool removeInstsThisCycle;
641
642 protected:
643 /** The fetch stage. */
644 typename CPUPolicy::Fetch fetch;
645
646 /** The decode stage. */
647 typename CPUPolicy::Decode decode;
648
649 /** The dispatch stage. */
650 typename CPUPolicy::Rename rename;
651
652 /** The issue/execute/writeback stages. */
653 typename CPUPolicy::IEW iew;
654
655 /** The commit stage. */
656 typename CPUPolicy::Commit commit;
657
658 /** The register file. */
659 PhysRegFile regFile;
660
661 /** The free list. */
662 typename CPUPolicy::FreeList freeList;
663
664 /** The rename map. */
665 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
666
667 /** The commit rename map. */
668 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
669
670 /** The re-order buffer. */
671 typename CPUPolicy::ROB rob;
672
673 /** Active Threads List */
674 std::list<ThreadID> activeThreads;
675
676 /** Integer Register Scoreboard */
677 Scoreboard scoreboard;
678
679 std::vector<TheISA::ISA *> isa;
680
681 /** Instruction port. Note that it has to appear after the fetch stage. */
682 IcachePort icachePort;
683
684 /** Data port. Note that it has to appear after the iew stages */
685 DcachePort dcachePort;
686
687 public:
688 /** Enum to give each stage a specific index, so when calling
689 * activateStage() or deactivateStage(), they can specify which stage
690 * is being activated/deactivated.
691 */
692 enum StageIdx {
693 FetchIdx,
694 DecodeIdx,
695 RenameIdx,
696 IEWIdx,
697 CommitIdx,
698 NumStages };
699
700 /** Typedefs from the Impl to get the structs that each of the
701 * time buffers should use.
702 */
703 typedef typename CPUPolicy::TimeStruct TimeStruct;
704
705 typedef typename CPUPolicy::FetchStruct FetchStruct;
706
707 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
708
709 typedef typename CPUPolicy::RenameStruct RenameStruct;
710
711 typedef typename CPUPolicy::IEWStruct IEWStruct;
712
713 /** The main time buffer to do backwards communication. */
714 TimeBuffer<TimeStruct> timeBuffer;
715
716 /** The fetch stage's instruction queue. */
717 TimeBuffer<FetchStruct> fetchQueue;
718
719 /** The decode stage's instruction queue. */
720 TimeBuffer<DecodeStruct> decodeQueue;
721
722 /** The rename stage's instruction queue. */
723 TimeBuffer<RenameStruct> renameQueue;
724
725 /** The IEW stage's instruction queue. */
726 TimeBuffer<IEWStruct> iewQueue;
727
728 private:
729 /** The activity recorder; used to tell if the CPU has any
730 * activity remaining or if it can go to idle and deschedule
731 * itself.
732 */
733 ActivityRecorder activityRec;
734
735 public:
736 /** Records that there was time buffer activity this cycle. */
737 void activityThisCycle() { activityRec.activity(); }
738
739 /** Changes a stage's status to active within the activity recorder. */
740 void activateStage(const StageIdx idx)
741 { activityRec.activateStage(idx); }
742
743 /** Changes a stage's status to inactive within the activity recorder. */
744 void deactivateStage(const StageIdx idx)
745 { activityRec.deactivateStage(idx); }
746
747 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
748 void wakeCPU();
749
750 virtual void wakeup();
751
752 /** Gets a free thread id. Use if thread ids change across system. */
753 ThreadID getFreeTid();
754
755 public:
756 /** Returns a pointer to a thread context. */
757 ThreadContext *
758 tcBase(ThreadID tid)
759 {
760 return thread[tid]->getTC();
761 }
762
763 /** The global sequence number counter. */
764 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
765
766 /** Pointer to the checker, which can dynamically verify
767 * instruction results at run time. This can be set to NULL if it
768 * is not being used.
769 */
770 Checker<Impl> *checker;
771
772 /** Pointer to the system. */
773 System *system;
774
775 /** DrainManager to notify when draining has completed. */
776 DrainManager *drainManager;
777
778 /** Pointers to all of the threads in the CPU. */
779 std::vector<Thread *> thread;
780
781 /** Is there a context switch pending? */
782 bool contextSwitch;
783
784 /** Threads Scheduled to Enter CPU */
785 std::list<int> cpuWaitList;
786
787 /** The cycle that the CPU was last running, used for statistics. */
788 Cycles lastRunningCycle;
789
790 /** The cycle that the CPU was last activated by a new thread*/
791 Tick lastActivatedCycle;
792
793 /** Mapping for system thread id to cpu id */
794 std::map<ThreadID, unsigned> threadMap;
795
796 /** Available thread ids in the cpu*/
797 std::vector<ThreadID> tids;
798
799 /** CPU read function, forwards read to LSQ. */
800 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
801 uint8_t *data, int load_idx)
802 {
803 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
804 data, load_idx);
805 }
806
807 /** CPU write function, forwards write to LSQ. */
808 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
809 uint8_t *data, int store_idx)
810 {
811 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
812 data, store_idx);
813 }
814
815 /** Used by the fetch unit to get a hold of the instruction port. */
816 virtual MasterPort &getInstPort() { return icachePort; }
817
818 /** Get the dcache port (used to find block size for translations). */
819 virtual MasterPort &getDataPort() { return dcachePort; }
820
821 /** Stat for total number of times the CPU is descheduled. */
822 Stats::Scalar timesIdled;
823 /** Stat for total number of cycles the CPU spends descheduled. */
824 Stats::Scalar idleCycles;
825 /** Stat for total number of cycles the CPU spends descheduled due to a
826 * quiesce operation or waiting for an interrupt. */
827 Stats::Scalar quiesceCycles;
828 /** Stat for the number of committed instructions per thread. */
829 Stats::Vector committedInsts;
830 /** Stat for the number of committed ops (including micro ops) per thread. */
831 Stats::Vector committedOps;
832 /** Stat for the total number of committed instructions. */
833 Stats::Scalar totalCommittedInsts;
834 /** Stat for the CPI per thread. */
835 Stats::Formula cpi;
836 /** Stat for the total CPI. */
837 Stats::Formula totalCpi;
838 /** Stat for the IPC per thread. */
839 Stats::Formula ipc;
840 /** Stat for the total IPC. */
841 Stats::Formula totalIpc;
842
843 //number of integer register file accesses
844 Stats::Scalar intRegfileReads;
845 Stats::Scalar intRegfileWrites;
846 //number of float register file accesses
847 Stats::Scalar fpRegfileReads;
848 Stats::Scalar fpRegfileWrites;
849 //number of misc
850 Stats::Scalar miscRegfileReads;
851 Stats::Scalar miscRegfileWrites;
852};
853
854#endif // __CPU_O3_CPU_HH__