1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "cpu/activity.hh"
46#include "cpu/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;
70
71 BaseO3CPU(Params *params);
72
73 void regStats();
74
75 /** Sets this CPU's ID. */
76 void setCpuId(int id) { cpu_id = id; }
77
78 /** Reads this CPU's ID. */
79 int readCpuId() { return cpu_id; }
80
81 protected:
82 int cpu_id;
83};
84
85/**
86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages. The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93 public:
94 // Typedefs from the Impl here.
95 typedef typename Impl::CPUPol CPUPolicy;
96 typedef typename Impl::Params Params;
97 typedef typename Impl::DynInstPtr DynInstPtr;
98 typedef typename Impl::O3CPU O3CPU;
99
100 typedef O3ThreadState<Impl> Thread;
101
102 typedef typename std::list<DynInstPtr>::iterator ListIt;
103
104 friend class O3ThreadContext<Impl>;
105
106 public:
107 enum Status {
108 Running,
109 Idle,
110 Halted,
111 Blocked,
112 SwitchedOut
113 };
114
115#if FULL_SYSTEM
116 TheISA::ITB * itb;
117 TheISA::DTB * dtb;
118#endif
119
120 /** Overall CPU status. */
121 Status _status;
122
123 /** Per-thread status in CPU, used for SMT. */
124 Status _threadStatus[Impl::MaxThreads];
125
126 private:
127 class TickEvent : public Event
128 {
129 private:
130 /** Pointer to the CPU. */
131 FullO3CPU<Impl> *cpu;
132
133 public:
134 /** Constructs a tick event. */
135 TickEvent(FullO3CPU<Impl> *c);
136
137 /** Processes a tick event, calling tick() on the CPU. */
138 void process();
139 /** Returns the description of the tick event. */
140 const char *description();
141 };
142
143 /** The tick event used for scheduling CPU ticks. */
144 TickEvent tickEvent;
145
146 /** Schedule tick event, regardless of its current state. */
147 void scheduleTickEvent(int delay)
148 {
149 if (tickEvent.squashed())
150 tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
151 else if (!tickEvent.scheduled())
152 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
153 }
154
155 /** Unschedule tick event, regardless of its current state. */
156 void unscheduleTickEvent()
157 {
158 if (tickEvent.scheduled())
159 tickEvent.squash();
160 }
161
162 class ActivateThreadEvent : public Event
163 {
164 private:
165 /** Number of Thread to Activate */
166 int tid;
167
168 /** Pointer to the CPU. */
169 FullO3CPU<Impl> *cpu;
170
171 public:
172 /** Constructs the event. */
173 ActivateThreadEvent();
174
175 /** Initialize Event */
176 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
177
178 /** Processes the event, calling activateThread() on the CPU. */
179 void process();
180
181 /** Returns the description of the event. */
182 const char *description();
183 };
184
185 /** Schedule thread to activate , regardless of its current state. */
186 void scheduleActivateThreadEvent(int tid, int delay)
187 {
188 // Schedule thread to activate, regardless of its current state.
189 if (activateThreadEvent[tid].squashed())
190 activateThreadEvent[tid].
191 reschedule(nextCycle(curTick + cycles(delay)));
192 else if (!activateThreadEvent[tid].scheduled())
193 activateThreadEvent[tid].
194 schedule(nextCycle(curTick + cycles(delay)));
195 }
196
197 /** Unschedule actiavte thread event, regardless of its current state. */
198 void unscheduleActivateThreadEvent(int tid)
199 {
200 if (activateThreadEvent[tid].scheduled())
201 activateThreadEvent[tid].squash();
202 }
203
204 /** The tick event used for scheduling CPU ticks. */
205 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
206
207 class DeallocateContextEvent : public Event
208 {
209 private:
210 /** Number of Thread to deactivate */
211 int tid;
212
213 /** Should the thread be removed from the CPU? */
214 bool remove;
215
216 /** Pointer to the CPU. */
217 FullO3CPU<Impl> *cpu;
218
219 public:
220 /** Constructs the event. */
221 DeallocateContextEvent();
222
223 /** Initialize Event */
224 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
225
226 /** Processes the event, calling activateThread() on the CPU. */
227 void process();
228
229 /** Sets whether the thread should also be removed from the CPU. */
230 void setRemove(bool _remove) { remove = _remove; }
231
232 /** Returns the description of the event. */
233 const char *description();
234 };
235
236 /** Schedule cpu to deallocate thread context.*/
237 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
238 {
239 // Schedule thread to activate, regardless of its current state.
240 if (deallocateContextEvent[tid].squashed())
241 deallocateContextEvent[tid].
242 reschedule(nextCycle(curTick + cycles(delay)));
243 else if (!deallocateContextEvent[tid].scheduled())
244 deallocateContextEvent[tid].
245 schedule(nextCycle(curTick + cycles(delay)));
246 }
247
248 /** Unschedule thread deallocation in CPU */
249 void unscheduleDeallocateContextEvent(int tid)
250 {
251 if (deallocateContextEvent[tid].scheduled())
252 deallocateContextEvent[tid].squash();
253 }
254
255 /** The tick event used for scheduling CPU ticks. */
256 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
257
258 public:
259 /** Constructs a CPU with the given parameters. */
260 FullO3CPU(O3CPU *o3_cpu, Params *params);
261 /** Destructor. */
262 ~FullO3CPU();
263
264 /** Registers statistics. */
265 void fullCPURegStats();
266
267 /** Returns a specific port. */
268 Port *getPort(const std::string &if_name, int idx);
269
270 /** Ticks CPU, calling tick() on each stage, and checking the overall
271 * activity to see if the CPU should deschedule itself.
272 */
273 void tick();
274
275 /** Initialize the CPU */
276 void init();
277
278 /** Returns the Number of Active Threads in the CPU */
279 int numActiveThreads()
280 { return activeThreads.size(); }
281
282 /** Add Thread to Active Threads List */
283 void activateThread(unsigned tid);
284
285 /** Remove Thread from Active Threads List */
286 void deactivateThread(unsigned tid);
287
288 /** Setup CPU to insert a thread's context */
289 void insertThread(unsigned tid);
290
291 /** Remove all of a thread's context from CPU */
292 void removeThread(unsigned tid);
293
294 /** Count the Total Instructions Committed in the CPU. */
295 virtual Counter totalInstructions() const
296 {
297 Counter total(0);
298
299 for (int i=0; i < thread.size(); i++)
300 total += thread[i]->numInst;
301
302 return total;
303 }
304
305 /** Add Thread to Active Threads List. */
306 void activateContext(int tid, int delay);
307
308 /** Remove Thread from Active Threads List */
309 void suspendContext(int tid);
310
311 /** Remove Thread from Active Threads List &&
312 * Possibly Remove Thread Context from CPU.
313 */
314 bool deallocateContext(int tid, bool remove, int delay = 1);
315
316 /** Remove Thread from Active Threads List &&
317 * Remove Thread Context from CPU.
318 */
319 void haltContext(int tid);
320
321 /** Activate a Thread When CPU Resources are Available. */
322 void activateWhenReady(int tid);
323
324 /** Add or Remove a Thread Context in the CPU. */
325 void doContextSwitch();
326
327 /** Update The Order In Which We Process Threads. */
328 void updateThreadPriority();
329
330 /** Serialize state. */
331 virtual void serialize(std::ostream &os);
332
333 /** Unserialize from a checkpoint. */
334 virtual void unserialize(Checkpoint *cp, const std::string §ion);
335
336 public:
337 /** Executes a syscall on this cycle.
338 * ---------------------------------------
339 * Note: this is a virtual function. CPU-Specific
340 * functionality defined in derived classes
341 */
342 virtual void syscall(int tid) { panic("Unimplemented!"); }
343
344 /** Starts draining the CPU's pipeline of all instructions in
345 * order to stop all memory accesses. */
346 virtual unsigned int drain(Event *drain_event);
347
348 /** Resumes execution after a drain. */
349 virtual void resume();
350
351 /** Signals to this CPU that a stage has completed switching out. */
352 void signalDrained();
353
354 /** Switches out this CPU. */
355 virtual void switchOut();
356
357 /** Takes over from another CPU. */
358 virtual void takeOverFrom(BaseCPU *oldCPU);
359
360 /** Get the current instruction sequence number, and increment it. */
361 InstSeqNum getAndIncrementInstSeq()
362 { return globalSeqNum++; }
363
364#if FULL_SYSTEM
365 /** Update the Virt and Phys ports of all ThreadContexts to
366 * reflect change in memory connections. */
367 void updateMemPorts();
368
369 /** Check if this address is a valid instruction address. */
370 bool validInstAddr(Addr addr) { return true; }
371
372 /** Check if this address is a valid data address. */
373 bool validDataAddr(Addr addr) { return true; }
374
375 /** Get instruction asid. */
376 int getInstAsid(unsigned tid)
377 { return regFile.miscRegs[tid].getInstAsid(); }
378
379 /** Get data asid. */
380 int getDataAsid(unsigned tid)
381 { return regFile.miscRegs[tid].getDataAsid(); }
382#else
383 /** Get instruction asid. */
384 int getInstAsid(unsigned tid)
385 { return thread[tid]->getInstAsid(); }
386
387 /** Get data asid. */
388 int getDataAsid(unsigned tid)
389 { return thread[tid]->getDataAsid(); }
390
391#endif
392
393 /** Register accessors. Index refers to the physical register index. */
394 uint64_t readIntReg(int reg_idx);
395
396 TheISA::FloatReg readFloatReg(int reg_idx);
397
398 TheISA::FloatReg readFloatReg(int reg_idx, int width);
399
400 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
401
402 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
403
404 void setIntReg(int reg_idx, uint64_t val);
405
406 void setFloatReg(int reg_idx, TheISA::FloatReg val);
407
408 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
409
410 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
411
412 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
413
414 uint64_t readArchIntReg(int reg_idx, unsigned tid);
415
416 float readArchFloatRegSingle(int reg_idx, unsigned tid);
417
418 double readArchFloatRegDouble(int reg_idx, unsigned tid);
419
420 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
421
422 /** Architectural register accessors. Looks up in the commit
423 * rename table to obtain the true physical index of the
424 * architected register first, then accesses that physical
425 * register.
426 */
427 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
428
429 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
430
431 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
432
433 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
434
435 /** Reads the commit PC of a specific thread. */
436 uint64_t readPC(unsigned tid);
437
438 /** Sets the commit PC of a specific thread. */
439 void setPC(Addr new_PC, unsigned tid);
440
441 /** Reads the next PC of a specific thread. */
442 uint64_t readNextPC(unsigned tid);
443
444 /** Sets the next PC of a specific thread. */
445 void setNextPC(uint64_t val, unsigned tid);
446
447 /** Reads the next NPC of a specific thread. */
448 uint64_t readNextNPC(unsigned tid);
449
450 /** Sets the next NPC of a specific thread. */
451 void setNextNPC(uint64_t val, unsigned tid);
452
453 /** Function to add instruction onto the head of the list of the
454 * instructions. Used when new instructions are fetched.
455 */
456 ListIt addInst(DynInstPtr &inst);
457
458 /** Function to tell the CPU that an instruction has completed. */
459 void instDone(unsigned tid);
460
461 /** Add Instructions to the CPU Remove List*/
462 void addToRemoveList(DynInstPtr &inst);
463
464 /** Remove an instruction from the front end of the list. There's
465 * no restriction on location of the instruction.
466 */
467 void removeFrontInst(DynInstPtr &inst);
468
469 /** Remove all instructions that are not currently in the ROB.
470 * There's also an option to not squash delay slot instructions.*/
471 void removeInstsNotInROB(unsigned tid);
472
473 /** Remove all instructions younger than the given sequence number. */
474 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
475
476 /** Removes the instruction pointed to by the iterator. */
477 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
478
479 /** Cleans up all instructions on the remove list. */
480 void cleanUpRemovedInsts();
481
482 /** Debug function to print all instructions on the list. */
483 void dumpInsts();
484
485 public:
486 /** List of all the instructions in flight. */
487 std::list<DynInstPtr> instList;
488
489 /** List of all the instructions that will be removed at the end of this
490 * cycle.
491 */
492 std::queue<ListIt> removeList;
493
494#ifdef DEBUG
495 /** Debug structure to keep track of the sequence numbers still in
496 * flight.
497 */
498 std::set<InstSeqNum> snList;
499#endif
500
501 /** Records if instructions need to be removed this cycle due to
502 * being retired or squashed.
503 */
504 bool removeInstsThisCycle;
505
506 protected:
507 /** The fetch stage. */
508 typename CPUPolicy::Fetch fetch;
509
510 /** The decode stage. */
511 typename CPUPolicy::Decode decode;
512
513 /** The dispatch stage. */
514 typename CPUPolicy::Rename rename;
515
516 /** The issue/execute/writeback stages. */
517 typename CPUPolicy::IEW iew;
518
519 /** The commit stage. */
520 typename CPUPolicy::Commit commit;
521
522 /** The register file. */
523 typename CPUPolicy::RegFile regFile;
524
525 /** The free list. */
526 typename CPUPolicy::FreeList freeList;
527
528 /** The rename map. */
529 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
530
531 /** The commit rename map. */
532 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
533
534 /** The re-order buffer. */
535 typename CPUPolicy::ROB rob;
536
537 /** Active Threads List */
538 std::list<unsigned> activeThreads;
539
540 /** Integer Register Scoreboard */
541 Scoreboard scoreboard;
542
543 public:
544 /** Enum to give each stage a specific index, so when calling
545 * activateStage() or deactivateStage(), they can specify which stage
546 * is being activated/deactivated.
547 */
548 enum StageIdx {
549 FetchIdx,
550 DecodeIdx,
551 RenameIdx,
552 IEWIdx,
553 CommitIdx,
554 NumStages };
555
556 /** Typedefs from the Impl to get the structs that each of the
557 * time buffers should use.
558 */
559 typedef typename CPUPolicy::TimeStruct TimeStruct;
560
561 typedef typename CPUPolicy::FetchStruct FetchStruct;
562
563 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
564
565 typedef typename CPUPolicy::RenameStruct RenameStruct;
566
567 typedef typename CPUPolicy::IEWStruct IEWStruct;
568
569 /** The main time buffer to do backwards communication. */
570 TimeBuffer<TimeStruct> timeBuffer;
571
572 /** The fetch stage's instruction queue. */
573 TimeBuffer<FetchStruct> fetchQueue;
574
575 /** The decode stage's instruction queue. */
576 TimeBuffer<DecodeStruct> decodeQueue;
577
578 /** The rename stage's instruction queue. */
579 TimeBuffer<RenameStruct> renameQueue;
580
581 /** The IEW stage's instruction queue. */
582 TimeBuffer<IEWStruct> iewQueue;
583
584 private:
585 /** The activity recorder; used to tell if the CPU has any
586 * activity remaining or if it can go to idle and deschedule
587 * itself.
588 */
589 ActivityRecorder activityRec;
590
591 public:
592 /** Records that there was time buffer activity this cycle. */
593 void activityThisCycle() { activityRec.activity(); }
594
595 /** Changes a stage's status to active within the activity recorder. */
596 void activateStage(const StageIdx idx)
597 { activityRec.activateStage(idx); }
598
599 /** Changes a stage's status to inactive within the activity recorder. */
600 void deactivateStage(const StageIdx idx)
601 { activityRec.deactivateStage(idx); }
602
603 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
604 void wakeCPU();
605
606 /** Gets a free thread id. Use if thread ids change across system. */
607 int getFreeTid();
608
609 public:
610 /** Returns a pointer to a thread context. */
611 ThreadContext *tcBase(unsigned tid)
612 {
613 return thread[tid]->getTC();
614 }
615
616 /** The global sequence number counter. */
617 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
618
619 /** Pointer to the checker, which can dynamically verify
620 * instruction results at run time. This can be set to NULL if it
621 * is not being used.
622 */
623 Checker<DynInstPtr> *checker;
624
625#if FULL_SYSTEM
626 /** Pointer to the system. */
627 System *system;
628
629 /** Pointer to physical memory. */
630 PhysicalMemory *physmem;
631#endif
632
633 /** Event to call process() on once draining has completed. */
634 Event *drainEvent;
635
636 /** Counter of how many stages have completed draining. */
637 int drainCount;
638
639 /** Pointers to all of the threads in the CPU. */
640 std::vector<Thread *> thread;
641
642 /** Whether or not the CPU should defer its registration. */
643 bool deferRegistration;
644
645 /** Is there a context switch pending? */
646 bool contextSwitch;
647
648 /** Threads Scheduled to Enter CPU */
649 std::list<int> cpuWaitList;
650
651 /** The cycle that the CPU was last running, used for statistics. */
652 Tick lastRunningCycle;
653
654 /** The cycle that the CPU was last activated by a new thread*/
655 Tick lastActivatedCycle;
656
657 /** Number of Threads CPU can process */
658 unsigned numThreads;
659
660 /** Mapping for system thread id to cpu id */
661 std::map<unsigned,unsigned> threadMap;
662
663 /** Available thread ids in the cpu*/
664 std::vector<unsigned> tids;
665
666 /** Stat for total number of times the CPU is descheduled. */
667 Stats::Scalar<> timesIdled;
668 /** Stat for total number of cycles the CPU spends descheduled. */
669 Stats::Scalar<> idleCycles;
670 /** Stat for the number of committed instructions per thread. */
671 Stats::Vector<> committedInsts;
672 /** Stat for the total number of committed instructions. */
673 Stats::Scalar<> totalCommittedInsts;
674 /** Stat for the CPI per thread. */
675 Stats::Formula cpi;
676 /** Stat for the total CPI. */
677 Stats::Formula totalCpi;
678 /** Stat for the IPC per thread. */
679 Stats::Formula ipc;
680 /** Stat for the total IPC. */
681 Stats::Formula totalIpc;
682};
683
684#endif // __CPU_O3_CPU_HH__
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "cpu/activity.hh"
46#include "cpu/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;
70
71 BaseO3CPU(Params *params);
72
73 void regStats();
74
75 /** Sets this CPU's ID. */
76 void setCpuId(int id) { cpu_id = id; }
77
78 /** Reads this CPU's ID. */
79 int readCpuId() { return cpu_id; }
80
81 protected:
82 int cpu_id;
83};
84
85/**
86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages. The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93 public:
94 // Typedefs from the Impl here.
95 typedef typename Impl::CPUPol CPUPolicy;
96 typedef typename Impl::Params Params;
97 typedef typename Impl::DynInstPtr DynInstPtr;
98 typedef typename Impl::O3CPU O3CPU;
99
100 typedef O3ThreadState<Impl> Thread;
101
102 typedef typename std::list<DynInstPtr>::iterator ListIt;
103
104 friend class O3ThreadContext<Impl>;
105
106 public:
107 enum Status {
108 Running,
109 Idle,
110 Halted,
111 Blocked,
112 SwitchedOut
113 };
114
115#if FULL_SYSTEM
116 TheISA::ITB * itb;
117 TheISA::DTB * dtb;
118#endif
119
120 /** Overall CPU status. */
121 Status _status;
122
123 /** Per-thread status in CPU, used for SMT. */
124 Status _threadStatus[Impl::MaxThreads];
125
126 private:
127 class TickEvent : public Event
128 {
129 private:
130 /** Pointer to the CPU. */
131 FullO3CPU<Impl> *cpu;
132
133 public:
134 /** Constructs a tick event. */
135 TickEvent(FullO3CPU<Impl> *c);
136
137 /** Processes a tick event, calling tick() on the CPU. */
138 void process();
139 /** Returns the description of the tick event. */
140 const char *description();
141 };
142
143 /** The tick event used for scheduling CPU ticks. */
144 TickEvent tickEvent;
145
146 /** Schedule tick event, regardless of its current state. */
147 void scheduleTickEvent(int delay)
148 {
149 if (tickEvent.squashed())
150 tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
151 else if (!tickEvent.scheduled())
152 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
153 }
154
155 /** Unschedule tick event, regardless of its current state. */
156 void unscheduleTickEvent()
157 {
158 if (tickEvent.scheduled())
159 tickEvent.squash();
160 }
161
162 class ActivateThreadEvent : public Event
163 {
164 private:
165 /** Number of Thread to Activate */
166 int tid;
167
168 /** Pointer to the CPU. */
169 FullO3CPU<Impl> *cpu;
170
171 public:
172 /** Constructs the event. */
173 ActivateThreadEvent();
174
175 /** Initialize Event */
176 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
177
178 /** Processes the event, calling activateThread() on the CPU. */
179 void process();
180
181 /** Returns the description of the event. */
182 const char *description();
183 };
184
185 /** Schedule thread to activate , regardless of its current state. */
186 void scheduleActivateThreadEvent(int tid, int delay)
187 {
188 // Schedule thread to activate, regardless of its current state.
189 if (activateThreadEvent[tid].squashed())
190 activateThreadEvent[tid].
191 reschedule(nextCycle(curTick + cycles(delay)));
192 else if (!activateThreadEvent[tid].scheduled())
193 activateThreadEvent[tid].
194 schedule(nextCycle(curTick + cycles(delay)));
195 }
196
197 /** Unschedule actiavte thread event, regardless of its current state. */
198 void unscheduleActivateThreadEvent(int tid)
199 {
200 if (activateThreadEvent[tid].scheduled())
201 activateThreadEvent[tid].squash();
202 }
203
204 /** The tick event used for scheduling CPU ticks. */
205 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
206
207 class DeallocateContextEvent : public Event
208 {
209 private:
210 /** Number of Thread to deactivate */
211 int tid;
212
213 /** Should the thread be removed from the CPU? */
214 bool remove;
215
216 /** Pointer to the CPU. */
217 FullO3CPU<Impl> *cpu;
218
219 public:
220 /** Constructs the event. */
221 DeallocateContextEvent();
222
223 /** Initialize Event */
224 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
225
226 /** Processes the event, calling activateThread() on the CPU. */
227 void process();
228
229 /** Sets whether the thread should also be removed from the CPU. */
230 void setRemove(bool _remove) { remove = _remove; }
231
232 /** Returns the description of the event. */
233 const char *description();
234 };
235
236 /** Schedule cpu to deallocate thread context.*/
237 void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
238 {
239 // Schedule thread to activate, regardless of its current state.
240 if (deallocateContextEvent[tid].squashed())
241 deallocateContextEvent[tid].
242 reschedule(nextCycle(curTick + cycles(delay)));
243 else if (!deallocateContextEvent[tid].scheduled())
244 deallocateContextEvent[tid].
245 schedule(nextCycle(curTick + cycles(delay)));
246 }
247
248 /** Unschedule thread deallocation in CPU */
249 void unscheduleDeallocateContextEvent(int tid)
250 {
251 if (deallocateContextEvent[tid].scheduled())
252 deallocateContextEvent[tid].squash();
253 }
254
255 /** The tick event used for scheduling CPU ticks. */
256 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
257
258 public:
259 /** Constructs a CPU with the given parameters. */
260 FullO3CPU(O3CPU *o3_cpu, Params *params);
261 /** Destructor. */
262 ~FullO3CPU();
263
264 /** Registers statistics. */
265 void fullCPURegStats();
266
267 /** Returns a specific port. */
268 Port *getPort(const std::string &if_name, int idx);
269
270 /** Ticks CPU, calling tick() on each stage, and checking the overall
271 * activity to see if the CPU should deschedule itself.
272 */
273 void tick();
274
275 /** Initialize the CPU */
276 void init();
277
278 /** Returns the Number of Active Threads in the CPU */
279 int numActiveThreads()
280 { return activeThreads.size(); }
281
282 /** Add Thread to Active Threads List */
283 void activateThread(unsigned tid);
284
285 /** Remove Thread from Active Threads List */
286 void deactivateThread(unsigned tid);
287
288 /** Setup CPU to insert a thread's context */
289 void insertThread(unsigned tid);
290
291 /** Remove all of a thread's context from CPU */
292 void removeThread(unsigned tid);
293
294 /** Count the Total Instructions Committed in the CPU. */
295 virtual Counter totalInstructions() const
296 {
297 Counter total(0);
298
299 for (int i=0; i < thread.size(); i++)
300 total += thread[i]->numInst;
301
302 return total;
303 }
304
305 /** Add Thread to Active Threads List. */
306 void activateContext(int tid, int delay);
307
308 /** Remove Thread from Active Threads List */
309 void suspendContext(int tid);
310
311 /** Remove Thread from Active Threads List &&
312 * Possibly Remove Thread Context from CPU.
313 */
314 bool deallocateContext(int tid, bool remove, int delay = 1);
315
316 /** Remove Thread from Active Threads List &&
317 * Remove Thread Context from CPU.
318 */
319 void haltContext(int tid);
320
321 /** Activate a Thread When CPU Resources are Available. */
322 void activateWhenReady(int tid);
323
324 /** Add or Remove a Thread Context in the CPU. */
325 void doContextSwitch();
326
327 /** Update The Order In Which We Process Threads. */
328 void updateThreadPriority();
329
330 /** Serialize state. */
331 virtual void serialize(std::ostream &os);
332
333 /** Unserialize from a checkpoint. */
334 virtual void unserialize(Checkpoint *cp, const std::string §ion);
335
336 public:
337 /** Executes a syscall on this cycle.
338 * ---------------------------------------
339 * Note: this is a virtual function. CPU-Specific
340 * functionality defined in derived classes
341 */
342 virtual void syscall(int tid) { panic("Unimplemented!"); }
343
344 /** Starts draining the CPU's pipeline of all instructions in
345 * order to stop all memory accesses. */
346 virtual unsigned int drain(Event *drain_event);
347
348 /** Resumes execution after a drain. */
349 virtual void resume();
350
351 /** Signals to this CPU that a stage has completed switching out. */
352 void signalDrained();
353
354 /** Switches out this CPU. */
355 virtual void switchOut();
356
357 /** Takes over from another CPU. */
358 virtual void takeOverFrom(BaseCPU *oldCPU);
359
360 /** Get the current instruction sequence number, and increment it. */
361 InstSeqNum getAndIncrementInstSeq()
362 { return globalSeqNum++; }
363
364#if FULL_SYSTEM
365 /** Update the Virt and Phys ports of all ThreadContexts to
366 * reflect change in memory connections. */
367 void updateMemPorts();
368
369 /** Check if this address is a valid instruction address. */
370 bool validInstAddr(Addr addr) { return true; }
371
372 /** Check if this address is a valid data address. */
373 bool validDataAddr(Addr addr) { return true; }
374
375 /** Get instruction asid. */
376 int getInstAsid(unsigned tid)
377 { return regFile.miscRegs[tid].getInstAsid(); }
378
379 /** Get data asid. */
380 int getDataAsid(unsigned tid)
381 { return regFile.miscRegs[tid].getDataAsid(); }
382#else
383 /** Get instruction asid. */
384 int getInstAsid(unsigned tid)
385 { return thread[tid]->getInstAsid(); }
386
387 /** Get data asid. */
388 int getDataAsid(unsigned tid)
389 { return thread[tid]->getDataAsid(); }
390
391#endif
392
393 /** Register accessors. Index refers to the physical register index. */
394 uint64_t readIntReg(int reg_idx);
395
396 TheISA::FloatReg readFloatReg(int reg_idx);
397
398 TheISA::FloatReg readFloatReg(int reg_idx, int width);
399
400 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
401
402 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
403
404 void setIntReg(int reg_idx, uint64_t val);
405
406 void setFloatReg(int reg_idx, TheISA::FloatReg val);
407
408 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
409
410 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
411
412 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
413
414 uint64_t readArchIntReg(int reg_idx, unsigned tid);
415
416 float readArchFloatRegSingle(int reg_idx, unsigned tid);
417
418 double readArchFloatRegDouble(int reg_idx, unsigned tid);
419
420 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
421
422 /** Architectural register accessors. Looks up in the commit
423 * rename table to obtain the true physical index of the
424 * architected register first, then accesses that physical
425 * register.
426 */
427 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
428
429 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
430
431 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
432
433 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
434
435 /** Reads the commit PC of a specific thread. */
436 uint64_t readPC(unsigned tid);
437
438 /** Sets the commit PC of a specific thread. */
439 void setPC(Addr new_PC, unsigned tid);
440
441 /** Reads the next PC of a specific thread. */
442 uint64_t readNextPC(unsigned tid);
443
444 /** Sets the next PC of a specific thread. */
445 void setNextPC(uint64_t val, unsigned tid);
446
447 /** Reads the next NPC of a specific thread. */
448 uint64_t readNextNPC(unsigned tid);
449
450 /** Sets the next NPC of a specific thread. */
451 void setNextNPC(uint64_t val, unsigned tid);
452
453 /** Function to add instruction onto the head of the list of the
454 * instructions. Used when new instructions are fetched.
455 */
456 ListIt addInst(DynInstPtr &inst);
457
458 /** Function to tell the CPU that an instruction has completed. */
459 void instDone(unsigned tid);
460
461 /** Add Instructions to the CPU Remove List*/
462 void addToRemoveList(DynInstPtr &inst);
463
464 /** Remove an instruction from the front end of the list. There's
465 * no restriction on location of the instruction.
466 */
467 void removeFrontInst(DynInstPtr &inst);
468
469 /** Remove all instructions that are not currently in the ROB.
470 * There's also an option to not squash delay slot instructions.*/
471 void removeInstsNotInROB(unsigned tid);
472
473 /** Remove all instructions younger than the given sequence number. */
474 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
475
476 /** Removes the instruction pointed to by the iterator. */
477 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
478
479 /** Cleans up all instructions on the remove list. */
480 void cleanUpRemovedInsts();
481
482 /** Debug function to print all instructions on the list. */
483 void dumpInsts();
484
485 public:
486 /** List of all the instructions in flight. */
487 std::list<DynInstPtr> instList;
488
489 /** List of all the instructions that will be removed at the end of this
490 * cycle.
491 */
492 std::queue<ListIt> removeList;
493
494#ifdef DEBUG
495 /** Debug structure to keep track of the sequence numbers still in
496 * flight.
497 */
498 std::set<InstSeqNum> snList;
499#endif
500
501 /** Records if instructions need to be removed this cycle due to
502 * being retired or squashed.
503 */
504 bool removeInstsThisCycle;
505
506 protected:
507 /** The fetch stage. */
508 typename CPUPolicy::Fetch fetch;
509
510 /** The decode stage. */
511 typename CPUPolicy::Decode decode;
512
513 /** The dispatch stage. */
514 typename CPUPolicy::Rename rename;
515
516 /** The issue/execute/writeback stages. */
517 typename CPUPolicy::IEW iew;
518
519 /** The commit stage. */
520 typename CPUPolicy::Commit commit;
521
522 /** The register file. */
523 typename CPUPolicy::RegFile regFile;
524
525 /** The free list. */
526 typename CPUPolicy::FreeList freeList;
527
528 /** The rename map. */
529 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
530
531 /** The commit rename map. */
532 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
533
534 /** The re-order buffer. */
535 typename CPUPolicy::ROB rob;
536
537 /** Active Threads List */
538 std::list<unsigned> activeThreads;
539
540 /** Integer Register Scoreboard */
541 Scoreboard scoreboard;
542
543 public:
544 /** Enum to give each stage a specific index, so when calling
545 * activateStage() or deactivateStage(), they can specify which stage
546 * is being activated/deactivated.
547 */
548 enum StageIdx {
549 FetchIdx,
550 DecodeIdx,
551 RenameIdx,
552 IEWIdx,
553 CommitIdx,
554 NumStages };
555
556 /** Typedefs from the Impl to get the structs that each of the
557 * time buffers should use.
558 */
559 typedef typename CPUPolicy::TimeStruct TimeStruct;
560
561 typedef typename CPUPolicy::FetchStruct FetchStruct;
562
563 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
564
565 typedef typename CPUPolicy::RenameStruct RenameStruct;
566
567 typedef typename CPUPolicy::IEWStruct IEWStruct;
568
569 /** The main time buffer to do backwards communication. */
570 TimeBuffer<TimeStruct> timeBuffer;
571
572 /** The fetch stage's instruction queue. */
573 TimeBuffer<FetchStruct> fetchQueue;
574
575 /** The decode stage's instruction queue. */
576 TimeBuffer<DecodeStruct> decodeQueue;
577
578 /** The rename stage's instruction queue. */
579 TimeBuffer<RenameStruct> renameQueue;
580
581 /** The IEW stage's instruction queue. */
582 TimeBuffer<IEWStruct> iewQueue;
583
584 private:
585 /** The activity recorder; used to tell if the CPU has any
586 * activity remaining or if it can go to idle and deschedule
587 * itself.
588 */
589 ActivityRecorder activityRec;
590
591 public:
592 /** Records that there was time buffer activity this cycle. */
593 void activityThisCycle() { activityRec.activity(); }
594
595 /** Changes a stage's status to active within the activity recorder. */
596 void activateStage(const StageIdx idx)
597 { activityRec.activateStage(idx); }
598
599 /** Changes a stage's status to inactive within the activity recorder. */
600 void deactivateStage(const StageIdx idx)
601 { activityRec.deactivateStage(idx); }
602
603 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
604 void wakeCPU();
605
606 /** Gets a free thread id. Use if thread ids change across system. */
607 int getFreeTid();
608
609 public:
610 /** Returns a pointer to a thread context. */
611 ThreadContext *tcBase(unsigned tid)
612 {
613 return thread[tid]->getTC();
614 }
615
616 /** The global sequence number counter. */
617 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
618
619 /** Pointer to the checker, which can dynamically verify
620 * instruction results at run time. This can be set to NULL if it
621 * is not being used.
622 */
623 Checker<DynInstPtr> *checker;
624
625#if FULL_SYSTEM
626 /** Pointer to the system. */
627 System *system;
628
629 /** Pointer to physical memory. */
630 PhysicalMemory *physmem;
631#endif
632
633 /** Event to call process() on once draining has completed. */
634 Event *drainEvent;
635
636 /** Counter of how many stages have completed draining. */
637 int drainCount;
638
639 /** Pointers to all of the threads in the CPU. */
640 std::vector<Thread *> thread;
641
642 /** Whether or not the CPU should defer its registration. */
643 bool deferRegistration;
644
645 /** Is there a context switch pending? */
646 bool contextSwitch;
647
648 /** Threads Scheduled to Enter CPU */
649 std::list<int> cpuWaitList;
650
651 /** The cycle that the CPU was last running, used for statistics. */
652 Tick lastRunningCycle;
653
654 /** The cycle that the CPU was last activated by a new thread*/
655 Tick lastActivatedCycle;
656
657 /** Number of Threads CPU can process */
658 unsigned numThreads;
659
660 /** Mapping for system thread id to cpu id */
661 std::map<unsigned,unsigned> threadMap;
662
663 /** Available thread ids in the cpu*/
664 std::vector<unsigned> tids;
665
666 /** Stat for total number of times the CPU is descheduled. */
667 Stats::Scalar<> timesIdled;
668 /** Stat for total number of cycles the CPU spends descheduled. */
669 Stats::Scalar<> idleCycles;
670 /** Stat for the number of committed instructions per thread. */
671 Stats::Vector<> committedInsts;
672 /** Stat for the total number of committed instructions. */
673 Stats::Scalar<> totalCommittedInsts;
674 /** Stat for the CPI per thread. */
675 Stats::Formula cpi;
676 /** Stat for the total CPI. */
677 Stats::Formula totalCpi;
678 /** Stat for the IPC per thread. */
679 Stats::Formula ipc;
680 /** Stat for the total IPC. */
681 Stats::Formula totalIpc;
682};
683
684#endif // __CPU_O3_CPU_HH__