1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/generic/types.hh"
57#include "arch/types.hh"
58#include "base/statistics.hh"
59#include "config/the_isa.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"
65#include "cpu/base.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/timebuf.hh"
68//#include "cpu/o3/thread_context.hh"
69#include "params/DerivO3CPU.hh"
70#include "sim/process.hh"
71
72template <class>
73class Checker;
74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 using VecElem = TheISA::VecElem;
107 using VecRegContainer = TheISA::VecRegContainer;
108
109 using VecPredRegContainer = TheISA::VecPredRegContainer;
110
111 typedef O3ThreadState<Impl> ImplState;
112 typedef O3ThreadState<Impl> Thread;
113
114 typedef typename std::list<DynInstPtr>::iterator ListIt;
115
116 friend class O3ThreadContext<Impl>;
117
118 public:
119 enum Status {
120 Running,
121 Idle,
122 Halted,
123 Blocked,
124 SwitchedOut
125 };
126
127 BaseTLB *itb;
128 BaseTLB *dtb;
129 using LSQRequest = typename LSQ<Impl>::LSQRequest;
130
131 /** Overall CPU status. */
132 Status _status;
133
134 private:
135
136 /**
137 * IcachePort class for instruction fetch.
138 */
139 class IcachePort : public MasterPort
140 {
141 protected:
142 /** Pointer to fetch. */
143 DefaultFetch<Impl> *fetch;
144
145 public:
146 /** Default constructor. */
147 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
148 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
149 { }
150
151 protected:
152
153 /** Timing version of receive. Handles setting fetch to the
154 * proper status to start fetching. */
155 virtual bool recvTimingResp(PacketPtr pkt);
156
157 /** Handles doing a retry of a failed fetch. */
158 virtual void recvReqRetry();
159 };
160
161 /**
162 * DcachePort class for the load/store queue.
163 */
164 class DcachePort : public MasterPort
165 {
166 protected:
167
168 /** Pointer to LSQ. */
169 LSQ<Impl> *lsq;
170 FullO3CPU<Impl> *cpu;
171
172 public:
173 /** Default constructor. */
174 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
175 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
176 cpu(_cpu)
177 { }
178
179 protected:
180
181 /** Timing version of receive. Handles writing back and
182 * completing the load or store that has returned from
183 * memory. */
184 virtual bool recvTimingResp(PacketPtr pkt);
185 virtual void recvTimingSnoopReq(PacketPtr pkt);
186
187 virtual void recvFunctionalSnoop(PacketPtr pkt)
188 {
189 // @todo: Is there a need for potential invalidation here?
190 }
191
192 /** Handles doing a retry of the previous send. */
193 virtual void recvReqRetry();
194
195 /**
196 * As this CPU requires snooping to maintain the load store queue
197 * change the behaviour from the base CPU port.
198 *
199 * @return true since we have to snoop
200 */
201 virtual bool isSnooping() const { return true; }
202 };
203
204 /** The tick event used for scheduling CPU ticks. */
205 EventFunctionWrapper tickEvent;
206
207 /** The exit event used for terminating all ready-to-exit threads */
208 EventFunctionWrapper threadExitEvent;
209
210 /** Schedule tick event, regardless of its current state. */
211 void scheduleTickEvent(Cycles delay)
212 {
213 if (tickEvent.squashed())
214 reschedule(tickEvent, clockEdge(delay));
215 else if (!tickEvent.scheduled())
216 schedule(tickEvent, clockEdge(delay));
217 }
218
219 /** Unschedule tick event, regardless of its current state. */
220 void unscheduleTickEvent()
221 {
222 if (tickEvent.scheduled())
223 tickEvent.squash();
224 }
225
226 /**
227 * Check if the pipeline has drained and signal drain done.
228 *
229 * This method checks if a drain has been requested and if the CPU
230 * has drained successfully (i.e., there are no instructions in
231 * the pipeline). If the CPU has drained, it deschedules the tick
232 * event and signals the drain manager.
233 *
234 * @return False if a drain hasn't been requested or the CPU
235 * hasn't drained, true otherwise.
236 */
237 bool tryDrain();
238
239 /**
240 * Perform sanity checks after a drain.
241 *
242 * This method is called from drain() when it has determined that
243 * the CPU is fully drained when gem5 is compiled with the NDEBUG
244 * macro undefined. The intention of this method is to do more
245 * extensive tests than the isDrained() method to weed out any
246 * draining bugs.
247 */
248 void drainSanityCheck() const;
249
250 /** Check if a system is in a drained state. */
251 bool isDrained() const;
252
253 public:
254 /** Constructs a CPU with the given parameters. */
255 FullO3CPU(DerivO3CPUParams *params);
256 /** Destructor. */
257 ~FullO3CPU();
258
259 /** Registers statistics. */
260 void regStats() override;
261
262 ProbePointArg<PacketPtr> *ppInstAccessComplete;
263 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
264
265 /** Register probe points. */
266 void regProbePoints() override;
267
268 void demapPage(Addr vaddr, uint64_t asn)
269 {
270 this->itb->demapPage(vaddr, asn);
271 this->dtb->demapPage(vaddr, asn);
272 }
273
274 void demapInstPage(Addr vaddr, uint64_t asn)
275 {
276 this->itb->demapPage(vaddr, asn);
277 }
278
279 void demapDataPage(Addr vaddr, uint64_t asn)
280 {
281 this->dtb->demapPage(vaddr, asn);
282 }
283
284 /** Ticks CPU, calling tick() on each stage, and checking the overall
285 * activity to see if the CPU should deschedule itself.
286 */
287 void tick();
288
289 /** Initialize the CPU */
290 void init() override;
291
292 void startup() override;
293
294 /** Returns the Number of Active Threads in the CPU */
295 int numActiveThreads()
296 { return activeThreads.size(); }
297
298 /** Add Thread to Active Threads List */
299 void activateThread(ThreadID tid);
300
301 /** Remove Thread from Active Threads List */
302 void deactivateThread(ThreadID tid);
303
304 /** Setup CPU to insert a thread's context */
305 void insertThread(ThreadID tid);
306
307 /** Remove all of a thread's context from CPU */
308 void removeThread(ThreadID tid);
309
310 /** Count the Total Instructions Committed in the CPU. */
311 Counter totalInsts() const override;
312
313 /** Count the Total Ops (including micro ops) committed in the CPU. */
314 Counter totalOps() const override;
315
316 /** Add Thread to Active Threads List. */
317 void activateContext(ThreadID tid) override;
318
319 /** Remove Thread from Active Threads List */
320 void suspendContext(ThreadID tid) override;
321
322 /** Remove Thread from Active Threads List &&
323 * Remove Thread Context from CPU.
324 */
325 void haltContext(ThreadID tid) override;
326
327 /** Update The Order In Which We Process Threads. */
328 void updateThreadPriority();
329
330 /** Is the CPU draining? */
331 bool isDraining() const { return drainState() == DrainState::Draining; }
332
333 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
334 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
335
336 /** Insert tid to the list of threads trying to exit */
337 void addThreadToExitingList(ThreadID tid);
338
339 /** Is the thread trying to exit? */
340 bool isThreadExiting(ThreadID tid) const;
341
342 /**
343 * If a thread is trying to exit and its corresponding trap event
344 * has been completed, schedule an event to terminate the thread.
345 */
346 void scheduleThreadExitEvent(ThreadID tid);
347
348 /** Terminate all threads that are ready to exit */
349 void exitThreads();
350
351 public:
352 /** Executes a syscall.
353 * @todo: Determine if this needs to be virtual.
354 */
355 void syscall(int64_t callnum, ThreadID tid, Fault *fault);
356
357 /** Starts draining the CPU's pipeline of all instructions in
358 * order to stop all memory accesses. */
359 DrainState drain() override;
360
361 /** Resumes execution after a drain. */
362 void drainResume() override;
363
364 /**
365 * Commit has reached a safe point to drain a thread.
366 *
367 * Commit calls this method to inform the pipeline that it has
368 * reached a point where it is not executed microcode and is about
369 * to squash uncommitted instructions to fully drain the pipeline.
370 */
371 void commitDrained(ThreadID tid);
372
373 /** Switches out this CPU. */
374 void switchOut() override;
375
376 /** Takes over from another CPU. */
377 void takeOverFrom(BaseCPU *oldCPU) override;
378
379 void verifyMemoryMode() const override;
380
381 /** Get the current instruction sequence number, and increment it. */
382 InstSeqNum getAndIncrementInstSeq()
383 { return globalSeqNum++; }
384
385 /** Traps to handle given fault. */
386 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
387
388 /** HW return from error interrupt. */
389 Fault hwrei(ThreadID tid);
390
391 bool simPalCheck(int palFunc, ThreadID tid);
392
393 /** Check if a change in renaming is needed for vector registers.
394 * The vecMode variable is updated and propagated to rename maps.
395 *
396 * @param tid ThreadID
397 * @param freelist list of free registers
398 */
399 void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
400
401 /** Returns the Fault for any valid interrupt. */
402 Fault getInterrupts();
403
404 /** Processes any an interrupt fault. */
405 void processInterrupts(const Fault &interrupt);
406
407 /** Halts the CPU. */
408 void halt() { panic("Halt not implemented!\n"); }
409
410 /** Register accessors. Index refers to the physical register index. */
411
412 /** Reads a miscellaneous register. */
413 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
414
415 /** Reads a misc. register, including any side effects the read
416 * might have as defined by the architecture.
417 */
418 RegVal readMiscReg(int misc_reg, ThreadID tid);
419
420 /** Sets a miscellaneous register. */
421 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
422
423 /** Sets a misc. register, including any side effects the write
424 * might have as defined by the architecture.
425 */
426 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
427
428 RegVal readIntReg(PhysRegIdPtr phys_reg);
429
430 RegVal readFloatReg(PhysRegIdPtr phys_reg);
431
432 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
433
434 /**
435 * Read physical vector register for modification.
436 */
437 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
438
439 /** Returns current vector renaming mode */
440 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
441
442 /** Sets the current vector renaming mode */
443 void vecRenameMode(Enums::VecRegRenameMode vec_mode)
444 { vecMode = vec_mode; }
445
446 /**
447 * Read physical vector register lane
448 */
449 template<typename VecElem, int LaneIdx>
450 VecLaneT<VecElem, true>
451 readVecLane(PhysRegIdPtr phys_reg) const
452 {
453 vecRegfileReads++;
454 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
455 }
456
457 /**
458 * Read physical vector register lane
459 */
460 template<typename VecElem>
461 VecLaneT<VecElem, true>
462 readVecLane(PhysRegIdPtr phys_reg) const
463 {
464 vecRegfileReads++;
465 return regFile.readVecLane<VecElem>(phys_reg);
466 }
467
468 /** Write a lane of the destination vector register. */
469 template<typename LD>
470 void
471 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
472 {
473 vecRegfileWrites++;
474 return regFile.setVecLane(phys_reg, val);
475 }
476
477 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
478
479 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
480
481 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
482
483 RegVal readCCReg(PhysRegIdPtr phys_reg);
484
485 void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
486
487 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
488
489 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
490
491 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
492
493 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
494
495 void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
496
497 RegVal readArchIntReg(int reg_idx, ThreadID tid);
498
499 RegVal readArchFloatReg(int reg_idx, ThreadID tid);
500
501 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
502 /** Read architectural vector register for modification. */
503 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
504
505 /** Read architectural vector register lane. */
506 template<typename VecElem>
507 VecLaneT<VecElem, true>
508 readArchVecLane(int reg_idx, int lId, ThreadID tid) const
509 {
510 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
511 RegId(VecRegClass, reg_idx));
512 return readVecLane<VecElem>(phys_reg);
513 }
514
515
516 /** Write a lane of the destination vector register. */
517 template<typename LD>
518 void
519 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
520 {
521 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
522 RegId(VecRegClass, reg_idx));
523 setVecLane(phys_reg, val);
524 }
525
526 const VecElem& readArchVecElem(const RegIndex& reg_idx,
527 const ElemIndex& ldx, ThreadID tid) const;
528
529 const VecPredRegContainer& readArchVecPredReg(int reg_idx,
530 ThreadID tid) const;
531
532 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
533
534 RegVal readArchCCReg(int reg_idx, ThreadID tid);
535
536 /** Architectural register accessors. Looks up in the commit
537 * rename table to obtain the true physical index of the
538 * architected register first, then accesses that physical
539 * register.
540 */
541 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
542
543 void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
544
545 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
546 ThreadID tid);
547
548 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
549
550 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
551 const VecElem& val, ThreadID tid);
552
553 void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
554
555 /** Sets the commit PC state of a specific thread. */
556 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
557
558 /** Reads the commit PC state of a specific thread. */
559 TheISA::PCState pcState(ThreadID tid);
560
561 /** Reads the commit PC of a specific thread. */
562 Addr instAddr(ThreadID tid);
563
564 /** Reads the commit micro PC of a specific thread. */
565 MicroPC microPC(ThreadID tid);
566
567 /** Reads the next PC of a specific thread. */
568 Addr nextInstAddr(ThreadID tid);
569
570 /** Initiates a squash of all in-flight instructions for a given
571 * thread. The source of the squash is an external update of
572 * state through the TC.
573 */
574 void squashFromTC(ThreadID tid);
575
576 /** Function to add instruction onto the head of the list of the
577 * instructions. Used when new instructions are fetched.
578 */
579 ListIt addInst(const DynInstPtr &inst);
580
581 /** Function to tell the CPU that an instruction has completed. */
582 void instDone(ThreadID tid, const DynInstPtr &inst);
583
584 /** Remove an instruction from the front end of the list. There's
585 * no restriction on location of the instruction.
586 */
587 void removeFrontInst(const DynInstPtr &inst);
588
589 /** Remove all instructions that are not currently in the ROB.
590 * There's also an option to not squash delay slot instructions.*/
591 void removeInstsNotInROB(ThreadID tid);
592
593 /** Remove all instructions younger than the given sequence number. */
594 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
595
596 /** Removes the instruction pointed to by the iterator. */
597 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
598
599 /** Cleans up all instructions on the remove list. */
600 void cleanUpRemovedInsts();
601
602 /** Debug function to print all instructions on the list. */
603 void dumpInsts();
604
605 public:
606#ifndef NDEBUG
607 /** Count of total number of dynamic instructions in flight. */
608 int instcount;
609#endif
610
611 /** List of all the instructions in flight. */
612 std::list<DynInstPtr> instList;
613
614 /** List of all the instructions that will be removed at the end of this
615 * cycle.
616 */
617 std::queue<ListIt> removeList;
618
619#ifdef DEBUG
620 /** Debug structure to keep track of the sequence numbers still in
621 * flight.
622 */
623 std::set<InstSeqNum> snList;
624#endif
625
626 /** Records if instructions need to be removed this cycle due to
627 * being retired or squashed.
628 */
629 bool removeInstsThisCycle;
630
631 protected:
632 /** The fetch stage. */
633 typename CPUPolicy::Fetch fetch;
634
635 /** The decode stage. */
636 typename CPUPolicy::Decode decode;
637
638 /** The dispatch stage. */
639 typename CPUPolicy::Rename rename;
640
641 /** The issue/execute/writeback stages. */
642 typename CPUPolicy::IEW iew;
643
644 /** The commit stage. */
645 typename CPUPolicy::Commit commit;
646
647 /** The rename mode of the vector registers */
648 Enums::VecRegRenameMode vecMode;
649
650 /** The register file. */
651 PhysRegFile regFile;
652
653 /** The free list. */
654 typename CPUPolicy::FreeList freeList;
655
656 /** The rename map. */
657 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
658
659 /** The commit rename map. */
660 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
661
662 /** The re-order buffer. */
663 typename CPUPolicy::ROB rob;
664
665 /** Active Threads List */
666 std::list<ThreadID> activeThreads;
667
668 /**
669 * This is a list of threads that are trying to exit. Each thread id
670 * is mapped to a boolean value denoting whether the thread is ready
671 * to exit.
672 */
673 std::unordered_map<ThreadID, bool> exitingThreads;
674
675 /** Integer Register Scoreboard */
676 Scoreboard scoreboard;
677
678 std::vector<TheISA::ISA *> isa;
679
680 /** Instruction port. Note that it has to appear after the fetch stage. */
681 IcachePort icachePort;
682
683 /** Data port. Note that it has to appear after the iew stages */
684 DcachePort dcachePort;
685
686 public:
687 /** Enum to give each stage a specific index, so when calling
688 * activateStage() or deactivateStage(), they can specify which stage
689 * is being activated/deactivated.
690 */
691 enum StageIdx {
692 FetchIdx,
693 DecodeIdx,
694 RenameIdx,
695 IEWIdx,
696 CommitIdx,
697 NumStages };
698
699 /** Typedefs from the Impl to get the structs that each of the
700 * time buffers should use.
701 */
702 typedef typename CPUPolicy::TimeStruct TimeStruct;
703
704 typedef typename CPUPolicy::FetchStruct FetchStruct;
705
706 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
707
708 typedef typename CPUPolicy::RenameStruct RenameStruct;
709
710 typedef typename CPUPolicy::IEWStruct IEWStruct;
711
712 /** The main time buffer to do backwards communication. */
713 TimeBuffer<TimeStruct> timeBuffer;
714
715 /** The fetch stage's instruction queue. */
716 TimeBuffer<FetchStruct> fetchQueue;
717
718 /** The decode stage's instruction queue. */
719 TimeBuffer<DecodeStruct> decodeQueue;
720
721 /** The rename stage's instruction queue. */
722 TimeBuffer<RenameStruct> renameQueue;
723
724 /** The IEW stage's instruction queue. */
725 TimeBuffer<IEWStruct> iewQueue;
726
727 private:
728 /** The activity recorder; used to tell if the CPU has any
729 * activity remaining or if it can go to idle and deschedule
730 * itself.
731 */
732 ActivityRecorder activityRec;
733
734 public:
735 /** Records that there was time buffer activity this cycle. */
736 void activityThisCycle() { activityRec.activity(); }
737
738 /** Changes a stage's status to active within the activity recorder. */
739 void activateStage(const StageIdx idx)
740 { activityRec.activateStage(idx); }
741
742 /** Changes a stage's status to inactive within the activity recorder. */
743 void deactivateStage(const StageIdx idx)
744 { activityRec.deactivateStage(idx); }
745
746 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
747 void wakeCPU();
748
749 virtual void wakeup(ThreadID tid) override;
750
751 /** Gets a free thread id. Use if thread ids change across system. */
752 ThreadID getFreeTid();
753
754 public:
755 /** Returns a pointer to a thread context. */
756 ThreadContext *
757 tcBase(ThreadID tid)
758 {
759 return thread[tid]->getTC();
760 }
761
762 /** The global sequence number counter. */
763 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
764
765 /** Pointer to the checker, which can dynamically verify
766 * instruction results at run time. This can be set to NULL if it
767 * is not being used.
768 */
769 Checker<Impl> *checker;
770
771 /** Pointer to the system. */
772 System *system;
773
774 /** Pointers to all of the threads in the CPU. */
775 std::vector<Thread *> thread;
776
777 /** Threads Scheduled to Enter CPU */
778 std::list<int> cpuWaitList;
779
780 /** The cycle that the CPU was last running, used for statistics. */
781 Cycles lastRunningCycle;
782
783 /** The cycle that the CPU was last activated by a new thread*/
784 Tick lastActivatedCycle;
785
786 /** Mapping for system thread id to cpu id */
787 std::map<ThreadID, unsigned> threadMap;
788
789 /** Available thread ids in the cpu*/
790 std::vector<ThreadID> tids;
791
792 /** CPU pushRequest function, forwards request to LSQ. */
793 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
794 unsigned int size, Addr addr, Request::Flags flags,
795 uint64_t *res, AtomicOpFunctor *amo_op = nullptr)
796 {
797 return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
798 flags, res, amo_op);
799 }
800
801 /** CPU read function, forwards read to LSQ. */
802 Fault read(LSQRequest* req, int load_idx)
803 {
804 return this->iew.ldstQueue.read(req, load_idx);
805 }
806
807 /** CPU write function, forwards write to LSQ. */
808 Fault write(LSQRequest* req, uint8_t *data, int store_idx)
809 {
810 return this->iew.ldstQueue.write(req, data, store_idx);
811 }
812
813 /** Used by the fetch unit to get a hold of the instruction port. */
814 MasterPort &getInstPort() override { return icachePort; }
815
816 /** Get the dcache port (used to find block size for translations). */
817 MasterPort &getDataPort() override { return dcachePort; }
818
819 /** Stat for total number of times the CPU is descheduled. */
820 Stats::Scalar timesIdled;
821 /** Stat for total number of cycles the CPU spends descheduled. */
822 Stats::Scalar idleCycles;
823 /** Stat for total number of cycles the CPU spends descheduled due to a
824 * quiesce operation or waiting for an interrupt. */
825 Stats::Scalar quiesceCycles;
826 /** Stat for the number of committed instructions per thread. */
827 Stats::Vector committedInsts;
828 /** Stat for the number of committed ops (including micro ops) per thread. */
829 Stats::Vector committedOps;
830 /** Stat for the CPI per thread. */
831 Stats::Formula cpi;
832 /** Stat for the total CPI. */
833 Stats::Formula totalCpi;
834 /** Stat for the IPC per thread. */
835 Stats::Formula ipc;
836 /** Stat for the total IPC. */
837 Stats::Formula totalIpc;
838
839 //number of integer register file accesses
840 Stats::Scalar intRegfileReads;
841 Stats::Scalar intRegfileWrites;
842 //number of float register file accesses
843 Stats::Scalar fpRegfileReads;
844 Stats::Scalar fpRegfileWrites;
845 //number of vector register file accesses
846 mutable Stats::Scalar vecRegfileReads;
847 Stats::Scalar vecRegfileWrites;
848 //number of predicate register file accesses
849 mutable Stats::Scalar vecPredRegfileReads;
850 Stats::Scalar vecPredRegfileWrites;
851 //number of CC register file accesses
852 Stats::Scalar ccRegfileReads;
853 Stats::Scalar ccRegfileWrites;
854 //number of misc
855 Stats::Scalar miscRegfileReads;
856 Stats::Scalar miscRegfileWrites;
857};
858
859#endif // __CPU_O3_CPU_HH__