1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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439 * register.
440 */
441 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
442
443 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
444
445 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
446
447 /** Sets the commit PC state of a specific thread. */
448 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
449
450 /** Reads the commit PC state of a specific thread. */
451 TheISA::PCState pcState(ThreadID tid);
452
453 /** Reads the commit PC of a specific thread. */
454 Addr instAddr(ThreadID tid);
455
456 /** Reads the commit micro PC of a specific thread. */
457 MicroPC microPC(ThreadID tid);
458
459 /** Reads the next PC of a specific thread. */
460 Addr nextInstAddr(ThreadID tid);
461
462 /** Initiates a squash of all in-flight instructions for a given
463 * thread. The source of the squash is an external update of
464 * state through the TC.
465 */
466 void squashFromTC(ThreadID tid);
467
468 /** Function to add instruction onto the head of the list of the
469 * instructions. Used when new instructions are fetched.

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