1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;

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106 friend class O3ThreadContext<Impl>;
107
108 public:
109 enum Status {
110 Running,
111 Idle,
112 Halted,
113 Blocked,
114 Drained,
115 SwitchedOut
116 };
117
118 /** Overall CPU status. */
119 Status _status;
120
121 /** Per-thread status in CPU, used for SMT. */
122 Status _threadStatus[Impl::MaxThreads];

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268
269 /** Executes a syscall on this cycle.
270 * ---------------------------------------
271 * Note: this is a virtual function. CPU-Specific
272 * functionality defined in derived classes
273 */
274 virtual void syscall(int tid) { panic("Unimplemented!"); }
275
276 /** Starts draining the CPU's pipeline of all instructions in
277 * order to stop all memory accesses. */
278 virtual bool drain(Event *drain_event);
279
280 /** Resumes execution after a drain. */
281 virtual void resume();
282
283 /** Signals to this CPU that a stage has completed switching out. */
284 void signalDrained();
285
286 /** Switches out this CPU. */
287 virtual void switchOut();
288
289 /** Takes over from another CPU. */
290 virtual void takeOverFrom(BaseCPU *oldCPU);
291
292 /** Get the current instruction sequence number, and increment it. */
293 InstSeqNum getAndIncrementInstSeq()
294 { return globalSeqNum++; }
295
296#if FULL_SYSTEM
297 /** Check if this address is a valid instruction address. */
298 bool validInstAddr(Addr addr) { return true; }

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555
556 /** Pointer to physical memory. */
557 PhysicalMemory *physmem;
558#endif
559
560 /** Pointer to memory. */
561 MemObject *mem;
562
563 /** Event to call process() on once draining has completed. */
564 Event *drainEvent;
565
566 /** Counter of how many stages have completed draining. */
567 int drainCount;
568
569 /** Pointers to all of the threads in the CPU. */
570 std::vector<Thread *> thread;
571
572 /** Pointer to the icache interface. */
573 MemInterface *icacheInterface;
574 /** Pointer to the dcache interface. */
575 MemInterface *dcacheInterface;
576

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