cpu.cc (9919:803903a8dac1) cpu.cc (9920:028e4da64b42)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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220 removeInstsThisCycle(false),
221 fetch(this, params),
222 decode(this, params),
223 rename(this, params),
224 iew(this, params),
225 commit(this, params),
226
227 regFile(params->numPhysIntRegs,
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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220 removeInstsThisCycle(false),
221 fetch(this, params),
222 decode(this, params),
223 rename(this, params),
224 iew(this, params),
225 commit(this, params),
226
227 regFile(params->numPhysIntRegs,
228 params->numPhysFloatRegs),
228 params->numPhysFloatRegs,
229 params->numPhysCCRegs),
229
230 freeList(name() + ".freelist", &regFile),
231
232 rob(this,
233 params->numROBEntries, params->squashWidth,
234 params->smtROBPolicy, params->smtROBThreshold,
235 params->numThreads),
236

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322 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
323 "or edit your workload size.");
324 }
325 }
326
327 //Make Sure That this a Valid Architeture
328 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
329 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
230
231 freeList(name() + ".freelist", &regFile),
232
233 rob(this,
234 params->numROBEntries, params->squashWidth,
235 params->smtROBPolicy, params->smtROBThreshold,
236 params->numThreads),
237

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323 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
324 "or edit your workload size.");
325 }
326 }
327
328 //Make Sure That this a Valid Architeture
329 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
330 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
331 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
330
331 rename.setScoreboard(&scoreboard);
332 iew.setScoreboard(&scoreboard);
333
334 // Setup the rename map for whichever stages need it.
335 for (ThreadID tid = 0; tid < numThreads; tid++) {
336 isa[tid] = params->isa[tid];
337

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363 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
364 }
365
366 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
367 PhysRegIndex phys_reg = freeList.getFloatReg();
368 renameMap[tid].setFloatEntry(ridx, phys_reg);
369 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
370 }
332
333 rename.setScoreboard(&scoreboard);
334 iew.setScoreboard(&scoreboard);
335
336 // Setup the rename map for whichever stages need it.
337 for (ThreadID tid = 0; tid < numThreads; tid++) {
338 isa[tid] = params->isa[tid];
339

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365 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
366 }
367
368 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
369 PhysRegIndex phys_reg = freeList.getFloatReg();
370 renameMap[tid].setFloatEntry(ridx, phys_reg);
371 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
372 }
373
374 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
375 PhysRegIndex phys_reg = freeList.getCCReg();
376 renameMap[tid].setCCEntry(ridx, phys_reg);
377 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
378 }
371 }
372
373 rename.setRenameMap(renameMap);
374 commit.setRenameMap(commitRenameMap);
375 rename.setFreeList(&freeList);
376
377 // Setup the ROB for whichever stages need it.
378 commit.setROB(&rob);

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550 .desc("number of floating regfile reads")
551 .prereq(fpRegfileReads);
552
553 fpRegfileWrites
554 .name(name() + ".fp_regfile_writes")
555 .desc("number of floating regfile writes")
556 .prereq(fpRegfileWrites);
557
379 }
380
381 rename.setRenameMap(renameMap);
382 commit.setRenameMap(commitRenameMap);
383 rename.setFreeList(&freeList);
384
385 // Setup the ROB for whichever stages need it.
386 commit.setROB(&rob);

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558 .desc("number of floating regfile reads")
559 .prereq(fpRegfileReads);
560
561 fpRegfileWrites
562 .name(name() + ".fp_regfile_writes")
563 .desc("number of floating regfile writes")
564 .prereq(fpRegfileWrites);
565
566 ccRegfileReads
567 .name(name() + ".cc_regfile_reads")
568 .desc("number of cc regfile reads")
569 .prereq(ccRegfileReads);
570
571 ccRegfileWrites
572 .name(name() + ".cc_regfile_writes")
573 .desc("number of cc regfile writes")
574 .prereq(ccRegfileWrites);
575
558 miscRegfileReads
559 .name(name() + ".misc_regfile_reads")
560 .desc("number of misc regfile reads")
561 .prereq(miscRegfileReads);
562
563 miscRegfileWrites
564 .name(name() + ".misc_regfile_writes")
565 .desc("number of misc regfile writes")

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837 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
838 PhysRegIndex phys_reg = freeList.getIntReg();
839
840 renameMap[tid].setEntry(ireg,phys_reg);
841 scoreboard.setReg(phys_reg);
842 }
843
844 //Bind Float Regs to Rename Map
576 miscRegfileReads
577 .name(name() + ".misc_regfile_reads")
578 .desc("number of misc regfile reads")
579 .prereq(miscRegfileReads);
580
581 miscRegfileWrites
582 .name(name() + ".misc_regfile_writes")
583 .desc("number of misc regfile writes")

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855 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
856 PhysRegIndex phys_reg = freeList.getIntReg();
857
858 renameMap[tid].setEntry(ireg,phys_reg);
859 scoreboard.setReg(phys_reg);
860 }
861
862 //Bind Float Regs to Rename Map
845 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
863 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
864 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
846 PhysRegIndex phys_reg = freeList.getFloatReg();
847
848 renameMap[tid].setEntry(freg,phys_reg);
849 scoreboard.setReg(phys_reg);
850 }
851
865 PhysRegIndex phys_reg = freeList.getFloatReg();
866
867 renameMap[tid].setEntry(freg,phys_reg);
868 scoreboard.setReg(phys_reg);
869 }
870
871 //Bind condition-code Regs to Rename Map
872 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
873 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
874 creg < max_reg; creg++) {
875 PhysRegIndex phys_reg = freeList.getCCReg();
876
877 renameMap[tid].setEntry(creg,phys_reg);
878 scoreboard.setReg(phys_reg);
879 }
880
852 //Copy Thread Data Into RegFile
853 //this->copyFromTC(tid);
854
855 //Set PC/NPC/NNPC
856 pcState(src_tc->pcState(), tid);
857
858 src_tc->setStatus(ThreadContext::Active);
859

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883 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
884 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
885
886 scoreboard.unsetReg(phys_reg);
887 freeList.addReg(phys_reg);
888 }
889
890 // Unbind Float Regs from Rename Map
881 //Copy Thread Data Into RegFile
882 //this->copyFromTC(tid);
883
884 //Set PC/NPC/NNPC
885 pcState(src_tc->pcState(), tid);
886
887 src_tc->setStatus(ThreadContext::Active);
888

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912 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
913 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
914
915 scoreboard.unsetReg(phys_reg);
916 freeList.addReg(phys_reg);
917 }
918
919 // Unbind Float Regs from Rename Map
891 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
920 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
921 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
892 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
893
894 scoreboard.unsetReg(phys_reg);
895 freeList.addReg(phys_reg);
896 }
897
922 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
923
924 scoreboard.unsetReg(phys_reg);
925 freeList.addReg(phys_reg);
926 }
927
928 // Unbind condition-code Regs from Rename Map
929 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
930 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
931 creg < max_reg; creg++) {
932 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
933
934 scoreboard.unsetReg(phys_reg);
935 freeList.addReg(phys_reg);
936 }
937
898 // Squash Throughout Pipeline
899 DynInstPtr inst = commit.rob->readHeadInst(tid);
900 InstSeqNum squash_seq_num = inst->seqNum;
901 fetch.squash(0, squash_seq_num, inst, tid);
902 decode.squash(tid);
903 rename.squash(squash_seq_num, tid);
904 iew.squash(tid);
905 iew.ldstQueue.squash(squash_seq_num, tid);

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929FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
930{
931 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
932 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
933 tid);
934
935 bool ready = true;
936
938 // Squash Throughout Pipeline
939 DynInstPtr inst = commit.rob->readHeadInst(tid);
940 InstSeqNum squash_seq_num = inst->seqNum;
941 fetch.squash(0, squash_seq_num, inst, tid);
942 decode.squash(tid);
943 rename.squash(squash_seq_num, tid);
944 iew.squash(tid);
945 iew.ldstQueue.squash(squash_seq_num, tid);

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969FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
970{
971 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
972 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
973 tid);
974
975 bool ready = true;
976
977 // Should these all be '<' not '>='? This seems backwards...
937 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
938 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
939 "Phys. Int. Regs.\n",
940 tid);
941 ready = false;
942 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
943 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944 "Phys. Float. Regs.\n",
945 tid);
946 ready = false;
978 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
979 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
980 "Phys. Int. Regs.\n",
981 tid);
982 ready = false;
983 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
984 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
985 "Phys. Float. Regs.\n",
986 tid);
987 ready = false;
988 } else if (freeList.numFreeCCRegs() >= TheISA::NumCCRegs) {
989 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
990 "Phys. CC. Regs.\n",
991 tid);
992 ready = false;
947 } else if (commit.rob->numFreeEntries() >=
948 commit.rob->entryAmount(activeThreads.size() + 1)) {
949 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950 "ROB entries.\n",
951 tid);
952 ready = false;
953 } else if (iew.instQueue.numFreeEntries() >=
954 iew.instQueue.entryAmount(activeThreads.size() + 1)) {

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1361FloatRegBits
1362FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1363{
1364 fpRegfileReads++;
1365 return regFile.readFloatRegBits(reg_idx);
1366}
1367
1368template <class Impl>
993 } else if (commit.rob->numFreeEntries() >=
994 commit.rob->entryAmount(activeThreads.size() + 1)) {
995 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
996 "ROB entries.\n",
997 tid);
998 ready = false;
999 } else if (iew.instQueue.numFreeEntries() >=
1000 iew.instQueue.entryAmount(activeThreads.size() + 1)) {

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1407FloatRegBits
1408FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1409{
1410 fpRegfileReads++;
1411 return regFile.readFloatRegBits(reg_idx);
1412}
1413
1414template <class Impl>
1415CCReg
1416FullO3CPU<Impl>::readCCReg(int reg_idx)
1417{
1418 ccRegfileReads++;
1419 return regFile.readCCReg(reg_idx);
1420}
1421
1422template <class Impl>
1369void
1370FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1371{
1372 intRegfileWrites++;
1373 regFile.setIntReg(reg_idx, val);
1374}
1375
1376template <class Impl>

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1385void
1386FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1387{
1388 fpRegfileWrites++;
1389 regFile.setFloatRegBits(reg_idx, val);
1390}
1391
1392template <class Impl>
1423void
1424FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1425{
1426 intRegfileWrites++;
1427 regFile.setIntReg(reg_idx, val);
1428}
1429
1430template <class Impl>

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1439void
1440FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1441{
1442 fpRegfileWrites++;
1443 regFile.setFloatRegBits(reg_idx, val);
1444}
1445
1446template <class Impl>
1447void
1448FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1449{
1450 ccRegfileWrites++;
1451 regFile.setCCReg(reg_idx, val);
1452}
1453
1454template <class Impl>
1393uint64_t
1394FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1395{
1396 intRegfileReads++;
1397 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1398
1399 return regFile.readIntReg(phys_reg);
1400}

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1415{
1416 fpRegfileReads++;
1417 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1418
1419 return regFile.readFloatRegBits(phys_reg);
1420}
1421
1422template <class Impl>
1455uint64_t
1456FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1457{
1458 intRegfileReads++;
1459 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1460
1461 return regFile.readIntReg(phys_reg);
1462}

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1477{
1478 fpRegfileReads++;
1479 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1480
1481 return regFile.readFloatRegBits(phys_reg);
1482}
1483
1484template <class Impl>
1485CCReg
1486FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1487{
1488 ccRegfileReads++;
1489 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1490
1491 return regFile.readCCReg(phys_reg);
1492}
1493
1494template <class Impl>
1423void
1424FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1425{
1426 intRegfileWrites++;
1427 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1428
1429 regFile.setIntReg(phys_reg, val);
1430}

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1445{
1446 fpRegfileWrites++;
1447 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1448
1449 regFile.setFloatRegBits(phys_reg, val);
1450}
1451
1452template <class Impl>
1495void
1496FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1497{
1498 intRegfileWrites++;
1499 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1500
1501 regFile.setIntReg(phys_reg, val);
1502}

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1517{
1518 fpRegfileWrites++;
1519 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1520
1521 regFile.setFloatRegBits(phys_reg, val);
1522}
1523
1524template <class Impl>
1525void
1526FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1527{
1528 ccRegfileWrites++;
1529 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1530
1531 regFile.setCCReg(phys_reg, val);
1532}
1533
1534template <class Impl>
1453TheISA::PCState
1454FullO3CPU<Impl>::pcState(ThreadID tid)
1455{
1456 return commit.pcState(tid);
1457}
1458
1459template <class Impl>
1460void

--- 312 unchanged lines hidden --- 		1535TheISA::PCState
1536FullO3CPU<Impl>::pcState(ThreadID tid)
1537{
1538 return commit.pcState(tid);
1539}
1540
1541template <class Impl>
1542void

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