cpu.cc (9436:4a0223da4924) cpu.cc (9444:ab47fe7f03f0)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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252 renameQueue(params->backComSize, params->forwardComSize),
253 iewQueue(params->backComSize, params->forwardComSize),
254 activityRec(name(), NumStages,
255 params->backComSize + params->forwardComSize,
256 params->activity),
257
258 globalSeqNum(1),
259 system(params->system),
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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252 renameQueue(params->backComSize, params->forwardComSize),
253 iewQueue(params->backComSize, params->forwardComSize),
254 activityRec(name(), NumStages,
255 params->backComSize + params->forwardComSize,
256 params->activity),
257
258 globalSeqNum(1),
259 system(params->system),
260 drainCount(0),
260 drainManager(NULL),
261 lastRunningCycle(curCycle())
262{
263 if (!params->switched_out) {
264 _status = Running;
265 } else {
266 _status = SwitchedOut;
267 }
268

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579 .prereq(miscRegfileWrites);
580}
581
582template <class Impl>
583void
584FullO3CPU<Impl>::tick()
585{
586 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
261 lastRunningCycle(curCycle())
262{
263 if (!params->switched_out) {
264 _status = Running;
265 } else {
266 _status = SwitchedOut;
267 }
268

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579 .prereq(miscRegfileWrites);
580}
581
582template <class Impl>
583void
584FullO3CPU<Impl>::tick()
585{
586 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
587 assert(!switchedOut());
588 assert(getDrainState() != Drainable::Drained);
587
588 ++numCycles;
589
590// activity = false;
591
592 //Tick each of the stages
593 fetch.tick();
594

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613
614 activityRec.advance();
615
616 if (removeInstsThisCycle) {
617 cleanUpRemovedInsts();
618 }
619
620 if (!tickEvent.scheduled()) {
589
590 ++numCycles;
591
592// activity = false;
593
594 //Tick each of the stages
595 fetch.tick();
596

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615
616 activityRec.advance();
617
618 if (removeInstsThisCycle) {
619 cleanUpRemovedInsts();
620 }
621
622 if (!tickEvent.scheduled()) {
621 if (_status == SwitchedOut ||
622 getDrainState() == Drainable::Drained) {
623 if (_status == SwitchedOut) {
623 DPRINTF(O3CPU, "Switched out!\n");
624 // increment stat
625 lastRunningCycle = curCycle();
626 } else if (!activityRec.active() || _status == Idle) {
627 DPRINTF(O3CPU, "Idle!\n");
628 lastRunningCycle = curCycle();
629 timesIdled++;
630 } else {
631 schedule(tickEvent, clockEdge(Cycles(1)));
632 DPRINTF(O3CPU, "Scheduling next tick!\n");
633 }
634 }
635
636 if (!FullSystem)
637 updateThreadPriority();
624 DPRINTF(O3CPU, "Switched out!\n");
625 // increment stat
626 lastRunningCycle = curCycle();
627 } else if (!activityRec.active() || _status == Idle) {
628 DPRINTF(O3CPU, "Idle!\n");
629 lastRunningCycle = curCycle();
630 timesIdled++;
631 } else {
632 schedule(tickEvent, clockEdge(Cycles(1)));
633 DPRINTF(O3CPU, "Scheduling next tick!\n");
634 }
635 }
636
637 if (!FullSystem)
638 updateThreadPriority();
639
640 tryDrain();
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::init()
643{
644 BaseCPU::init();
645

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652 for (ThreadID tid = 0; tid < numThreads; ++tid) {
653 // Set noSquashFromTC so that the CPU doesn't squash when initially
654 // setting up registers.
655 thread[tid]->noSquashFromTC = true;
656 // Initialise the ThreadContext's memory proxies
657 thread[tid]->initMemProxies(thread[tid]->getTC());
658 }
659
641}
642
643template <class Impl>
644void
645FullO3CPU<Impl>::init()
646{
647 BaseCPU::init();
648

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655 for (ThreadID tid = 0; tid < numThreads; ++tid) {
656 // Set noSquashFromTC so that the CPU doesn't squash when initially
657 // setting up registers.
658 thread[tid]->noSquashFromTC = true;
659 // Initialise the ThreadContext's memory proxies
660 thread[tid]->initMemProxies(thread[tid]->getTC());
661 }
662
660 // this CPU could still be unconnected if we are restoring from a
661 // checkpoint and this CPU is to be switched in, thus we can only
662 // do this here if the instruction port is actually connected, if
663 // not we have to do it as part of takeOverFrom
664 if (icachePort.isConnected())
665 fetch.setIcache();
666
667 if (FullSystem && !params()->switched_out) {
668 for (ThreadID tid = 0; tid < numThreads; tid++) {
669 ThreadContext *src_tc = threadContexts[tid];
670 TheISA::initCPU(src_tc, src_tc->contextId());
671 }
672 }
673
674 // Clear noSquashFromTC.
675 for (int tid = 0; tid < numThreads; ++tid)
676 thread[tid]->noSquashFromTC = false;
677
678 commit.setThreads(thread);
679}
680
681template <class Impl>
682void
683FullO3CPU<Impl>::startup()
684{
685 fetch.startupStage();
663 if (FullSystem && !params()->switched_out) {
664 for (ThreadID tid = 0; tid < numThreads; tid++) {
665 ThreadContext *src_tc = threadContexts[tid];
666 TheISA::initCPU(src_tc, src_tc->contextId());
667 }
668 }
669
670 // Clear noSquashFromTC.
671 for (int tid = 0; tid < numThreads; ++tid)
672 thread[tid]->noSquashFromTC = false;
673
674 commit.setThreads(thread);
675}
676
677template <class Impl>
678void
679FullO3CPU<Impl>::startup()
680{
681 fetch.startupStage();
682 decode.startupStage();
686 iew.startupStage();
687 rename.startupStage();
688 commit.startupStage();
689}
690
691template <class Impl>
692void
693FullO3CPU<Impl>::activateThread(ThreadID tid)
694{
695 list<ThreadID>::iterator isActive =
696 std::find(activeThreads.begin(), activeThreads.end(), tid);
697
698 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
683 iew.startupStage();
684 rename.startupStage();
685 commit.startupStage();
686}
687
688template <class Impl>
689void
690FullO3CPU<Impl>::activateThread(ThreadID tid)
691{
692 list<ThreadID>::iterator isActive =
693 std::find(activeThreads.begin(), activeThreads.end(), tid);
694
695 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
696 assert(!switchedOut());
699
700 if (isActive == activeThreads.end()) {
701 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
702 tid);
703
704 activeThreads.push_back(tid);
705 }
706}
707
708template <class Impl>
709void
710FullO3CPU<Impl>::deactivateThread(ThreadID tid)
711{
712 //Remove From Active List, if Active
713 list<ThreadID>::iterator thread_it =
714 std::find(activeThreads.begin(), activeThreads.end(), tid);
715
716 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
697
698 if (isActive == activeThreads.end()) {
699 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
700 tid);
701
702 activeThreads.push_back(tid);
703 }
704}
705
706template <class Impl>
707void
708FullO3CPU<Impl>::deactivateThread(ThreadID tid)
709{
710 //Remove From Active List, if Active
711 list<ThreadID>::iterator thread_it =
712 std::find(activeThreads.begin(), activeThreads.end(), tid);
713
714 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
715 assert(!switchedOut());
717
718 if (thread_it != activeThreads.end()) {
719 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
720 tid);
721 activeThreads.erase(thread_it);
722 }
723}
724

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747
748 return total;
749}
750
751template <class Impl>
752void
753FullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay)
754{
716
717 if (thread_it != activeThreads.end()) {
718 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
719 tid);
720 activeThreads.erase(thread_it);
721 }
722}
723

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746
747 return total;
748}
749
750template <class Impl>
751void
752FullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay)
753{
754 assert(!switchedOut());
755
755 // Needs to set each stage to running as well.
756 if (delay){
757 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
758 "on cycle %d\n", tid, clockEdge(delay));
759 scheduleActivateThreadEvent(tid, delay);
760 } else {
761 activateThread(tid);
762 }
763
756 // Needs to set each stage to running as well.
757 if (delay){
758 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
759 "on cycle %d\n", tid, clockEdge(delay));
760 scheduleActivateThreadEvent(tid, delay);
761 } else {
762 activateThread(tid);
763 }
764
765 // We don't want to wake the CPU if it is drained. In that case,
766 // we just want to flag the thread as active and schedule the tick
767 // event from drainResume() instead.
768 if (getDrainState() == Drainable::Drained)
769 return;
770
764 // If we are time 0 or if the last activation time is in the past,
765 // schedule the next tick and wake up the fetch unit
766 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
767 scheduleTickEvent(delay);
768
769 // Be sure to signal that there's some activity so the CPU doesn't
770 // deschedule itself.
771 activityRec.activity();

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802 }
803}
804
805template <class Impl>
806void
807FullO3CPU<Impl>::suspendContext(ThreadID tid)
808{
809 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
771 // If we are time 0 or if the last activation time is in the past,
772 // schedule the next tick and wake up the fetch unit
773 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
774 scheduleTickEvent(delay);
775
776 // Be sure to signal that there's some activity so the CPU doesn't
777 // deschedule itself.
778 activityRec.activity();

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809 }
810}
811
812template <class Impl>
813void
814FullO3CPU<Impl>::suspendContext(ThreadID tid)
815{
816 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
817 assert(!switchedOut());
810 bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1));
811 // If this was the last thread then unschedule the tick event.
812 if ((activeThreads.size() == 1 && !deallocated) ||
813 activeThreads.size() == 0)
814 unscheduleTickEvent();
815
816 DPRINTF(Quiesce, "Suspending Context\n");
817 lastRunningCycle = curCycle();
818 _status = Idle;
819}
820
821template <class Impl>
822void
823FullO3CPU<Impl>::haltContext(ThreadID tid)
824{
825 //For now, this is the same as deallocate
826 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
818 bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1));
819 // If this was the last thread then unschedule the tick event.
820 if ((activeThreads.size() == 1 && !deallocated) ||
821 activeThreads.size() == 0)
822 unscheduleTickEvent();
823
824 DPRINTF(Quiesce, "Suspending Context\n");
825 lastRunningCycle = curCycle();
826 _status = Idle;
827}
828
829template <class Impl>
830void
831FullO3CPU<Impl>::haltContext(ThreadID tid)
832{
833 //For now, this is the same as deallocate
834 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
835 assert(!switchedOut());
827 scheduleDeallocateContext(tid, true, Cycles(1));
828}
829
830template <class Impl>
831void
832FullO3CPU<Impl>::insertThread(ThreadID tid)
833{
834 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");

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1115 activateThread(i);
1116 }
1117}
1118
1119template <class Impl>
1120unsigned int
1121FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1122{
836 scheduleDeallocateContext(tid, true, Cycles(1));
837}
838
839template <class Impl>
840void
841FullO3CPU<Impl>::insertThread(ThreadID tid)
842{
843 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");

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1124 activateThread(i);
1125 }
1126}
1127
1128template <class Impl>
1129unsigned int
1130FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1131{
1123 DPRINTF(O3CPU, "Switching out\n");
1124
1125 // If the CPU isn't doing anything, then return immediately.
1132 // If the CPU isn't doing anything, then return immediately.
1126 if (_status == SwitchedOut)
1133 if (switchedOut()) {
1134 setDrainState(Drainable::Drained);
1127 return 0;
1135 return 0;
1136 }
1128
1137
1129 drainCount = 0;
1130 fetch.drain();
1131 decode.drain();
1132 rename.drain();
1133 iew.drain();
1138 DPRINTF(Drain, "Draining...\n");
1139 setDrainState(Drainable::Draining);
1140
1141 // We only need to signal a drain to the commit stage as this
1142 // initiates squashing controls the draining. Once the commit
1143 // stage commits an instruction where it is safe to stop, it'll
1144 // squash the rest of the instructions in the pipeline and force
1145 // the fetch stage to stall. The pipeline will be drained once all
1146 // in-flight instructions have retired.
1134 commit.drain();
1135
1136 // Wake the CPU and record activity so everything can drain out if
1137 // the CPU was not able to immediately drain.
1147 commit.drain();
1148
1149 // Wake the CPU and record activity so everything can drain out if
1150 // the CPU was not able to immediately drain.
1138 if (getDrainState() != Drainable::Drained) {
1139 // A bit of a hack...set the drainManager after all the drain()
1140 // calls have been made, that way if all of the stages drain
1141 // immediately, the signalDrained() function knows not to call
1142 // process on the drain event.
1151 if (!isDrained()) {
1143 drainManager = drain_manager;
1144
1145 wakeCPU();
1146 activityRec.activity();
1147
1148 DPRINTF(Drain, "CPU not drained\n");
1149
1150 return 1;
1151 } else {
1152 drainManager = drain_manager;
1153
1154 wakeCPU();
1155 activityRec.activity();
1156
1157 DPRINTF(Drain, "CPU not drained\n");
1158
1159 return 1;
1160 } else {
1161 setDrainState(Drainable::Drained);
1162 DPRINTF(Drain, "CPU is already drained\n");
1163 if (tickEvent.scheduled())
1164 deschedule(tickEvent);
1165
1166 // Flush out any old data from the time buffers. In
1167 // particular, there might be some data in flight from the
1168 // fetch stage that isn't visible in any of the CPU buffers we
1169 // test in isDrained().
1170 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1171 timeBuffer.advance();
1172 fetchQueue.advance();
1173 decodeQueue.advance();
1174 renameQueue.advance();
1175 iewQueue.advance();
1176 }
1177
1178 drainSanityCheck();
1152 return 0;
1153 }
1154}
1155
1156template <class Impl>
1179 return 0;
1180 }
1181}
1182
1183template <class Impl>
1184bool
1185FullO3CPU<Impl>::tryDrain()
1186{
1187 if (!drainManager || !isDrained())
1188 return false;
1189
1190 if (tickEvent.scheduled())
1191 deschedule(tickEvent);
1192
1193 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1194 drainManager->signalDrainDone();
1195 drainManager = NULL;
1196
1197 return true;
1198}
1199
1200template <class Impl>
1157void
1201void
1158FullO3CPU<Impl>::drainResume()
1202FullO3CPU<Impl>::drainSanityCheck() const
1159{
1203{
1160 fetch.resume();
1161 decode.resume();
1162 rename.resume();
1163 iew.resume();
1164 commit.resume();
1204 assert(isDrained());
1205 fetch.drainSanityCheck();
1206 decode.drainSanityCheck();
1207 rename.drainSanityCheck();
1208 iew.drainSanityCheck();
1209 commit.drainSanityCheck();
1210}
1165
1211
1166 setDrainState(Drainable::Running);
1212template <class Impl>
1213bool
1214FullO3CPU<Impl>::isDrained() const
1215{
1216 bool drained(true);
1167
1217
1168 if (_status == SwitchedOut)
1169 return;
1218 for (ThreadID i = 0; i < thread.size(); ++i) {
1219 if (activateThreadEvent[i].scheduled()) {
1220 DPRINTF(Drain, "CPU not drained, tread %i has a "
1221 "pending activate event\n", i);
1222 drained = false;
1223 }
1224 if (deallocateContextEvent[i].scheduled()) {
1225 DPRINTF(Drain, "CPU not drained, tread %i has a "
1226 "pending deallocate context event\n", i);
1227 drained = false;
1228 }
1229 }
1170
1230
1171 if (system->getMemoryMode() != Enums::timing) {
1172 fatal("The O3 CPU requires the memory system to be in "
1173 "'timing' mode.\n");
1231 if (!instList.empty() || !removeList.empty()) {
1232 DPRINTF(Drain, "Main CPU structures not drained.\n");
1233 drained = false;
1174 }
1175
1234 }
1235
1176 if (!tickEvent.scheduled())
1177 schedule(tickEvent, nextCycle());
1178 _status = Running;
1236 if (!fetch.isDrained()) {
1237 DPRINTF(Drain, "Fetch not drained.\n");
1238 drained = false;
1239 }
1240
1241 if (!decode.isDrained()) {
1242 DPRINTF(Drain, "Decode not drained.\n");
1243 drained = false;
1244 }
1245
1246 if (!rename.isDrained()) {
1247 DPRINTF(Drain, "Rename not drained.\n");
1248 drained = false;
1249 }
1250
1251 if (!iew.isDrained()) {
1252 DPRINTF(Drain, "IEW not drained.\n");
1253 drained = false;
1254 }
1255
1256 if (!commit.isDrained()) {
1257 DPRINTF(Drain, "Commit not drained.\n");
1258 drained = false;
1259 }
1260
1261 return drained;
1179}
1180
1181template <class Impl>
1182void
1262}
1263
1264template <class Impl>
1265void
1183FullO3CPU<Impl>::signalDrained()
1266FullO3CPU<Impl>::commitDrained(ThreadID tid)
1184{
1267{
1185 if (++drainCount == NumStages) {
1186 if (tickEvent.scheduled())
1187 tickEvent.squash();
1268 fetch.drainStall(tid);
1269}
1188
1270
1189 setDrainState(Drainable::Drained);
1271template <class Impl>
1272void
1273FullO3CPU<Impl>::drainResume()
1274{
1275 setDrainState(Drainable::Running);
1276 if (switchedOut())
1277 return;
1190
1278
1191 if (drainManager) {
1192 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1193 drainManager->signalDrainDone();
1194 drainManager = NULL;
1279 DPRINTF(Drain, "Resuming...\n");
1280
1281 if (system->getMemoryMode() != Enums::timing) {
1282 fatal("The O3 CPU requires the memory system to be in "
1283 "'timing' mode.\n");
1284 }
1285
1286 fetch.drainResume();
1287 commit.drainResume();
1288
1289 _status = Idle;
1290 for (ThreadID i = 0; i < thread.size(); i++) {
1291 if (thread[i]->status() == ThreadContext::Active) {
1292 DPRINTF(Drain, "Activating thread: %i\n", i);
1293 activateThread(i);
1294 _status = Running;
1195 }
1196 }
1295 }
1296 }
1197 assert(drainCount <= 5);
1297
1298 assert(!tickEvent.scheduled());
1299 if (_status == Running)
1300 schedule(tickEvent, nextCycle());
1198}
1199
1200template <class Impl>
1201void
1202FullO3CPU<Impl>::switchOut()
1203{
1301}
1302
1303template <class Impl>
1304void
1305FullO3CPU<Impl>::switchOut()
1306{
1307 DPRINTF(O3CPU, "Switching out\n");
1204 BaseCPU::switchOut();
1205
1308 BaseCPU::switchOut();
1309
1206 fetch.switchOut();
1207 rename.switchOut();
1208 iew.switchOut();
1209 commit.switchOut();
1210 instList.clear();
1211 while (!removeList.empty()) {
1212 removeList.pop();
1213 }
1310 activityRec.reset();
1214
1215 _status = SwitchedOut;
1216
1217 if (checker)
1218 checker->switchOut();
1311
1312 _status = SwitchedOut;
1313
1314 if (checker)
1315 checker->switchOut();
1219
1220 if (tickEvent.scheduled())
1221 tickEvent.squash();
1222}
1223
1224template <class Impl>
1225void
1226FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1227{
1316}
1317
1318template <class Impl>
1319void
1320FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1321{
1228 // Flush out any old data from the time buffers.
1229 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1230 timeBuffer.advance();
1231 fetchQueue.advance();
1232 decodeQueue.advance();
1233 renameQueue.advance();
1234 iewQueue.advance();
1235 }
1236
1237 activityRec.reset();
1238
1239 BaseCPU::takeOverFrom(oldCPU);
1240
1241 fetch.takeOverFrom();
1242 decode.takeOverFrom();
1243 rename.takeOverFrom();
1244 iew.takeOverFrom();
1245 commit.takeOverFrom();
1246
1322 BaseCPU::takeOverFrom(oldCPU);
1323
1324 fetch.takeOverFrom();
1325 decode.takeOverFrom();
1326 rename.takeOverFrom();
1327 iew.takeOverFrom();
1328 commit.takeOverFrom();
1329
1247 assert(!tickEvent.scheduled() || tickEvent.squashed());
1330 assert(!tickEvent.scheduled());
1248
1249 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1250 if (oldO3CPU)
1251 globalSeqNum = oldO3CPU->globalSeqNum;
1252
1331
1332 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1333 if (oldO3CPU)
1334 globalSeqNum = oldO3CPU->globalSeqNum;
1335
1253 // @todo: Figure out how to properly select the tid to put onto
1254 // the active threads list.
1255 ThreadID tid = 0;
1256
1257 list<ThreadID>::iterator isActive =
1258 std::find(activeThreads.begin(), activeThreads.end(), tid);
1259
1260 if (isActive == activeThreads.end()) {
1261 //May Need to Re-code this if the delay variable is the delay
1262 //needed for thread to activate
1263 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1264 tid);
1265
1266 activeThreads.push_back(tid);
1267 }
1268
1269 // Set all statuses to active, schedule the CPU's tick event.
1270 // @todo: Fix up statuses so this is handled properly
1271 ThreadID size = threadContexts.size();
1272 for (ThreadID i = 0; i < size; ++i) {
1273 ThreadContext *tc = threadContexts[i];
1274 if (tc->status() == ThreadContext::Active && _status != Running) {
1275 _status = Running;
1276 reschedule(tickEvent, nextCycle(), true);
1277 }
1278 }
1279 if (!tickEvent.scheduled())
1280 schedule(tickEvent, nextCycle());
1281
1282 lastRunningCycle = curCycle();
1336 lastRunningCycle = curCycle();
1337 _status = Idle;
1283}
1284
1285template <class Impl>
1286TheISA::MiscReg
1287FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1288{
1289 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1290}

--- 459 unchanged lines hidden --- 		1338}
1339
1340template <class Impl>
1341TheISA::MiscReg
1342FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1343{
1344 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1345}

--- 459 unchanged lines hidden ---