cpu.cc (9382:1c97b57d5169) cpu.cc (9384:877293183bdf)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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236 params->numThreads),
237
238 scoreboard(params->numThreads,
239 TheISA::NumIntRegs, params->numPhysIntRegs,
240 TheISA::NumFloatRegs, params->numPhysFloatRegs,
241 TheISA::NumMiscRegs * numThreads,
242 TheISA::ZeroReg),
243
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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236 params->numThreads),
237
238 scoreboard(params->numThreads,
239 TheISA::NumIntRegs, params->numPhysIntRegs,
240 TheISA::NumFloatRegs, params->numPhysFloatRegs,
241 TheISA::NumMiscRegs * numThreads,
242 TheISA::ZeroReg),
243
244 isa(numThreads, NULL),
245
244 icachePort(&fetch, this),
245 dcachePort(&iew.ldstQueue, this),
246
247 timeBuffer(params->backComSize, params->forwardComSize),
248 fetchQueue(params->backComSize, params->forwardComSize),
249 decodeQueue(params->backComSize, params->forwardComSize),
250 renameQueue(params->backComSize, params->forwardComSize),
251 iewQueue(params->backComSize, params->forwardComSize),

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335
336 // Setup the rename map for whichever stages need it.
337 PhysRegIndex lreg_idx = 0;
338 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
339
340 for (ThreadID tid = 0; tid < numThreads; tid++) {
341 bool bindRegs = (tid <= active_threads - 1);
342
246 icachePort(&fetch, this),
247 dcachePort(&iew.ldstQueue, this),
248
249 timeBuffer(params->backComSize, params->forwardComSize),
250 fetchQueue(params->backComSize, params->forwardComSize),
251 decodeQueue(params->backComSize, params->forwardComSize),
252 renameQueue(params->backComSize, params->forwardComSize),
253 iewQueue(params->backComSize, params->forwardComSize),

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337
338 // Setup the rename map for whichever stages need it.
339 PhysRegIndex lreg_idx = 0;
340 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
341
342 for (ThreadID tid = 0; tid < numThreads; tid++) {
343 bool bindRegs = (tid <= active_threads - 1);
344
345 isa[tid] = params->isa[tid];
346
343 commitRenameMap[tid].init(TheISA::NumIntRegs,
344 params->numPhysIntRegs,
345 lreg_idx, //Index for Logical. Regs
346
347 TheISA::NumFloatRegs,
348 params->numPhysFloatRegs,
349 freg_idx, //Index for Float Regs
350

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1280
1281 lastRunningCycle = curCycle();
1282}
1283
1284template <class Impl>
1285TheISA::MiscReg
1286FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1287{
347 commitRenameMap[tid].init(TheISA::NumIntRegs,
348 params->numPhysIntRegs,
349 lreg_idx, //Index for Logical. Regs
350
351 TheISA::NumFloatRegs,
352 params->numPhysFloatRegs,
353 freg_idx, //Index for Float Regs
354

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1284
1285 lastRunningCycle = curCycle();
1286}
1287
1288template <class Impl>
1289TheISA::MiscReg
1290FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1291{
1288 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1292 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1289}
1290
1291template <class Impl>
1292TheISA::MiscReg
1293FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1294{
1295 miscRegfileReads++;
1293}
1294
1295template <class Impl>
1296TheISA::MiscReg
1297FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1298{
1299 miscRegfileReads++;
1296 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1300 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1297}
1298
1299template <class Impl>
1300void
1301FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1302 const TheISA::MiscReg &val, ThreadID tid)
1303{
1301}
1302
1303template <class Impl>
1304void
1305FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1306 const TheISA::MiscReg &val, ThreadID tid)
1307{
1304 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1308 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1305}
1306
1307template <class Impl>
1308void
1309FullO3CPU<Impl>::setMiscReg(int misc_reg,
1310 const TheISA::MiscReg &val, ThreadID tid)
1311{
1312 miscRegfileWrites++;
1309}
1310
1311template <class Impl>
1312void
1313FullO3CPU<Impl>::setMiscReg(int misc_reg,
1314 const TheISA::MiscReg &val, ThreadID tid)
1315{
1316 miscRegfileWrites++;
1313 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1317 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1314}
1315
1316template <class Impl>
1317uint64_t
1318FullO3CPU<Impl>::readIntReg(int reg_idx)
1319{
1320 intRegfileReads++;
1321 return regFile.readIntReg(reg_idx);

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1319
1320template <class Impl>
1321uint64_t
1322FullO3CPU<Impl>::readIntReg(int reg_idx)
1323{
1324 intRegfileReads++;
1325 return regFile.readIntReg(reg_idx);

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