cpu.cc (8975:7f36d4436074) cpu.cc (9152:86c0e6ca5e7c)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50#include "cpu/o3/cpu.hh"
51#include "cpu/o3/isa_specific.hh"
52#include "cpu/o3/thread_context.hh"
53#include "cpu/activity.hh"
54#include "cpu/quiesce_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/thread_context.hh"
57#include "debug/Activity.hh"
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50#include "cpu/o3/cpu.hh"
51#include "cpu/o3/isa_specific.hh"
52#include "cpu/o3/thread_context.hh"
53#include "cpu/activity.hh"
54#include "cpu/quiesce_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/thread_context.hh"
57#include "debug/Activity.hh"
58#include "debug/Drain.hh"
58#include "debug/O3CPU.hh"
59#include "debug/Quiesce.hh"
60#include "enums/MemoryMode.hh"
61#include "sim/core.hh"
62#include "sim/full_system.hh"
63#include "sim/process.hh"
64#include "sim/stat_control.hh"
65#include "sim/system.hh"

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255 globalSeqNum(1),
256 system(params->system),
257 drainCount(0),
258 deferRegistration(params->defer_registration)
259{
260 if (!deferRegistration) {
261 _status = Running;
262 } else {
59#include "debug/O3CPU.hh"
60#include "debug/Quiesce.hh"
61#include "enums/MemoryMode.hh"
62#include "sim/core.hh"
63#include "sim/full_system.hh"
64#include "sim/process.hh"
65#include "sim/stat_control.hh"
66#include "sim/system.hh"

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256 globalSeqNum(1),
257 system(params->system),
258 drainCount(0),
259 deferRegistration(params->defer_registration)
260{
261 if (!deferRegistration) {
262 _status = Running;
263 } else {
263 _status = Idle;
264 _status = SwitchedOut;
264 }
265
266 if (params->checker) {
267 BaseCPU *temp_checker = params->checker;
268 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
269 checker->setIcachePort(&icachePort);
270 checker->setSystem(params->system);
271 } else {

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1114
1115template <class Impl>
1116unsigned int
1117FullO3CPU<Impl>::drain(Event *drain_event)
1118{
1119 DPRINTF(O3CPU, "Switching out\n");
1120
1121 // If the CPU isn't doing anything, then return immediately.
265 }
266
267 if (params->checker) {
268 BaseCPU *temp_checker = params->checker;
269 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
270 checker->setIcachePort(&icachePort);
271 checker->setSystem(params->system);
272 } else {

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1115
1116template <class Impl>
1117unsigned int
1118FullO3CPU<Impl>::drain(Event *drain_event)
1119{
1120 DPRINTF(O3CPU, "Switching out\n");
1121
1122 // If the CPU isn't doing anything, then return immediately.
1122 if (_status == Idle || _status == SwitchedOut) {
1123 if (_status == SwitchedOut)
1123 return 0;
1124 return 0;
1124 }
1125
1126 drainCount = 0;
1127 fetch.drain();
1128 decode.drain();
1129 rename.drain();
1130 iew.drain();
1131 commit.drain();
1132

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1137 // calls have been made, that way if all of the stages drain
1138 // immediately, the signalDrained() function knows not to call
1139 // process on the drain event.
1140 drainEvent = drain_event;
1141
1142 wakeCPU();
1143 activityRec.activity();
1144
1125
1126 drainCount = 0;
1127 fetch.drain();
1128 decode.drain();
1129 rename.drain();
1130 iew.drain();
1131 commit.drain();
1132

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1137 // calls have been made, that way if all of the stages drain
1138 // immediately, the signalDrained() function knows not to call
1139 // process on the drain event.
1140 drainEvent = drain_event;
1141
1142 wakeCPU();
1143 activityRec.activity();
1144
1145 DPRINTF(Drain, "CPU not drained\n");
1146
1145 return 1;
1146 } else {
1147 return 0;
1148 }
1149}
1150
1151template <class Impl>
1152void
1153FullO3CPU<Impl>::resume()
1154{
1155 fetch.resume();
1156 decode.resume();
1157 rename.resume();
1158 iew.resume();
1159 commit.resume();
1160
1161 changeState(SimObject::Running);
1162
1147 return 1;
1148 } else {
1149 return 0;
1150 }
1151}
1152
1153template <class Impl>
1154void
1155FullO3CPU<Impl>::resume()
1156{
1157 fetch.resume();
1158 decode.resume();
1159 rename.resume();
1160 iew.resume();
1161 commit.resume();
1162
1163 changeState(SimObject::Running);
1164
1163 if (_status == SwitchedOut || _status == Idle)
1165 if (_status == SwitchedOut)
1164 return;
1165
1166 assert(system->getMemoryMode() == Enums::timing);
1167
1168 if (!tickEvent.scheduled())
1169 schedule(tickEvent, nextCycle());
1170 _status = Running;
1171}

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1178 if (tickEvent.scheduled())
1179 tickEvent.squash();
1180
1181 changeState(SimObject::Drained);
1182
1183 BaseCPU::switchOut();
1184
1185 if (drainEvent) {
1166 return;
1167
1168 assert(system->getMemoryMode() == Enums::timing);
1169
1170 if (!tickEvent.scheduled())
1171 schedule(tickEvent, nextCycle());
1172 _status = Running;
1173}

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1180 if (tickEvent.scheduled())
1181 tickEvent.squash();
1182
1183 changeState(SimObject::Drained);
1184
1185 BaseCPU::switchOut();
1186
1187 if (drainEvent) {
1188 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1186 drainEvent->process();
1187 drainEvent = NULL;
1188 }
1189 }
1190 assert(drainCount <= 5);
1191}
1192
1193template <class Impl>

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1232 fetch.takeOverFrom();
1233 decode.takeOverFrom();
1234 rename.takeOverFrom();
1235 iew.takeOverFrom();
1236 commit.takeOverFrom();
1237
1238 assert(!tickEvent.scheduled() || tickEvent.squashed());
1239
1189 drainEvent->process();
1190 drainEvent = NULL;
1191 }
1192 }
1193 assert(drainCount <= 5);
1194}
1195
1196template <class Impl>

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1235 fetch.takeOverFrom();
1236 decode.takeOverFrom();
1237 rename.takeOverFrom();
1238 iew.takeOverFrom();
1239 commit.takeOverFrom();
1240
1241 assert(!tickEvent.scheduled() || tickEvent.squashed());
1242
1243 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1244 if (oldO3CPU)
1245 globalSeqNum = oldO3CPU->globalSeqNum;
1246
1240 // @todo: Figure out how to properly select the tid to put onto
1241 // the active threads list.
1242 ThreadID tid = 0;
1243
1244 list<ThreadID>::iterator isActive =
1245 std::find(activeThreads.begin(), activeThreads.end(), tid);
1246
1247 if (isActive == activeThreads.end()) {

--- 485 unchanged lines hidden --- 		1247 // @todo: Figure out how to properly select the tid to put onto
1248 // the active threads list.
1249 ThreadID tid = 0;
1250
1251 list<ThreadID>::iterator isActive =
1252 std::find(activeThreads.begin(), activeThreads.end(), tid);
1253
1254 if (isActive == activeThreads.end()) {

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