cpu.cc (8948:e95ee70f876c) cpu.cc (8975:7f36d4436074)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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82void
83BaseO3CPU::regStats()
84{
85 BaseCPU::regStats();
86}
87
88template<class Impl>
89bool
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 73 unchanged lines hidden (view full) ---

82void
83BaseO3CPU::regStats()
84{
85 BaseCPU::regStats();
86}
87
88template<class Impl>
89bool
90FullO3CPU::IcachePort::recvTiming(PacketPtr pkt)
90FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
91{
91{
92 assert(pkt->isResponse());
93 DPRINTF(O3CPU, "Fetch unit received timing\n");
94 // We shouldn't ever get a block in ownership state
95 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
96 fetch->processCacheCompletion(pkt);
97
98 return true;
99}
100
101template<class Impl>
102void
103FullO3CPU<Impl>::IcachePort::recvRetry()
104{
105 fetch->recvRetry();
106}
107
108template <class Impl>
109bool
92 DPRINTF(O3CPU, "Fetch unit received timing\n");
93 // We shouldn't ever get a block in ownership state
94 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
95 fetch->processCacheCompletion(pkt);
96
97 return true;
98}
99
100template<class Impl>
101void
102FullO3CPU<Impl>::IcachePort::recvRetry()
103{
104 fetch->recvRetry();
105}
106
107template <class Impl>
108bool
110FullO3CPU::DcachePort::recvTiming(PacketPtr pkt)
109FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
111{
110{
112 assert(pkt->isResponse());
113 return lsq->recvTiming(pkt);
111 return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
112}
113
114template <class Impl>
117bool
118FullO3CPU::DcachePort::recvTimingSnoop(PacketPtr pkt)
115void
116FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
117{
120 assert(pkt->isRequest());
121 return lsq->recvTimingSnoop(pkt);
118 lsq->recvTimingSnoopReq(pkt);
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DcachePort::recvRetry()
127{
128 lsq->recvRetry();
129}

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120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125 lsq->recvRetry();
126}

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