cpu.cc (8921:e53972f72165) cpu.cc (8948:e95ee70f876c)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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84{
85 BaseCPU::regStats();
86}
87
88template<class Impl>
89bool
90FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
91{
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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84{
85 BaseCPU::regStats();
86}
87
88template<class Impl>
89bool
90FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
91{
92 assert(pkt->isResponse());
92 DPRINTF(O3CPU, "Fetch unit received timing\n");
93 DPRINTF(O3CPU, "Fetch unit received timing\n");
93 if (pkt->isResponse()) {
94 // We shouldn't ever get a block in ownership state
95 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
94 // We shouldn't ever get a block in ownership state
95 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
96 fetch->processCacheCompletion(pkt);
96
97
97 fetch->processCacheCompletion(pkt);
98 }
99 //else Snooped a coherence request, just return
100 return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvRetry()
106{
107 fetch->recvRetry();
108}
109
110template <class Impl>
111bool
112FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
113{
98 return true;
99}
100
101template<class Impl>
102void
103FullO3CPU<Impl>::IcachePort::recvRetry()
104{
105 fetch->recvRetry();
106}
107
108template <class Impl>
109bool
110FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
111{
112 assert(pkt->isResponse());
114 return lsq->recvTiming(pkt);
115}
116
117template <class Impl>
113 return lsq->recvTiming(pkt);
114}
115
116template <class Impl>
117bool
118FullO3CPU<Impl>::DcachePort::recvTimingSnoop(PacketPtr pkt)
119{
120 assert(pkt->isRequest());
121 return lsq->recvTimingSnoop(pkt);
122}
123
124template <class Impl>
118void
119FullO3CPU<Impl>::DcachePort::recvRetry()
120{
121 lsq->recvRetry();
122}
123
124template <class Impl>
125FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)

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126FullO3CPU<Impl>::DcachePort::recvRetry()
127{
128 lsq->recvRetry();
129}
130
131template <class Impl>
132FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)

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