cpu.cc (8876:44f8e7bb7fdf) cpu.cc (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
48#include "cpu/checker/cpu.hh"
49#include "cpu/checker/thread_context.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/quiesce_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Activity.hh"
57#include "debug/O3CPU.hh"
58#include "debug/Quiesce.hh"
59#include "enums/MemoryMode.hh"
60#include "sim/core.hh"
61#include "sim/full_system.hh"
62#include "sim/process.hh"
63#include "sim/stat_control.hh"
64#include "sim/system.hh"
65
50#include "cpu/o3/cpu.hh"
51#include "cpu/o3/isa_specific.hh"
52#include "cpu/o3/thread_context.hh"
53#include "cpu/activity.hh"
54#include "cpu/quiesce_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/thread_context.hh"
57#include "debug/Activity.hh"
58#include "debug/O3CPU.hh"
59#include "debug/Quiesce.hh"
60#include "enums/MemoryMode.hh"
61#include "sim/core.hh"
62#include "sim/full_system.hh"
63#include "sim/process.hh"
64#include "sim/stat_control.hh"
65#include "sim/system.hh"
66
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#include "cpu/checker/thread_context.hh"
69#endif
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;

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258 deferRegistration(params->defer_registration)
259{
260 if (!deferRegistration) {
261 _status = Running;
262 } else {
263 _status = Idle;
264 }
265
67#if THE_ISA == ALPHA_ISA
68#include "arch/alpha/osfpal.hh"
69#include "debug/Activity.hh"
70#endif
71
72struct BaseCPUParams;
73
74using namespace TheISA;

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254 deferRegistration(params->defer_registration)
255{
256 if (!deferRegistration) {
257 _status = Running;
258 } else {
259 _status = Idle;
260 }
261
266#if USE_CHECKER
267 if (params->checker) {
268 BaseCPU *temp_checker = params->checker;
269 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
270 checker->setIcachePort(&icachePort);
271 checker->setSystem(params->system);
272 } else {
273 checker = NULL;
274 }
262 if (params->checker) {
263 BaseCPU *temp_checker = params->checker;
264 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
265 checker->setIcachePort(&icachePort);
266 checker->setSystem(params->system);
267 } else {
268 checker = NULL;
269 }
275#endif // USE_CHECKER
276
277 if (!FullSystem) {
278 thread.resize(numThreads);
279 tids.resize(numThreads);
280 }
281
282 // The stages also need their CPU pointer setup. However this
283 // must be done at the upper level CPU because they have pointers

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433
434 // Setup the TC that will serve as the interface to the threads/CPU.
435 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
436
437 tc = o3_tc;
438
439 // If we're using a checker, then the TC should be the
440 // CheckerThreadContext.
270
271 if (!FullSystem) {
272 thread.resize(numThreads);
273 tids.resize(numThreads);
274 }
275
276 // The stages also need their CPU pointer setup. However this
277 // must be done at the upper level CPU because they have pointers

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427
428 // Setup the TC that will serve as the interface to the threads/CPU.
429 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
430
431 tc = o3_tc;
432
433 // If we're using a checker, then the TC should be the
434 // CheckerThreadContext.
441#if USE_CHECKER
442 if (params->checker) {
443 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444 o3_tc, this->checker);
445 }
435 if (params->checker) {
436 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
437 o3_tc, this->checker);
438 }
446#endif
447
448 o3_tc->cpu = (typename Impl::O3CPU *)(this);
449 assert(o3_tc->cpu);
450 o3_tc->thread = this->thread[tid];
451
452 if (FullSystem) {
453 // Setup quiesce event.
454 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);

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1202 iew.switchOut();
1203 commit.switchOut();
1204 instList.clear();
1205 while (!removeList.empty()) {
1206 removeList.pop();
1207 }
1208
1209 _status = SwitchedOut;
439
440 o3_tc->cpu = (typename Impl::O3CPU *)(this);
441 assert(o3_tc->cpu);
442 o3_tc->thread = this->thread[tid];
443
444 if (FullSystem) {
445 // Setup quiesce event.
446 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);

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1194 iew.switchOut();
1195 commit.switchOut();
1196 instList.clear();
1197 while (!removeList.empty()) {
1198 removeList.pop();
1199 }
1200
1201 _status = SwitchedOut;
1210#if USE_CHECKER
1202
1211 if (checker)
1212 checker->switchOut();
1203 if (checker)
1204 checker->switchOut();
1213#endif
1205
1214 if (tickEvent.scheduled())
1215 tickEvent.squash();
1216}
1217
1218template <class Impl>
1219void
1220FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1221{

--- 514 unchanged lines hidden --- 		1206 if (tickEvent.scheduled())
1207 tickEvent.squash();
1208}
1209
1210template <class Impl>
1211void
1212FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1213{

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