cpu.cc (8834:21e8d54ecf07) cpu.cc (8850:ed91b534ed04)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 564 unchanged lines hidden (view full) ---

573
574 miscRegfileWrites
575 .name(name() + ".misc_regfile_writes")
576 .desc("number of misc regfile writes")
577 .prereq(miscRegfileWrites);
578}
579
580template <class Impl>
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 564 unchanged lines hidden (view full) ---

573
574 miscRegfileWrites
575 .name(name() + ".misc_regfile_writes")
576 .desc("number of misc regfile writes")
577 .prereq(miscRegfileWrites);
578}
579
580template <class Impl>
581Port *
582FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
583{
584 if (if_name == "dcache_port")
585 return &dcachePort;
586 else if (if_name == "icache_port")
587 return &icachePort;
588 else
589 panic("No Such Port\n");
590}
591
592template <class Impl>
593void
594FullO3CPU<Impl>::tick()
595{
596 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
597
598 ++numCycles;
599
600// activity = false;

--- 1141 unchanged lines hidden --- 		581void
582FullO3CPU<Impl>::tick()
583{
584 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
585
586 ++numCycles;
587
588// activity = false;

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