cpu.cc (8777:dd43f1c9fa0a) cpu.cc (8779:2a590c51adb1)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
34#include "arch/kernel_stats.hh"
34#include "config/full_system.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
35#include "config/full_system.hh"
36#include "config/the_isa.hh"
37#include "config/use_checker.hh"
38#include "cpu/o3/cpu.hh"
39#include "cpu/o3/isa_specific.hh"
40#include "cpu/o3/thread_context.hh"
41#include "cpu/activity.hh"
42#include "cpu/quiesce_event.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Activity.hh"
44#include "debug/O3CPU.hh"
45#include "debug/Quiesce.hh"
46#include "enums/MemoryMode.hh"
47#include "sim/core.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "debug/Activity.hh"
46#include "debug/O3CPU.hh"
47#include "debug/Quiesce.hh"
48#include "enums/MemoryMode.hh"
49#include "sim/core.hh"
50#include "sim/process.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51#include "sim/stat_control.hh"
52#include "sim/system.hh"
53
51#if FULL_SYSTEM
52#include "cpu/quiesce_event.hh"
53#else
54#include "sim/process.hh"
55#endif
56
57#if USE_CHECKER
58#include "cpu/checker/cpu.hh"
59#endif
60
61#if THE_ISA == ALPHA_ISA
62#include "arch/alpha/osfpal.hh"
63#include "debug/Activity.hh"
64#endif

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891 contextSwitch = true;
892
893 //@todo: dont always add to waitlist
894 //do waitlist
895 cpuWaitList.push_back(tid);
896 }
897}
898
54#if USE_CHECKER
55#include "cpu/checker/cpu.hh"
56#endif
57
58#if THE_ISA == ALPHA_ISA
59#include "arch/alpha/osfpal.hh"
60#include "debug/Activity.hh"
61#endif

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888 contextSwitch = true;
889
890 //@todo: dont always add to waitlist
891 //do waitlist
892 cpuWaitList.push_back(tid);
893 }
894}
895
899#if FULL_SYSTEM
900template <class Impl>
901Fault
902FullO3CPU<Impl>::hwrei(ThreadID tid)
903{
904#if THE_ISA == ALPHA_ISA
905 // Need to clear the lock flag upon returning from an interrupt.
906 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
907

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968FullO3CPU<Impl>::updateMemPorts()
969{
970 // Update all ThreadContext's memory ports (Functional/Virtual
971 // Ports)
972 ThreadID size = thread.size();
973 for (ThreadID i = 0; i < size; ++i)
974 thread[i]->connectMemPorts(thread[i]->getTC());
975}
896template <class Impl>
897Fault
898FullO3CPU<Impl>::hwrei(ThreadID tid)
899{
900#if THE_ISA == ALPHA_ISA
901 // Need to clear the lock flag upon returning from an interrupt.
902 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
903

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964FullO3CPU<Impl>::updateMemPorts()
965{
966 // Update all ThreadContext's memory ports (Functional/Virtual
967 // Ports)
968 ThreadID size = thread.size();
969 for (ThreadID i = 0; i < size; ++i)
970 thread[i]->connectMemPorts(thread[i]->getTC());
971}
976#endif
977
978template <class Impl>
979void
980FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
981{
982 // Pass the thread's TC into the invoke method.
983 fault->invoke(this->threadContexts[tid], inst);
984}

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1589 DPRINTF(Activity, "Waking up CPU\n");
1590
1591 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1592 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1593
1594 schedule(tickEvent, nextCycle());
1595}
1596
972
973template <class Impl>
974void
975FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
976{
977 // Pass the thread's TC into the invoke method.
978 fault->invoke(this->threadContexts[tid], inst);
979}

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1584 DPRINTF(Activity, "Waking up CPU\n");
1585
1586 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1587 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1588
1589 schedule(tickEvent, nextCycle());
1590}
1591
1597#if FULL_SYSTEM
1598template <class Impl>
1599void
1600FullO3CPU<Impl>::wakeup()
1601{
1602 if (this->thread[0]->status() != ThreadContext::Suspended)
1603 return;
1604
1605 this->wakeCPU();
1606
1607 DPRINTF(Quiesce, "Suspended Processor woken\n");
1608 this->threadContexts[0]->activate();
1609}
1592template <class Impl>
1593void
1594FullO3CPU<Impl>::wakeup()
1595{
1596 if (this->thread[0]->status() != ThreadContext::Suspended)
1597 return;
1598
1599 this->wakeCPU();
1600
1601 DPRINTF(Quiesce, "Suspended Processor woken\n");
1602 this->threadContexts[0]->activate();
1603}
1610#endif
1611
1612template <class Impl>
1613ThreadID
1614FullO3CPU<Impl>::getFreeTid()
1615{
1616 for (ThreadID tid = 0; tid < numThreads; tid++) {
1617 if (!tids[tid]) {
1618 tids[tid] = true;

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1605template <class Impl>
1606ThreadID
1607FullO3CPU<Impl>::getFreeTid()
1608{
1609 for (ThreadID tid = 0; tid < numThreads; tid++) {
1610 if (!tids[tid]) {
1611 tids[tid] = true;

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