cpu.cc (8706:b1838faf3bcc) cpu.cc (8707:489489c67fd9)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

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74}
75
76void
77BaseO3CPU::regStats()
78{
79 BaseCPU::regStats();
80}
81
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;

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86}
87
88void
89BaseO3CPU::regStats()
90{
91 BaseCPU::regStats();
92}
93
94template<class Impl>
95bool
96FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
97{
98 DPRINTF(O3CPU, "Fetch unit received timing\n");
99 if (pkt->isResponse()) {
100 // We shouldn't ever get a block in ownership state
101 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
102
103 fetch->processCacheCompletion(pkt);
104 }
105 //else Snooped a coherence request, just return
106 return true;
107}
108
109template<class Impl>
110void
111FullO3CPU<Impl>::IcachePort::recvRetry()
112{
113 fetch->recvRetry();
114}
115
82template <class Impl>
116template <class Impl>
117bool
118FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
119{
120 return lsq->recvTiming(pkt);
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DcachePort::recvRetry()
126{
127 lsq->recvRetry();
128}
129
130template <class Impl>
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84 : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()

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189 params->numThreads),
190
191 scoreboard(params->numThreads,
192 TheISA::NumIntRegs, params->numPhysIntRegs,
193 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194 TheISA::NumMiscRegs * numThreads,
195 TheISA::ZeroReg),
196
131FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
132 : Event(CPU_Tick_Pri), cpu(c)
133{
134}
135
136template <class Impl>
137void
138FullO3CPU<Impl>::TickEvent::process()

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237 params->numThreads),
238
239 scoreboard(params->numThreads,
240 TheISA::NumIntRegs, params->numPhysIntRegs,
241 TheISA::NumFloatRegs, params->numPhysFloatRegs,
242 TheISA::NumMiscRegs * numThreads,
243 TheISA::ZeroReg),
244
245 icachePort(&fetch, this),
246 dcachePort(&iew.ldstQueue, this),
247
197 timeBuffer(params->backComSize, params->forwardComSize),
198 fetchQueue(params->backComSize, params->forwardComSize),
199 decodeQueue(params->backComSize, params->forwardComSize),
200 renameQueue(params->backComSize, params->forwardComSize),
201 iewQueue(params->backComSize, params->forwardComSize),
202 activityRec(name(), NumStages,
203 params->backComSize + params->forwardComSize,
204 params->activity),

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213 } else {
214 _status = Idle;
215 }
216
217#if USE_CHECKER
218 if (params->checker) {
219 BaseCPU *temp_checker = params->checker;
220 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
248 timeBuffer(params->backComSize, params->forwardComSize),
249 fetchQueue(params->backComSize, params->forwardComSize),
250 decodeQueue(params->backComSize, params->forwardComSize),
251 renameQueue(params->backComSize, params->forwardComSize),
252 iewQueue(params->backComSize, params->forwardComSize),
253 activityRec(name(), NumStages,
254 params->backComSize + params->forwardComSize,
255 params->activity),

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264 } else {
265 _status = Idle;
266 }
267
268#if USE_CHECKER
269 if (params->checker) {
270 BaseCPU *temp_checker = params->checker;
271 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
272 checker->setIcachePort(&icachePort);
221#if FULL_SYSTEM
222 checker->setSystem(params->system);
223#endif
224 } else {
225 checker = NULL;
226 }
227#endif // USE_CHECKER
228

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523 .prereq(miscRegfileWrites);
524}
525
526template <class Impl>
527Port *
528FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
529{
530 if (if_name == "dcache_port")
273#if FULL_SYSTEM
274 checker->setSystem(params->system);
275#endif
276 } else {
277 checker = NULL;
278 }
279#endif // USE_CHECKER
280

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575 .prereq(miscRegfileWrites);
576}
577
578template <class Impl>
579Port *
580FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
581{
582 if (if_name == "dcache_port")
531 return iew.getDcachePort();
583 return &dcachePort;
532 else if (if_name == "icache_port")
584 else if (if_name == "icache_port")
533 return fetch.getIcachePort();
585 return &icachePort;
534 else
535 panic("No Such Port\n");
536}
537
538template <class Impl>
539void
540FullO3CPU<Impl>::tick()
541{

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601{
602 BaseCPU::init();
603
604 // Set inSyscall so that the CPU doesn't squash when initially
605 // setting up registers.
606 for (ThreadID tid = 0; tid < numThreads; ++tid)
607 thread[tid]->inSyscall = true;
608
586 else
587 panic("No Such Port\n");
588}
589
590template <class Impl>
591void
592FullO3CPU<Impl>::tick()
593{

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653{
654 BaseCPU::init();
655
656 // Set inSyscall so that the CPU doesn't squash when initially
657 // setting up registers.
658 for (ThreadID tid = 0; tid < numThreads; ++tid)
659 thread[tid]->inSyscall = true;
660
661 // this CPU could still be unconnected if we are restoring from a
662 // checkpoint and this CPU is to be switched in, thus we can only
663 // do this here if the instruction port is actually connected, if
664 // not we have to do it as part of takeOverFrom
665 if (icachePort.isConnected())
666 fetch.setIcache();
667
609#if FULL_SYSTEM
610 for (ThreadID tid = 0; tid < numThreads; tid++) {
611 ThreadContext *src_tc = threadContexts[tid];
612 TheISA::initCPU(src_tc, src_tc->contextId());
613 // Initialise the ThreadContext's memory proxies
614 thread[tid]->initMemProxies(thread[tid]->getTC());
615 }
616#endif

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1165 fetchQueue.advance();
1166 decodeQueue.advance();
1167 renameQueue.advance();
1168 iewQueue.advance();
1169 }
1170
1171 activityRec.reset();
1172
668#if FULL_SYSTEM
669 for (ThreadID tid = 0; tid < numThreads; tid++) {
670 ThreadContext *src_tc = threadContexts[tid];
671 TheISA::initCPU(src_tc, src_tc->contextId());
672 // Initialise the ThreadContext's memory proxies
673 thread[tid]->initMemProxies(thread[tid]->getTC());
674 }
675#endif

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1224 fetchQueue.advance();
1225 decodeQueue.advance();
1226 renameQueue.advance();
1227 iewQueue.advance();
1228 }
1229
1230 activityRec.reset();
1231
1173 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1232 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
1174
1175 fetch.takeOverFrom();
1176 decode.takeOverFrom();
1177 rename.takeOverFrom();
1178 iew.takeOverFrom();
1179 commit.takeOverFrom();
1180
1181 assert(!tickEvent.scheduled() || tickEvent.squashed());

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1234 fetch.takeOverFrom();
1235 decode.takeOverFrom();
1236 rename.takeOverFrom();
1237 iew.takeOverFrom();
1238 commit.takeOverFrom();
1239
1240 assert(!tickEvent.scheduled() || tickEvent.squashed());

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