cpu.cc (7684:ce48527a3edb) cpu.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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727 renameMap[tid].setEntry(freg,phys_reg);
728 scoreboard.setReg(phys_reg);
729 }
730
731 //Copy Thread Data Into RegFile
732 //this->copyFromTC(tid);
733
734 //Set PC/NPC/NNPC
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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727 renameMap[tid].setEntry(freg,phys_reg);
728 scoreboard.setReg(phys_reg);
729 }
730
731 //Copy Thread Data Into RegFile
732 //this->copyFromTC(tid);
733
734 //Set PC/NPC/NNPC
735 setPC(src_tc->readPC(), tid);
736 setNextPC(src_tc->readNextPC(), tid);
737 setNextNPC(src_tc->readNextNPC(), tid);
735 pcState(src_tc->pcState(), tid);
738
739 src_tc->setStatus(ThreadContext::Active);
740
741 activateContext(tid,1);
742
743 //Reset ROB/IQ/LSQ Entries
744 commit.rob->resetEntries();
745 iew.resetEntries();

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773 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
774
775 scoreboard.unsetReg(phys_reg);
776 freeList.addReg(phys_reg);
777 }
778
779 // Squash Throughout Pipeline
780 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
736
737 src_tc->setStatus(ThreadContext::Active);
738
739 activateContext(tid,1);
740
741 //Reset ROB/IQ/LSQ Entries
742 commit.rob->resetEntries();
743 iew.resetEntries();

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771 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
772
773 scoreboard.unsetReg(phys_reg);
774 freeList.addReg(phys_reg);
775 }
776
777 // Squash Throughout Pipeline
778 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
781 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid);
779 fetch.squash(0, squash_seq_num, tid);
782 decode.squash(tid);
783 rename.squash(squash_seq_num, tid);
784 iew.squash(tid);
785 iew.ldstQueue.squash(squash_seq_num, tid);
786 commit.rob->squash(squash_seq_num, tid);
787
788
789 assert(iew.instQueue.getCount(tid) == 0);

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1301{
1302 int idx = reg_idx + TheISA::NumIntRegs;
1303 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1304
1305 regFile.setFloatRegBits(phys_reg, val);
1306}
1307
1308template <class Impl>
780 decode.squash(tid);
781 rename.squash(squash_seq_num, tid);
782 iew.squash(tid);
783 iew.ldstQueue.squash(squash_seq_num, tid);
784 commit.rob->squash(squash_seq_num, tid);
785
786
787 assert(iew.instQueue.getCount(tid) == 0);

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1299{
1300 int idx = reg_idx + TheISA::NumIntRegs;
1301 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1302
1303 regFile.setFloatRegBits(phys_reg, val);
1304}
1305
1306template <class Impl>
1309uint64_t
1310FullO3CPU<Impl>::readPC(ThreadID tid)
1307TheISA::PCState
1308FullO3CPU<Impl>::pcState(ThreadID tid)
1311{
1309{
1312 return commit.readPC(tid);
1310 return commit.pcState(tid);
1313}
1314
1315template <class Impl>
1316void
1311}
1312
1313template <class Impl>
1314void
1317FullO3CPU<Impl>::setPC(Addr new_PC, ThreadID tid)
1315FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1318{
1316{
1319 commit.setPC(new_PC, tid);
1317 commit.pcState(val, tid);
1320}
1321
1322template <class Impl>
1318}
1319
1320template <class Impl>
1323uint64_t
1324FullO3CPU<Impl>::readMicroPC(ThreadID tid)
1321Addr
1322FullO3CPU<Impl>::instAddr(ThreadID tid)
1325{
1323{
1326 return commit.readMicroPC(tid);
1324 return commit.instAddr(tid);
1327}
1328
1329template <class Impl>
1325}
1326
1327template <class Impl>
1330void
1331FullO3CPU<Impl>::setMicroPC(Addr new_PC, ThreadID tid)
1328Addr
1329FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1332{
1330{
1333 commit.setMicroPC(new_PC, tid);
1331 return commit.nextInstAddr(tid);
1334}
1335
1336template <class Impl>
1332}
1333
1334template <class Impl>
1337uint64_t
1338FullO3CPU<Impl>::readNextPC(ThreadID tid)
1335MicroPC
1336FullO3CPU<Impl>::microPC(ThreadID tid)
1339{
1337{
1340 return commit.readNextPC(tid);
1338 return commit.microPC(tid);
1341}
1342
1343template <class Impl>
1344void
1339}
1340
1341template <class Impl>
1342void
1345FullO3CPU<Impl>::setNextPC(uint64_t val, ThreadID tid)
1346{
1347 commit.setNextPC(val, tid);
1348}
1349
1350template <class Impl>
1351uint64_t
1352FullO3CPU<Impl>::readNextNPC(ThreadID tid)
1353{
1354 return commit.readNextNPC(tid);
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::setNextNPC(uint64_t val, ThreadID tid)
1360{
1361 commit.setNextNPC(val, tid);
1362}
1363
1364template <class Impl>
1365uint64_t
1366FullO3CPU<Impl>::readNextMicroPC(ThreadID tid)
1367{
1368 return commit.readNextMicroPC(tid);
1369}
1370
1371template <class Impl>
1372void
1373FullO3CPU<Impl>::setNextMicroPC(Addr new_PC, ThreadID tid)
1374{
1375 commit.setNextMicroPC(new_PC, tid);
1376}
1377
1378template <class Impl>
1379void
1380FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1381{
1382 this->thread[tid]->inSyscall = true;
1383 this->commit.generateTCEvent(tid);
1384}
1385
1386template <class Impl>
1387typename FullO3CPU<Impl>::ListIt

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1414
1415 removeList.push(inst->getInstListIt());
1416}
1417
1418template <class Impl>
1419void
1420FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1421{
1343FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1344{
1345 this->thread[tid]->inSyscall = true;
1346 this->commit.generateTCEvent(tid);
1347}
1348
1349template <class Impl>
1350typename FullO3CPU<Impl>::ListIt

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1377
1378 removeList.push(inst->getInstListIt());
1379}
1380
1381template <class Impl>
1382void
1383FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1384{
1422 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1385 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1423 "[sn:%lli]\n",
1386 "[sn:%lli]\n",
1424 inst->threadNumber, inst->readPC(), inst->seqNum);
1387 inst->threadNumber, inst->pcState(), inst->seqNum);
1425
1426 removeInstsThisCycle = true;
1427
1428 // Remove the front instruction.
1429 removeList.push(inst->getInstListIt());
1430}
1431
1432template <class Impl>

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1504}
1505
1506template <class Impl>
1507inline void
1508FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1509{
1510 if ((*instIt)->threadNumber == tid) {
1511 DPRINTF(O3CPU, "Squashing instruction, "
1388
1389 removeInstsThisCycle = true;
1390
1391 // Remove the front instruction.
1392 removeList.push(inst->getInstListIt());
1393}
1394
1395template <class Impl>

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1467}
1468
1469template <class Impl>
1470inline void
1471FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1472{
1473 if ((*instIt)->threadNumber == tid) {
1474 DPRINTF(O3CPU, "Squashing instruction, "
1512 "[tid:%i] [sn:%lli] PC %#x\n",
1475 "[tid:%i] [sn:%lli] PC %s\n",
1513 (*instIt)->threadNumber,
1514 (*instIt)->seqNum,
1476 (*instIt)->threadNumber,
1477 (*instIt)->seqNum,
1515 (*instIt)->readPC());
1478 (*instIt)->pcState());
1516
1517 // Mark it as squashed.
1518 (*instIt)->setSquashed();
1519
1520 // @todo: Formulate a consistent method for deleting
1521 // instructions from the instruction list
1522 // Remove the instruction from the list.
1523 removeList.push(instIt);
1524 }
1525}
1526
1527template <class Impl>
1528void
1529FullO3CPU<Impl>::cleanUpRemovedInsts()
1530{
1531 while (!removeList.empty()) {
1532 DPRINTF(O3CPU, "Removing instruction, "
1479
1480 // Mark it as squashed.
1481 (*instIt)->setSquashed();
1482
1483 // @todo: Formulate a consistent method for deleting
1484 // instructions from the instruction list
1485 // Remove the instruction from the list.
1486 removeList.push(instIt);
1487 }
1488}
1489
1490template <class Impl>
1491void
1492FullO3CPU<Impl>::cleanUpRemovedInsts()
1493{
1494 while (!removeList.empty()) {
1495 DPRINTF(O3CPU, "Removing instruction, "
1533 "[tid:%i] [sn:%lli] PC %#x\n",
1496 "[tid:%i] [sn:%lli] PC %s\n",
1534 (*removeList.front())->threadNumber,
1535 (*removeList.front())->seqNum,
1497 (*removeList.front())->threadNumber,
1498 (*removeList.front())->seqNum,
1536 (*removeList.front())->readPC());
1499 (*removeList.front())->pcState());
1537
1538 instList.erase(removeList.front());
1539
1540 removeList.pop();
1541 }
1542
1543 removeInstsThisCycle = false;
1544}

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1558
1559 ListIt inst_list_it = instList.begin();
1560
1561 cprintf("Dumping Instruction List\n");
1562
1563 while (inst_list_it != instList.end()) {
1564 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1565 "Squashed:%i\n\n",
1500
1501 instList.erase(removeList.front());
1502
1503 removeList.pop();
1504 }
1505
1506 removeInstsThisCycle = false;
1507}

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1521
1522 ListIt inst_list_it = instList.begin();
1523
1524 cprintf("Dumping Instruction List\n");
1525
1526 while (inst_list_it != instList.end()) {
1527 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1528 "Squashed:%i\n\n",
1566 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1529 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1567 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1568 (*inst_list_it)->isSquashed());
1569 inst_list_it++;
1570 ++num;
1571 }
1572}
1573/*
1574template <class Impl>

--- 90 unchanged lines hidden --- 		1530 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1531 (*inst_list_it)->isSquashed());
1532 inst_list_it++;
1533 ++num;
1534 }
1535}
1536/*
1537template <class Impl>

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