cpu.cc (6313:95f69a436c82) cpu.cc (6314:781969fbeca9)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1210uint64_t
1211FullO3CPU<Impl>::readIntReg(int reg_idx)
1212{
1213 return regFile.readIntReg(reg_idx);
1214}
1215
1216template <class Impl>
1217FloatReg
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 1201 unchanged lines hidden (view full) ---

1210uint64_t
1211FullO3CPU<Impl>::readIntReg(int reg_idx)
1212{
1213 return regFile.readIntReg(reg_idx);
1214}
1215
1216template <class Impl>
1217FloatReg
1218FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
1219{
1220 return regFile.readFloatReg(reg_idx, width);
1221}
1222
1223template <class Impl>
1224FloatReg
1225FullO3CPU<Impl>::readFloatReg(int reg_idx)
1226{
1227 return regFile.readFloatReg(reg_idx);
1228}
1229
1230template <class Impl>
1231FloatRegBits
1218FullO3CPU<Impl>::readFloatReg(int reg_idx)
1219{
1220 return regFile.readFloatReg(reg_idx);
1221}
1222
1223template <class Impl>
1224FloatRegBits
1232FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
1233{
1234 return regFile.readFloatRegBits(reg_idx, width);
1235}
1236
1237template <class Impl>
1238FloatRegBits
1239FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1240{
1241 return regFile.readFloatRegBits(reg_idx);
1242}
1243
1244template <class Impl>
1245void
1246FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1247{
1248 regFile.setIntReg(reg_idx, val);
1249}
1250
1251template <class Impl>
1252void
1225FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1226{
1227 return regFile.readFloatRegBits(reg_idx);
1228}
1229
1230template <class Impl>
1231void
1232FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1233{
1234 regFile.setIntReg(reg_idx, val);
1235}
1236
1237template <class Impl>
1238void
1253FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
1254{
1255 regFile.setFloatReg(reg_idx, val, width);
1256}
1257
1258template <class Impl>
1259void
1260FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1261{
1262 regFile.setFloatReg(reg_idx, val);
1263}
1264
1265template <class Impl>
1266void
1239FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1240{
1241 regFile.setFloatReg(reg_idx, val);
1242}
1243
1244template <class Impl>
1245void
1267FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1268{
1269 regFile.setFloatRegBits(reg_idx, val, width);
1270}
1271
1272template <class Impl>
1273void
1274FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1275{
1276 regFile.setFloatRegBits(reg_idx, val);
1277}
1278
1279template <class Impl>
1280uint64_t
1281FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1282{
1283 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1284
1285 return regFile.readIntReg(phys_reg);
1286}
1287
1288template <class Impl>
1289float
1246FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1247{
1248 regFile.setFloatRegBits(reg_idx, val);
1249}
1250
1251template <class Impl>
1252uint64_t
1253FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1254{
1255 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1256
1257 return regFile.readIntReg(phys_reg);
1258}
1259
1260template <class Impl>
1261float
1290FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
1262FullO3CPU::readArchFloatReg(int reg_idx, ThreadID tid)
1291{
1292 int idx = reg_idx + TheISA::NumIntRegs;
1293 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1294
1295 return regFile.readFloatReg(phys_reg);
1296}
1297
1298template <class Impl>
1263{
1264 int idx = reg_idx + TheISA::NumIntRegs;
1265 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1266
1267 return regFile.readFloatReg(phys_reg);
1268}
1269
1270template <class Impl>
1299double
1300FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid)
1301{
1302 int idx = reg_idx + TheISA::NumIntRegs;
1303 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1304
1305 return regFile.readFloatReg(phys_reg, 64);
1306}
1307
1308template <class Impl>
1309uint64_t
1310FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1311{
1312 int idx = reg_idx + TheISA::NumIntRegs;
1313 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1314
1315 return regFile.readFloatRegBits(phys_reg);
1316}

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1321{
1322 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1323
1324 regFile.setIntReg(phys_reg, val);
1325}
1326
1327template <class Impl>
1328void
1271uint64_t
1272FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1273{
1274 int idx = reg_idx + TheISA::NumIntRegs;
1275 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1276
1277 return regFile.readFloatRegBits(phys_reg);
1278}

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1283{
1284 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1285
1286 regFile.setIntReg(phys_reg, val);
1287}
1288
1289template <class Impl>
1290void
1329FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
1291FullO3CPU::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1330{
1331 int idx = reg_idx + TheISA::NumIntRegs;
1332 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1333
1334 regFile.setFloatReg(phys_reg, val);
1335}
1336
1337template <class Impl>
1338void
1292{
1293 int idx = reg_idx + TheISA::NumIntRegs;
1294 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1295
1296 regFile.setFloatReg(phys_reg, val);
1297}
1298
1299template <class Impl>
1300void
1339FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid)
1340{
1341 int idx = reg_idx + TheISA::NumIntRegs;
1342 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1343
1344 regFile.setFloatReg(phys_reg, val, 64);
1345}
1346
1347template <class Impl>
1348void
1349FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1350{
1351 int idx = reg_idx + TheISA::NumIntRegs;
1352 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1353
1354 regFile.setFloatRegBits(phys_reg, val);
1355}
1356

--- 357 unchanged lines hidden --- 		1301FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1302{
1303 int idx = reg_idx + TheISA::NumIntRegs;
1304 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1305
1306 regFile.setFloatRegBits(phys_reg, val);
1307}
1308

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