cpu.cc (5639:67cc7f0427e7) | cpu.cc (5640:c811ced9efc1) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 39 unchanged lines hidden (view full) --- 48#else 49#include "sim/process.hh" 50#endif 51 52#if USE_CHECKER 53#include "cpu/checker/cpu.hh" 54#endif 55 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 39 unchanged lines hidden (view full) --- 48#else 49#include "sim/process.hh" 50#endif 51 52#if USE_CHECKER 53#include "cpu/checker/cpu.hh" 54#endif 55 |
56#if THE_ISA == ALPHA_ISA 57#include "arch/alpha/osfpal.hh" 58#endif 59 | |
60class BaseCPUParams; 61 62using namespace TheISA; 63 64BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 65 : BaseCPU(params), cpu_id(0) 66{ 67} --- 833 unchanged lines hidden (view full) --- 901 902 if (this->thread[0]->status() == ThreadContext::Suspended) { 903 DPRINTF(IPI,"Suspended Processor awoke\n"); 904 this->threadContexts[0]->activate(); 905 } 906} 907 908template <class Impl> | 56class BaseCPUParams; 57 58using namespace TheISA; 59 60BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 61 : BaseCPU(params), cpu_id(0) 62{ 63} --- 833 unchanged lines hidden (view full) --- 897 898 if (this->thread[0]->status() == ThreadContext::Suspended) { 899 DPRINTF(IPI,"Suspended Processor awoke\n"); 900 this->threadContexts[0]->activate(); 901 } 902} 903 904template <class Impl> |
909bool 910FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 911{ 912#if THE_ISA == ALPHA_ISA 913 if (this->thread[tid]->kernelStats) 914 this->thread[tid]->kernelStats->callpal(palFunc, 915 this->threadContexts[tid]); 916 917 switch (palFunc) { 918 case PAL::halt: 919 halt(); 920 if (--System::numSystemsRunning == 0) 921 exitSimLoop("all cpus halted"); 922 break; 923 924 case PAL::bpt: 925 case PAL::bugchk: 926 if (this->system->breakpoint()) 927 return false; 928 break; 929 } 930#endif 931 return true; 932} 933 934template <class Impl> | |
935Fault 936FullO3CPU<Impl>::getInterrupts() 937{ 938 // Check if there are any outstanding interrupts 939 return this->interrupts.getInterrupt(this->threadContexts[0]); 940} 941 942template <class Impl> --- 786 unchanged lines hidden --- | 905Fault 906FullO3CPU<Impl>::getInterrupts() 907{ 908 // Check if there are any outstanding interrupts 909 return this->interrupts.getInterrupt(this->threadContexts[0]); 910} 911 912template <class Impl> --- 786 unchanged lines hidden --- |