cpu.cc (5595:6ebdae3f619b) cpu.cc (5606:6da7a58b0bc8)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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69void
70BaseO3CPU::regStats()
71{
72 BaseCPU::regStats();
73}
74
75template <class Impl>
76FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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69void
70BaseO3CPU::regStats()
71{
72 BaseCPU::regStats();
73}
74
75template <class Impl>
76FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
77 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
77 : Event(CPU_Tick_Pri), cpu(c)
78{
79}
80
81template <class Impl>
82void
83FullO3CPU<Impl>::TickEvent::process()
84{
85 cpu->tick();
86}
87
88template <class Impl>
89const char *
90FullO3CPU<Impl>::TickEvent::description() const
91{
92 return "FullO3CPU tick";
93}
94
95template <class Impl>
96FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
78{
79}
80
81template <class Impl>
82void
83FullO3CPU<Impl>::TickEvent::process()
84{
85 cpu->tick();
86}
87
88template <class Impl>
89const char *
90FullO3CPU<Impl>::TickEvent::description() const
91{
92 return "FullO3CPU tick";
93}
94
95template <class Impl>
96FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
97 : Event(&mainEventQueue, CPU_Switch_Pri)
97 : Event(CPU_Switch_Pri)
98{
99}
100
101template <class Impl>
102void
103FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
104 FullO3CPU<Impl> *thread_cpu)
105{

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118const char *
119FullO3CPU<Impl>::ActivateThreadEvent::description() const
120{
121 return "FullO3CPU \"Activate Thread\"";
122}
123
124template <class Impl>
125FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
98{
99}
100
101template <class Impl>
102void
103FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
104 FullO3CPU<Impl> *thread_cpu)
105{

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118const char *
119FullO3CPU<Impl>::ActivateThreadEvent::description() const
120{
121 return "FullO3CPU \"Activate Thread\"";
122}
123
124template <class Impl>
125FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
126 : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
126 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
127{
128}
129
130template <class Impl>
131void
132FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
133 FullO3CPU<Impl> *thread_cpu)
134{

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571 DPRINTF(O3CPU, "Switched out!\n");
572 // increment stat
573 lastRunningCycle = curTick;
574 } else if (!activityRec.active() || _status == Idle) {
575 DPRINTF(O3CPU, "Idle!\n");
576 lastRunningCycle = curTick;
577 timesIdled++;
578 } else {
127{
128}
129
130template <class Impl>
131void
132FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
133 FullO3CPU<Impl> *thread_cpu)
134{

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571 DPRINTF(O3CPU, "Switched out!\n");
572 // increment stat
573 lastRunningCycle = curTick;
574 } else if (!activityRec.active() || _status == Idle) {
575 DPRINTF(O3CPU, "Idle!\n");
576 lastRunningCycle = curTick;
577 timesIdled++;
578 } else {
579 tickEvent.schedule(nextCycle(curTick + ticks(1)));
579 schedule(tickEvent, nextCycle(curTick + ticks(1)));
580 DPRINTF(O3CPU, "Scheduling next tick!\n");
581 }
582 }
583
584#if !FULL_SYSTEM
585 updateThreadPriority();
586#endif
580 DPRINTF(O3CPU, "Scheduling next tick!\n");
581 }
582 }
583
584#if !FULL_SYSTEM
585 updateThreadPriority();
586#endif
587
588}
589
590template <class Impl>
591void
592FullO3CPU<Impl>::init()
593{
594 if (!deferRegistration) {
595 registerThreadContexts();

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1116 if (_status == SwitchedOut || _status == Idle)
1117 return;
1118
1119#if FULL_SYSTEM
1120 assert(system->getMemoryMode() == Enums::timing);
1121#endif
1122
1123 if (!tickEvent.scheduled())
587}
588
589template <class Impl>
590void
591FullO3CPU<Impl>::init()
592{
593 if (!deferRegistration) {
594 registerThreadContexts();

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1115 if (_status == SwitchedOut || _status == Idle)
1116 return;
1117
1118#if FULL_SYSTEM
1119 assert(system->getMemoryMode() == Enums::timing);
1120#endif
1121
1122 if (!tickEvent.scheduled())
1124 tickEvent.schedule(nextCycle());
1123 schedule(tickEvent, nextCycle());
1125 _status = Running;
1126}
1127
1128template <class Impl>
1129void
1130FullO3CPU<Impl>::signalDrained()
1131{
1132 if (++drainCount == NumStages) {

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1209 }
1210
1211 // Set all statuses to active, schedule the CPU's tick event.
1212 // @todo: Fix up statuses so this is handled properly
1213 for (int i = 0; i < threadContexts.size(); ++i) {
1214 ThreadContext *tc = threadContexts[i];
1215 if (tc->status() == ThreadContext::Active && _status != Running) {
1216 _status = Running;
1124 _status = Running;
1125}
1126
1127template <class Impl>
1128void
1129FullO3CPU<Impl>::signalDrained()
1130{
1131 if (++drainCount == NumStages) {

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1208 }
1209
1210 // Set all statuses to active, schedule the CPU's tick event.
1211 // @todo: Fix up statuses so this is handled properly
1212 for (int i = 0; i < threadContexts.size(); ++i) {
1213 ThreadContext *tc = threadContexts[i];
1214 if (tc->status() == ThreadContext::Active && _status != Running) {
1215 _status = Running;
1217 tickEvent.schedule(nextCycle());
1216 schedule(tickEvent, nextCycle());
1218 }
1219 }
1220 if (!tickEvent.scheduled())
1217 }
1218 }
1219 if (!tickEvent.scheduled())
1221 tickEvent.schedule(nextCycle());
1220 schedule(tickEvent, nextCycle());
1222}
1223
1224template <class Impl>
1225TheISA::MiscReg
1226FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
1227{
1228 return this->regFile.readMiscRegNoEffect(misc_reg, tid);
1229}

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1682 return;
1683 }
1684
1685 DPRINTF(Activity, "Waking up CPU\n");
1686
1687 idleCycles += tickToCycles((curTick - 1) - lastRunningCycle);
1688 numCycles += tickToCycles((curTick - 1) - lastRunningCycle);
1689
1221}
1222
1223template <class Impl>
1224TheISA::MiscReg
1225FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
1226{
1227 return this->regFile.readMiscRegNoEffect(misc_reg, tid);
1228}

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1681 return;
1682 }
1683
1684 DPRINTF(Activity, "Waking up CPU\n");
1685
1686 idleCycles += tickToCycles((curTick - 1) - lastRunningCycle);
1687 numCycles += tickToCycles((curTick - 1) - lastRunningCycle);
1688
1690 tickEvent.schedule(nextCycle());
1689 schedule(tickEvent, nextCycle());
1691}
1692
1693template <class Impl>
1694int
1695FullO3CPU<Impl>::getFreeTid()
1696{
1697 for (int i=0; i < numThreads; i++) {
1698 if (!tids[i]) {

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1691
1692template <class Impl>
1693int
1694FullO3CPU<Impl>::getFreeTid()
1695{
1696 for (int i=0; i < numThreads; i++) {
1697 if (!tids[i]) {

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