cpu.cc (5362:0adba9a562c9) cpu.cc (5363:c474cb7a2b9c)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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690 }
691
692 // Squash Throughout Pipeline
693 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
694 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid);
695 decode.squash(tid);
696 rename.squash(squash_seq_num, tid);
697 iew.squash(tid);
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 681 unchanged lines hidden (view full) ---

690 }
691
692 // Squash Throughout Pipeline
693 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
694 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid);
695 decode.squash(tid);
696 rename.squash(squash_seq_num, tid);
697 iew.squash(tid);
698 //iew.ldstQueue.squash(squash_seq_num, tid);
698 iew.ldstQueue.squash(squash_seq_num, tid);
699 commit.rob->squash(squash_seq_num, tid);
700
701
702 assert(iew.instQueue.getCount(tid) == 0);
703 assert(iew.ldstQueue.getCount(tid) == 0);
704
705 // Reset ROB/IQ/LSQ Entries
706

--- 765 unchanged lines hidden --- 		699 commit.rob->squash(squash_seq_num, tid);
700
701
702 assert(iew.instQueue.getCount(tid) == 0);
703 assert(iew.ldstQueue.getCount(tid) == 0);
704
705 // Reset ROB/IQ/LSQ Entries
706

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