cpu.cc (4873:b135f6e6adfe) cpu.cc (4918:3214e3694fb2)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "cpu/quiesce_event.hh"
37#include "sim/system.hh"
38#else
39#include "sim/process.hh"
40#endif
41
42#include "cpu/activity.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "cpu/o3/isa_specific.hh"
46#include "cpu/o3/cpu.hh"
35#include "cpu/activity.hh"
36#include "cpu/simple_thread.hh"
37#include "cpu/thread_context.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/cpu.hh"
47
40#include "enums/MemoryMode.hh"
48#include "sim/core.hh"
49#include "sim/stat_control.hh"
50
41#include "sim/core.hh"
42#include "sim/stat_control.hh"
43
44#if FULL_SYSTEM
45#include "cpu/quiesce_event.hh"
46#include "sim/system.hh"
47#else
48#include "sim/process.hh"
49#endif
50
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)

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877 commit.resume();
878
879 changeState(SimObject::Running);
880
881 if (_status == SwitchedOut || _status == Idle)
882 return;
883
884#if FULL_SYSTEM
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)

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877 commit.resume();
878
879 changeState(SimObject::Running);
880
881 if (_status == SwitchedOut || _status == Idle)
882 return;
883
884#if FULL_SYSTEM
885 assert(system->getMemoryMode() == System::Timing);
885 assert(system->getMemoryMode() == Enums::timing);
886#endif
887
888 if (!tickEvent.scheduled())
889 tickEvent.schedule(nextCycle());
890 _status = Running;
891}
892
893template <class Impl>

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887
888 if (!tickEvent.scheduled())
889 tickEvent.schedule(nextCycle());
890 _status = Running;
891}
892
893template <class Impl>

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