cpu.cc (4598:56adf2e778a8) cpu.cc (4632:be5b8f67b8fb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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199 numThreads(number_of_threads)
200{
201 if (!deferRegistration) {
202 _status = Running;
203 } else {
204 _status = Idle;
205 }
206
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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199 numThreads(number_of_threads)
200{
201 if (!deferRegistration) {
202 _status = Running;
203 } else {
204 _status = Idle;
205 }
206
207#if USE_CHECKER
207 checker = NULL;
208
208 if (params->checker) {
209 if (params->checker) {
210#if USE_CHECKER
209 BaseCPU *temp_checker = params->checker;
210 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
211#if FULL_SYSTEM
212 checker->setSystem(params->system);
213#endif
211 BaseCPU *temp_checker = params->checker;
212 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
213#if FULL_SYSTEM
214 checker->setSystem(params->system);
215#endif
214 } else {
215 checker = NULL;
216 }
216#else
217 panic("Checker enabled but not compiled in!");
217#endif // USE_CHECKER
218#endif // USE_CHECKER
219 }
218
219#if !FULL_SYSTEM
220 thread.resize(number_of_threads);
221 tids.resize(number_of_threads);
222#endif
223
224 // The stages also need their CPU pointer setup. However this
225 // must be done at the upper level CPU because they have pointers

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377 totalCommittedInsts
378 .name(name() + ".committedInsts_total")
379 .desc("Number of Instructions Simulated");
380
381 cpi
382 .name(name() + ".cpi")
383 .desc("CPI: Cycles Per Instruction")
384 .precision(6);
220
221#if !FULL_SYSTEM
222 thread.resize(number_of_threads);
223 tids.resize(number_of_threads);
224#endif
225
226 // The stages also need their CPU pointer setup. However this
227 // must be done at the upper level CPU because they have pointers

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379 totalCommittedInsts
380 .name(name() + ".committedInsts_total")
381 .desc("Number of Instructions Simulated");
382
383 cpi
384 .name(name() + ".cpi")
385 .desc("CPI: Cycles Per Instruction")
386 .precision(6);
385 cpi = numCycles / committedInsts;
387 cpi = simTicks / committedInsts;
386
387 totalCpi
388 .name(name() + ".cpi_total")
389 .desc("CPI: Total CPI of All Threads")
390 .precision(6);
388
389 totalCpi
390 .name(name() + ".cpi_total")
391 .desc("CPI: Total CPI of All Threads")
392 .precision(6);
391 totalCpi = numCycles / totalCommittedInsts;
393 totalCpi = simTicks / totalCommittedInsts;
392
393 ipc
394 .name(name() + ".ipc")
395 .desc("IPC: Instructions Per Cycle")
396 .precision(6);
394
395 ipc
396 .name(name() + ".ipc")
397 .desc("IPC: Instructions Per Cycle")
398 .precision(6);
397 ipc = committedInsts / numCycles;
399 ipc = committedInsts / simTicks;
398
399 totalIpc
400 .name(name() + ".ipc_total")
401 .desc("IPC: Total IPC of All Threads")
402 .precision(6);
400
401 totalIpc
402 .name(name() + ".ipc_total")
403 .desc("IPC: Total IPC of All Threads")
404 .precision(6);
403 totalIpc = totalCommittedInsts / numCycles;
405 totalIpc = totalCommittedInsts / simTicks;
404
405}
406
407template <class Impl>
408Port *
409FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
410{
411 if (if_name == "dcache_port")

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689 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
690
691 scoreboard.unsetReg(phys_reg);
692 freeList.addReg(phys_reg);
693 }
694
695 // Squash Throughout Pipeline
696 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
406
407}
408
409template <class Impl>
410Port *
411FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
412{
413 if (if_name == "dcache_port")

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691 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
692
693 scoreboard.unsetReg(phys_reg);
694 freeList.addReg(phys_reg);
695 }
696
697 // Squash Throughout Pipeline
698 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
697 fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, true, tid);
699 fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, tid);
698 decode.squash(tid);
699 rename.squash(squash_seq_num, tid);
700 iew.squash(tid);
701 commit.rob->squash(squash_seq_num, tid);
702
703 assert(iew.ldstQueue.getCount(tid) == 0);
704
705 // Reset ROB/IQ/LSQ Entries

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1219 removeInstsThisCycle = true;
1220
1221 // Remove the front instruction.
1222 removeList.push(inst->getInstListIt());
1223}
1224
1225template <class Impl>
1226void
700 decode.squash(tid);
701 rename.squash(squash_seq_num, tid);
702 iew.squash(tid);
703 commit.rob->squash(squash_seq_num, tid);
704
705 assert(iew.ldstQueue.getCount(tid) == 0);
706
707 // Reset ROB/IQ/LSQ Entries

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1221 removeInstsThisCycle = true;
1222
1223 // Remove the front instruction.
1224 removeList.push(inst->getInstListIt());
1225}
1226
1227template <class Impl>
1228void
1227FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1228 bool squash_delay_slot,
1229 const InstSeqNum &delay_slot_seq_num)
1229FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1230{
1231 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1232 " list.\n", tid);
1233
1234 ListIt end_it;
1235
1236 bool rob_empty = false;
1237

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1252
1253 inst_it--;
1254
1255 // Walk through the instruction list, removing any instructions
1256 // that were inserted after the given instruction iterator, end_it.
1257 while (inst_it != end_it) {
1258 assert(!instList.empty());
1259
1230{
1231 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1232 " list.\n", tid);
1233
1234 ListIt end_it;
1235
1236 bool rob_empty = false;
1237

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1252
1253 inst_it--;
1254
1255 // Walk through the instruction list, removing any instructions
1256 // that were inserted after the given instruction iterator, end_it.
1257 while (inst_it != end_it) {
1258 assert(!instList.empty());
1259
1260#if ISA_HAS_DELAY_SLOT
1261 if(!squash_delay_slot &&
1262 delay_slot_seq_num >= (*inst_it)->seqNum) {
1263 break;
1264 }
1265#endif
1266 squashInstIt(inst_it, tid);
1267
1268 inst_it--;
1269 }
1270
1271 // If the ROB was empty, then we actually need to remove the first
1272 // instruction as well.
1273 if (rob_empty) {

--- 177 unchanged lines hidden --- 		1260 squashInstIt(inst_it, tid);
1261
1262 inst_it--;
1263 }
1264
1265 // If the ROB was empty, then we actually need to remove the first
1266 // instruction as well.
1267 if (rob_empty) {

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