cpu.cc (4167:ce5d0f62f13b) cpu.cc (4192:7accc6365bb9)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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552 activeThreads.erase(thread_it);
553 }
554}
555
556template <class Impl>
557void
558FullO3CPU<Impl>::activateContext(int tid, int delay)
559{
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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552 activeThreads.erase(thread_it);
553 }
554}
555
556template <class Impl>
557void
558FullO3CPU<Impl>::activateContext(int tid, int delay)
559{
560#if FULL_SYSTEM
561 // Connect the ThreadContext's memory ports (Functional/Virtual
562 // Ports)
563 threadContexts[tid]->connectMemPorts();
564#endif
565
566 // Needs to set each stage to running as well.
567 if (delay){
568 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
569 "on cycle %d\n", tid, curTick + cycles(delay));
570 scheduleActivateThreadEvent(tid, delay);
571 } else {
572 activateThread(tid);
573 }

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776 contextSwitch = true;
777
778 //@todo: dont always add to waitlist
779 //do waitlist
780 cpuWaitList.push_back(tid);
781 }
782}
783
560 // Needs to set each stage to running as well.
561 if (delay){
562 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
563 "on cycle %d\n", tid, curTick + cycles(delay));
564 scheduleActivateThreadEvent(tid, delay);
565 } else {
566 activateThread(tid);
567 }

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770 contextSwitch = true;
771
772 //@todo: dont always add to waitlist
773 //do waitlist
774 cpuWaitList.push_back(tid);
775 }
776}
777
778#if FULL_SYSTEM
784template <class Impl>
785void
779template <class Impl>
780void
781FullO3CPU<Impl>::updateMemPorts()
782{
783 // Update all ThreadContext's memory ports (Functional/Virtual
784 // Ports)
785 for (int i = 0; i < thread.size(); ++i)
786 thread[i]->connectMemPorts();
787}
788#endif
789
790template <class Impl>
791void
786FullO3CPU<Impl>::serialize(std::ostream &os)
787{
788 SimObject::State so_state = SimObject::getState();
789 SERIALIZE_ENUM(so_state);
790 BaseCPU::serialize(os);
791 nameOut(os, csprintf("%s.tickEvent", name()));
792 tickEvent.serialize(os);
793

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936 fetchQueue.advance();
937 decodeQueue.advance();
938 renameQueue.advance();
939 iewQueue.advance();
940 }
941
942 activityRec.reset();
943
792FullO3CPU<Impl>::serialize(std::ostream &os)
793{
794 SimObject::State so_state = SimObject::getState();
795 SERIALIZE_ENUM(so_state);
796 BaseCPU::serialize(os);
797 nameOut(os, csprintf("%s.tickEvent", name()));
798 tickEvent.serialize(os);
799

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942 fetchQueue.advance();
943 decodeQueue.advance();
944 renameQueue.advance();
945 iewQueue.advance();
946 }
947
948 activityRec.reset();
949
944 BaseCPU::takeOverFrom(oldCPU);
950 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
945
946 fetch.takeOverFrom();
947 decode.takeOverFrom();
948 rename.takeOverFrom();
949 iew.takeOverFrom();
950 commit.takeOverFrom();
951
952 assert(!tickEvent.scheduled());

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973 ThreadContext *tc = threadContexts[i];
974 if (tc->status() == ThreadContext::Active && _status != Running) {
975 _status = Running;
976 tickEvent.schedule(curTick);
977 }
978 }
979 if (!tickEvent.scheduled())
980 tickEvent.schedule(curTick);
951
952 fetch.takeOverFrom();
953 decode.takeOverFrom();
954 rename.takeOverFrom();
955 iew.takeOverFrom();
956 commit.takeOverFrom();
957
958 assert(!tickEvent.scheduled());

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979 ThreadContext *tc = threadContexts[i];
980 if (tc->status() == ThreadContext::Active && _status != Running) {
981 _status = Running;
982 tickEvent.schedule(curTick);
983 }
984 }
985 if (!tickEvent.scheduled())
986 tickEvent.schedule(curTick);
981
982 Port *peer;
983 Port *icachePort = fetch.getIcachePort();
984 if (icachePort->getPeer() == NULL) {
985 peer = oldCPU->getPort("icache_port")->getPeer();
986 icachePort->setPeer(peer);
987 } else {
988 peer = icachePort->getPeer();
989 }
990 peer->setPeer(icachePort);
991
992 Port *dcachePort = iew.getDcachePort();
993 if (dcachePort->getPeer() == NULL) {
994 peer = oldCPU->getPort("dcache_port")->getPeer();
995 dcachePort->setPeer(peer);
996 } else {
997 peer = dcachePort->getPeer();
998 }
999 peer->setPeer(dcachePort);
1000}
1001
1002template <class Impl>
1003uint64_t
1004FullO3CPU<Impl>::readIntReg(int reg_idx)
1005{
1006 return regFile.readIntReg(reg_idx);
1007}

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988
989template <class Impl>
990uint64_t
991FullO3CPU<Impl>::readIntReg(int reg_idx)
992{
993 return regFile.readIntReg(reg_idx);
994}

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