cpu.cc (3970:d54945bab95d) | cpu.cc (4030:4046b2213995) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 452 unchanged lines hidden (view full) --- 461 DPRINTF(O3CPU, "Switched out!\n"); 462 // increment stat 463 lastRunningCycle = curTick; 464 } else if (!activityRec.active() || _status == Idle) { 465 DPRINTF(O3CPU, "Idle!\n"); 466 lastRunningCycle = curTick; 467 timesIdled++; 468 } else { | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 452 unchanged lines hidden (view full) --- 461 DPRINTF(O3CPU, "Switched out!\n"); 462 // increment stat 463 lastRunningCycle = curTick; 464 } else if (!activityRec.active() || _status == Idle) { 465 DPRINTF(O3CPU, "Idle!\n"); 466 lastRunningCycle = curTick; 467 timesIdled++; 468 } else { |
469 tickEvent.schedule(curTick + cycles(1)); | 469 tickEvent.schedule(nextCycle(curTick + cycles(1))); |
470 DPRINTF(O3CPU, "Scheduling next tick!\n"); 471 } 472 } 473 474#if !FULL_SYSTEM 475 updateThreadPriority(); 476#endif 477 --- 397 unchanged lines hidden (view full) --- 875 if (_status == SwitchedOut || _status == Idle) 876 return; 877 878#if FULL_SYSTEM 879 assert(system->getMemoryMode() == System::Timing); 880#endif 881 882 if (!tickEvent.scheduled()) | 470 DPRINTF(O3CPU, "Scheduling next tick!\n"); 471 } 472 } 473 474#if !FULL_SYSTEM 475 updateThreadPriority(); 476#endif 477 --- 397 unchanged lines hidden (view full) --- 875 if (_status == SwitchedOut || _status == Idle) 876 return; 877 878#if FULL_SYSTEM 879 assert(system->getMemoryMode() == System::Timing); 880#endif 881 882 if (!tickEvent.scheduled()) |
883 tickEvent.schedule(curTick); | 883 tickEvent.schedule(nextCycle()); |
884 _status = Running; 885} 886 887template <class Impl> 888void 889FullO3CPU<Impl>::signalDrained() 890{ 891 if (++drainCount == NumStages) { --- 76 unchanged lines hidden (view full) --- 968 } 969 970 // Set all statuses to active, schedule the CPU's tick event. 971 // @todo: Fix up statuses so this is handled properly 972 for (int i = 0; i < threadContexts.size(); ++i) { 973 ThreadContext *tc = threadContexts[i]; 974 if (tc->status() == ThreadContext::Active && _status != Running) { 975 _status = Running; | 884 _status = Running; 885} 886 887template <class Impl> 888void 889FullO3CPU<Impl>::signalDrained() 890{ 891 if (++drainCount == NumStages) { --- 76 unchanged lines hidden (view full) --- 968 } 969 970 // Set all statuses to active, schedule the CPU's tick event. 971 // @todo: Fix up statuses so this is handled properly 972 for (int i = 0; i < threadContexts.size(); ++i) { 973 ThreadContext *tc = threadContexts[i]; 974 if (tc->status() == ThreadContext::Active && _status != Running) { 975 _status = Running; |
976 tickEvent.schedule(curTick); | 976 tickEvent.schedule(nextCycle()); |
977 } 978 } 979 if (!tickEvent.scheduled()) | 977 } 978 } 979 if (!tickEvent.scheduled()) |
980 tickEvent.schedule(curTick); | 980 tickEvent.schedule(nextCycle()); |
981 982 Port *peer; 983 Port *icachePort = fetch.getIcachePort(); 984 if (icachePort->getPeer() == NULL) { 985 peer = oldCPU->getPort("icache_port")->getPeer(); 986 icachePort->setPeer(peer); 987 } else { 988 peer = icachePort->getPeer(); --- 412 unchanged lines hidden (view full) --- 1401 DPRINTF(Activity, "CPU already running.\n"); 1402 return; 1403 } 1404 1405 DPRINTF(Activity, "Waking up CPU\n"); 1406 1407 idleCycles += (curTick - 1) - lastRunningCycle; 1408 | 981 982 Port *peer; 983 Port *icachePort = fetch.getIcachePort(); 984 if (icachePort->getPeer() == NULL) { 985 peer = oldCPU->getPort("icache_port")->getPeer(); 986 icachePort->setPeer(peer); 987 } else { 988 peer = icachePort->getPeer(); --- 412 unchanged lines hidden (view full) --- 1401 DPRINTF(Activity, "CPU already running.\n"); 1402 return; 1403 } 1404 1405 DPRINTF(Activity, "Waking up CPU\n"); 1406 1407 idleCycles += (curTick - 1) - lastRunningCycle; 1408 |
1409 tickEvent.schedule(curTick); | 1409 tickEvent.schedule(nextCycle()); |
1410} 1411 1412template <class Impl> 1413int 1414FullO3CPU<Impl>::getFreeTid() 1415{ 1416 for (int i=0; i < numThreads; i++) { 1417 if (!tids[i]) { --- 46 unchanged lines hidden --- | 1410} 1411 1412template <class Impl> 1413int 1414FullO3CPU<Impl>::getFreeTid() 1415{ 1416 for (int i=0; i < numThreads; i++) { 1417 if (!tids[i]) { --- 46 unchanged lines hidden --- |