cpu.cc (3781:b00795985f07) cpu.cc (3795:60ecc96c3cee)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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695 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
696
697 scoreboard.unsetReg(phys_reg);
698 freeList.addReg(phys_reg);
699 }
700
701 // Squash Throughout Pipeline
702 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 686 unchanged lines hidden (view full) ---

695 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
696
697 scoreboard.unsetReg(phys_reg);
698 freeList.addReg(phys_reg);
699 }
700
701 // Squash Throughout Pipeline
702 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
703 fetch.squash(0, squash_seq_num, true, tid);
703 fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, true, tid);
704 decode.squash(tid);
705 rename.squash(squash_seq_num, tid);
706 iew.squash(tid);
707 commit.rob->squash(squash_seq_num, tid);
708
709 assert(iew.ldstQueue.getCount(tid) == 0);
710
711 // Reset ROB/IQ/LSQ Entries

--- 752 unchanged lines hidden --- 		704 decode.squash(tid);
705 rename.squash(squash_seq_num, tid);
706 iew.squash(tid);
707 commit.rob->squash(squash_seq_num, tid);
708
709 assert(iew.ldstQueue.getCount(tid) == 0);
710
711 // Reset ROB/IQ/LSQ Entries

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