cpu.cc (3093:b09c33e66bce) cpu.cc (3125:febd811bccc6)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "cpu/quiesce_event.hh"
36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"

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788 thread[i]->getTC()->copyArchRegs(temp.getTC());
789 }
790}
791
792template <class Impl>
793unsigned int
794FullO3CPU<Impl>::drain(Event *drain_event)
795{
37#include "sim/system.hh"
38#else
39#include "sim/process.hh"
40#endif
41
42#include "cpu/activity.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"

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789 thread[i]->getTC()->copyArchRegs(temp.getTC());
790 }
791}
792
793template <class Impl>
794unsigned int
795FullO3CPU<Impl>::drain(Event *drain_event)
796{
797 DPRINTF(O3CPU, "Switching out\n");
798 BaseCPU::switchOut(_sampler);
796 drainCount = 0;
797 fetch.drain();
798 decode.drain();
799 rename.drain();
800 iew.drain();
801 commit.drain();
802
803 // Wake the CPU and record activity so everything can drain out if

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858}
859
860template <class Impl>
861void
862FullO3CPU<Impl>::switchOut()
863{
864 fetch.switchOut();
865 rename.switchOut();
799 drainCount = 0;
800 fetch.drain();
801 decode.drain();
802 rename.drain();
803 iew.drain();
804 commit.drain();
805
806 // Wake the CPU and record activity so everything can drain out if

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861}
862
863template <class Impl>
864void
865FullO3CPU<Impl>::switchOut()
866{
867 fetch.switchOut();
868 rename.switchOut();
869 iew.switchOut();
866 commit.switchOut();
867 instList.clear();
868 while (!removeList.empty()) {
869 removeList.pop();
870 }
871
872 _status = SwitchedOut;
873#if USE_CHECKER

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926 tickEvent.schedule(curTick);
927 }
928 }
929 if (!tickEvent.scheduled())
930 tickEvent.schedule(curTick);
931}
932
933template <class Impl>
870 commit.switchOut();
871 instList.clear();
872 while (!removeList.empty()) {
873 removeList.pop();
874 }
875
876 _status = SwitchedOut;
877#if USE_CHECKER

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930 tickEvent.schedule(curTick);
931 }
932 }
933 if (!tickEvent.scheduled())
934 tickEvent.schedule(curTick);
935}
936
937template <class Impl>
938void
939FullO3CPU<Impl>::serialize(std::ostream &os)
940{
941 BaseCPU::serialize(os);
942 nameOut(os, csprintf("%s.tickEvent", name()));
943 tickEvent.serialize(os);
944
945 // Use SimpleThread's ability to checkpoint to make it easier to
946 // write out the registers. Also make this static so it doesn't
947 // get instantiated multiple times (causes a panic in statistics).
948 static CPUExecContext temp;
949
950 for (int i = 0; i < thread.size(); i++) {
951 nameOut(os, csprintf("%s.xc.%i", name(), i));
952 temp.copyXC(thread[i]->getXCProxy());
953 temp.serialize(os);
954 }
955}
956
957template <class Impl>
958void
959FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
960{
961 BaseCPU::unserialize(cp, section);
962 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
963
964 // Use SimpleThread's ability to checkpoint to make it easier to
965 // read in the registers. Also make this static so it doesn't
966 // get instantiated multiple times (causes a panic in statistics).
967 static CPUExecContext temp;
968
969 for (int i = 0; i < thread.size(); i++) {
970 temp.copyXC(thread[i]->getXCProxy());
971 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
972 thread[i]->getXCProxy()->copyArchRegs(temp.getProxy());
973 }
974}
975
976template <class Impl>
934uint64_t
935FullO3CPU<Impl>::readIntReg(int reg_idx)
936{
937 return regFile.readIntReg(reg_idx);
938}
939
940template <class Impl>
941FloatReg

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978FullO3CPU<Impl>::readIntReg(int reg_idx)
979{
980 return regFile.readIntReg(reg_idx);
981}
982
983template <class Impl>
984FloatReg

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