cpu.cc (2935:d1223a6c9156) cpu.cc (3093:b09c33e66bce)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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176 decodeQueue(params->backComSize, params->forwardComSize),
177 renameQueue(params->backComSize, params->forwardComSize),
178 iewQueue(params->backComSize, params->forwardComSize),
179 activityRec(NumStages,
180 params->backComSize + params->forwardComSize,
181 params->activity),
182
183 globalSeqNum(1),
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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176 decodeQueue(params->backComSize, params->forwardComSize),
177 renameQueue(params->backComSize, params->forwardComSize),
178 iewQueue(params->backComSize, params->forwardComSize),
179 activityRec(NumStages,
180 params->backComSize + params->forwardComSize,
181 params->activity),
182
183 globalSeqNum(1),
184
185#if FULL_SYSTEM
186 system(params->system),
187 physmem(system->physmem),
188#endif // FULL_SYSTEM
189 mem(params->mem),
190 drainCount(0),
191 deferRegistration(params->deferRegistration),
192 numThreads(number_of_threads)

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317
318 // Setup the ROB for whichever stages need it.
319 commit.setROB(&rob);
320
321 lastRunningCycle = curTick;
322
323 lastActivatedCycle = -1;
324
184#if FULL_SYSTEM
185 system(params->system),
186 physmem(system->physmem),
187#endif // FULL_SYSTEM
188 mem(params->mem),
189 drainCount(0),
190 deferRegistration(params->deferRegistration),
191 numThreads(number_of_threads)

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316
317 // Setup the ROB for whichever stages need it.
318 commit.setROB(&rob);
319
320 lastRunningCycle = curTick;
321
322 lastActivatedCycle = -1;
323
324 // Give renameMap & rename stage access to the freeList;
325 //for (int i=0; i < numThreads; i++) {
326 //globalSeqNum[i] = 1;
327 //}
328
325 contextSwitch = false;
326}
327
328template <class Impl>
329FullO3CPU<Impl>::~FullO3CPU()
330{
331}
332

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622 }
623
624 //Copy Thread Data Into RegFile
625 //this->copyFromTC(tid);
626
627 //Set PC/NPC/NNPC
628 setPC(src_tc->readPC(), tid);
629 setNextPC(src_tc->readNextPC(), tid);
329 contextSwitch = false;
330}
331
332template <class Impl>
333FullO3CPU<Impl>::~FullO3CPU()
334{
335}
336

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626 }
627
628 //Copy Thread Data Into RegFile
629 //this->copyFromTC(tid);
630
631 //Set PC/NPC/NNPC
632 setPC(src_tc->readPC(), tid);
633 setNextPC(src_tc->readNextPC(), tid);
630#if THE_ISA != ALPHA_ISA
634#if ISA_HAS_DELAY_SLOT
631 setNextNPC(src_tc->readNextNPC(), tid);
632#endif
633
634 src_tc->setStatus(ThreadContext::Active);
635
636 activateContext(tid,1);
637
638 //Reset ROB/IQ/LSQ Entries

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1192
1193 inst_it--;
1194
1195 // Walk through the instruction list, removing any instructions
1196 // that were inserted after the given instruction iterator, end_it.
1197 while (inst_it != end_it) {
1198 assert(!instList.empty());
1199
635 setNextNPC(src_tc->readNextNPC(), tid);
636#endif
637
638 src_tc->setStatus(ThreadContext::Active);
639
640 activateContext(tid,1);
641
642 //Reset ROB/IQ/LSQ Entries

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1196
1197 inst_it--;
1198
1199 // Walk through the instruction list, removing any instructions
1200 // that were inserted after the given instruction iterator, end_it.
1201 while (inst_it != end_it) {
1202 assert(!instList.empty());
1203
1200#if THE_ISA != ALPHA_ISA
1204#if ISA_HAS_DELAY_SLOT
1201 if(!squash_delay_slot &&
1202 delay_slot_seq_num >= (*inst_it)->seqNum) {
1203 break;
1204 }
1205#endif
1206 squashInstIt(inst_it, tid);
1207
1208 inst_it--;

--- 182 unchanged lines hidden --- 		1205 if(!squash_delay_slot &&
1206 delay_slot_seq_num >= (*inst_it)->seqNum) {
1207 break;
1208 }
1209#endif
1210 squashInstIt(inst_it, tid);
1211
1212 inst_it--;

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