cpu.cc (2923:db8a876258df) cpu.cc (2935:d1223a6c9156)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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662 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
663 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
664
665 scoreboard.unsetReg(phys_reg);
666 freeList.addReg(phys_reg);
667 }
668
669 // Squash Throughout Pipeline
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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662 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
663 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
664
665 scoreboard.unsetReg(phys_reg);
666 freeList.addReg(phys_reg);
667 }
668
669 // Squash Throughout Pipeline
670 fetch.squash(0,tid);
670 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
671 fetch.squash(0, squash_seq_num, true, tid);
671 decode.squash(tid);
672 decode.squash(tid);
672 rename.squash(tid);
673 rename.squash(squash_seq_num, tid);
673 iew.squash(tid);
674 iew.squash(tid);
674 commit.rob->squash(commit.rob->readHeadInst(tid)->seqNum, tid);
675 commit.rob->squash(squash_seq_num, tid);
675
676 assert(iew.ldstQueue.getCount(tid) == 0);
677
678 // Reset ROB/IQ/LSQ Entries
679 if (activeThreads.size() >= 1) {
680 commit.rob->resetEntries();
681 iew.resetEntries();
682 }

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1096
1097template <class Impl>
1098void
1099FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1100{
1101 commit.setNextPC(val, tid);
1102}
1103
676
677 assert(iew.ldstQueue.getCount(tid) == 0);
678
679 // Reset ROB/IQ/LSQ Entries
680 if (activeThreads.size() >= 1) {
681 commit.rob->resetEntries();
682 iew.resetEntries();
683 }

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1097
1098template <class Impl>
1099void
1100FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1101{
1102 commit.setNextPC(val, tid);
1103}
1104
1104#if THE_ISA != ALPHA_ISA
1105template <class Impl>
1106uint64_t
1107FullO3CPU<Impl>::readNextNPC(unsigned tid)
1108{
1109 return commit.readNextNPC(tid);
1110}
1111
1112template <class Impl>
1113void
1105template <class Impl>
1106uint64_t
1107FullO3CPU<Impl>::readNextNPC(unsigned tid)
1108{
1109 return commit.readNextNPC(tid);
1110}
1111
1112template <class Impl>
1113void
1114FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
1114FullO3CPU::setNextNPC(uint64_t val,unsigned tid)
1115{
1116 commit.setNextNPC(val, tid);
1117}
1115{
1116 commit.setNextNPC(val, tid);
1117}
1118#endif
1119
1120template <class Impl>
1121typename FullO3CPU<Impl>::ListIt
1122FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1123{
1124 instList.push_back(inst);
1125
1126 return --(instList.end());

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1160 removeInstsThisCycle = true;
1161
1162 // Remove the front instruction.
1163 removeList.push(inst->getInstListIt());
1164}
1165
1166template <class Impl>
1167void
1118
1119template <class Impl>
1120typename FullO3CPU<Impl>::ListIt
1121FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1122{
1123 instList.push_back(inst);
1124
1125 return --(instList.end());

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1159 removeInstsThisCycle = true;
1160
1161 // Remove the front instruction.
1162 removeList.push(inst->getInstListIt());
1163}
1164
1165template <class Impl>
1166void
1168FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1167FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1168 bool squash_delay_slot,
1169 const InstSeqNum &delay_slot_seq_num)
1169{
1170 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1171 " list.\n", tid);
1172
1173 ListIt end_it;
1174
1175 bool rob_empty = false;
1176

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1191
1192 inst_it--;
1193
1194 // Walk through the instruction list, removing any instructions
1195 // that were inserted after the given instruction iterator, end_it.
1196 while (inst_it != end_it) {
1197 assert(!instList.empty());
1198
1170{
1171 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1172 " list.\n", tid);
1173
1174 ListIt end_it;
1175
1176 bool rob_empty = false;
1177

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1192
1193 inst_it--;
1194
1195 // Walk through the instruction list, removing any instructions
1196 // that were inserted after the given instruction iterator, end_it.
1197 while (inst_it != end_it) {
1198 assert(!instList.empty());
1199
1200#if THE_ISA != ALPHA_ISA
1201 if(!squash_delay_slot &&
1202 delay_slot_seq_num >= (*inst_it)->seqNum) {
1203 break;
1204 }
1205#endif
1199 squashInstIt(inst_it, tid);
1200
1201 inst_it--;
1202 }
1203
1204 // If the ROB was empty, then we actually need to remove the first
1205 // instruction as well.
1206 if (rob_empty) {

--- 177 unchanged lines hidden --- 		1206 squashInstIt(inst_it, tid);
1207
1208 inst_it--;
1209 }
1210
1211 // If the ROB was empty, then we actually need to remove the first
1212 // instruction as well.
1213 if (rob_empty) {

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