cpu.cc (2911:854ee6cd377e) cpu.cc (2918:20cdaf201249)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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436 activityRec.advance();
437
438 if (removeInstsThisCycle) {
439 cleanUpRemovedInsts();
440 }
441
442 if (!tickEvent.scheduled()) {
443 if (_status == SwitchedOut ||
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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436 activityRec.advance();
437
438 if (removeInstsThisCycle) {
439 cleanUpRemovedInsts();
440 }
441
442 if (!tickEvent.scheduled()) {
443 if (_status == SwitchedOut ||
444 getState() == SimObject::Drained) {
444 getState() == SimObject::DrainedTiming) {
445 // increment stat
446 lastRunningCycle = curTick;
447 } else if (!activityRec.active()) {
448 lastRunningCycle = curTick;
449 timesIdled++;
450 } else {
451 tickEvent.schedule(curTick + cycles(1));
452 }

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572 }
573}
574
575template <class Impl>
576void
577FullO3CPU<Impl>::suspendContext(int tid)
578{
579 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
445 // increment stat
446 lastRunningCycle = curTick;
447 } else if (!activityRec.active()) {
448 lastRunningCycle = curTick;
449 timesIdled++;
450 } else {
451 tickEvent.schedule(curTick + cycles(1));
452 }

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572 }
573}
574
575template <class Impl>
576void
577FullO3CPU<Impl>::suspendContext(int tid)
578{
579 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
580 deactivateThread(tid);
581 if (activeThreads.size() == 0)
582 unscheduleTickEvent();
580 unscheduleTickEvent();
583 _status = Idle;
581 _status = Idle;
582/*
583 //Remove From Active List, if Active
584 list<unsigned>::iterator isActive = find(
585 activeThreads.begin(), activeThreads.end(), tid);
586
587 if (isActive != activeThreads.end()) {
588 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
589 tid);
590 activeThreads.erase(isActive);
591 }
592*/
584}
585
586template <class Impl>
587void
588FullO3CPU<Impl>::haltContext(int tid)
589{
593}
594
595template <class Impl>
596void
597FullO3CPU<Impl>::haltContext(int tid)
598{
590 //For now, this is the same as deallocate
591 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
592 deallocateContext(tid, 1);
599 DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid);
600/*
601 //Remove From Active List, if Active
602 list<unsigned>::iterator isActive = find(
603 activeThreads.begin(), activeThreads.end(), tid);
604
605 if (isActive != activeThreads.end()) {
606 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
607 tid);
608 activeThreads.erase(isActive);
609
610 removeThread(tid);
611 }
612*/
593}
594
595template <class Impl>
596void
597FullO3CPU<Impl>::insertThread(unsigned tid)
598{
599 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
600 // Will change now that the PC and thread state is internal to the CPU

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740 cpuWaitList.push_back(tid);
741 }
742}
743
744template <class Impl>
745void
746FullO3CPU<Impl>::serialize(std::ostream &os)
747{
613}
614
615template <class Impl>
616void
617FullO3CPU<Impl>::insertThread(unsigned tid)
618{
619 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
620 // Will change now that the PC and thread state is internal to the CPU

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760 cpuWaitList.push_back(tid);
761 }
762}
763
764template <class Impl>
765void
766FullO3CPU<Impl>::serialize(std::ostream &os)
767{
748 SERIALIZE_ENUM(_status);
768 SimObject::State so_state = SimObject::getState();
769 SERIALIZE_ENUM(so_state);
749 BaseCPU::serialize(os);
750 nameOut(os, csprintf("%s.tickEvent", name()));
751 tickEvent.serialize(os);
752
753 // Use SimpleThread's ability to checkpoint to make it easier to
754 // write out the registers. Also make this static so it doesn't
755 // get instantiated multiple times (causes a panic in statistics).
756 static SimpleThread temp;

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761 temp.serialize(os);
762 }
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
768{
770 BaseCPU::serialize(os);
771 nameOut(os, csprintf("%s.tickEvent", name()));
772 tickEvent.serialize(os);
773
774 // Use SimpleThread's ability to checkpoint to make it easier to
775 // write out the registers. Also make this static so it doesn't
776 // get instantiated multiple times (causes a panic in statistics).
777 static SimpleThread temp;

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782 temp.serialize(os);
783 }
784}
785
786template <class Impl>
787void
788FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
789{
769 UNSERIALIZE_ENUM(_status);
790 SimObject::State so_state;
791 UNSERIALIZE_ENUM(so_state);
770 BaseCPU::unserialize(cp, section);
771 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
772
773 // Use SimpleThread's ability to checkpoint to make it easier to
774 // read in the registers. Also make this static so it doesn't
775 // get instantiated multiple times (causes a panic in statistics).
776 static SimpleThread temp;
777
778 for (int i = 0; i < thread.size(); i++) {
779 temp.copyTC(thread[i]->getTC());
780 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
781 thread[i]->getTC()->copyArchRegs(temp.getTC());
782 }
783}
784
785template <class Impl>
792 BaseCPU::unserialize(cp, section);
793 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
794
795 // Use SimpleThread's ability to checkpoint to make it easier to
796 // read in the registers. Also make this static so it doesn't
797 // get instantiated multiple times (causes a panic in statistics).
798 static SimpleThread temp;
799
800 for (int i = 0; i < thread.size(); i++) {
801 temp.copyTC(thread[i]->getTC());
802 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
803 thread[i]->getTC()->copyArchRegs(temp.getTC());
804 }
805}
806
807template <class Impl>
786unsigned int
808bool
787FullO3CPU<Impl>::drain(Event *drain_event)
788{
789 drainCount = 0;
790 fetch.drain();
791 decode.drain();
792 rename.drain();
793 iew.drain();
794 commit.drain();
795
796 // Wake the CPU and record activity so everything can drain out if
797 // the CPU was not able to immediately drain.
809FullO3CPU<Impl>::drain(Event *drain_event)
810{
811 drainCount = 0;
812 fetch.drain();
813 decode.drain();
814 rename.drain();
815 iew.drain();
816 commit.drain();
817
818 // Wake the CPU and record activity so everything can drain out if
819 // the CPU was not able to immediately drain.
798 if (getState() != SimObject::Drained) {
820 if (getState() != SimObject::DrainedTiming) {
799 // A bit of a hack...set the drainEvent after all the drain()
800 // calls have been made, that way if all of the stages drain
801 // immediately, the signalDrained() function knows not to call
802 // process on the drain event.
803 drainEvent = drain_event;
804
805 wakeCPU();
806 activityRec.activity();
807
821 // A bit of a hack...set the drainEvent after all the drain()
822 // calls have been made, that way if all of the stages drain
823 // immediately, the signalDrained() function knows not to call
824 // process on the drain event.
825 drainEvent = drain_event;
826
827 wakeCPU();
828 activityRec.activity();
829
808 return 1;
830 return false;
809 } else {
831 } else {
810 return 0;
832 return true;
811 }
812}
813
814template <class Impl>
815void
816FullO3CPU<Impl>::resume()
817{
833 }
834}
835
836template <class Impl>
837void
838FullO3CPU<Impl>::resume()
839{
818 assert(system->getMemoryMode() == System::Timing);
819 fetch.resume();
820 decode.resume();
821 rename.resume();
822 iew.resume();
823 commit.resume();
824
840 fetch.resume();
841 decode.resume();
842 rename.resume();
843 iew.resume();
844 commit.resume();
845
825 changeState(SimObject::Running);
826
827 if (_status == SwitchedOut || _status == Idle)
828 return;
829
830 if (!tickEvent.scheduled())
831 tickEvent.schedule(curTick);
832 _status = Running;
846 if (_status == SwitchedOut || _status == Idle)
847 return;
848
849 if (!tickEvent.scheduled())
850 tickEvent.schedule(curTick);
851 _status = Running;
852 changeState(SimObject::Timing);
833}
834
835template <class Impl>
836void
837FullO3CPU<Impl>::signalDrained()
838{
839 if (++drainCount == NumStages) {
840 if (tickEvent.scheduled())
841 tickEvent.squash();
842
853}
854
855template <class Impl>
856void
857FullO3CPU<Impl>::signalDrained()
858{
859 if (++drainCount == NumStages) {
860 if (tickEvent.scheduled())
861 tickEvent.squash();
862
843 changeState(SimObject::Drained);
863 changeState(SimObject::DrainedTiming);
844
845 if (drainEvent) {
846 drainEvent->process();
847 drainEvent = NULL;
848 }
849 }
850 assert(drainCount <= 5);
851}

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1040
1041 regFile.setIntReg(phys_reg, val);
1042}
1043
1044template <class Impl>
1045void
1046FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1047{
864
865 if (drainEvent) {
866 drainEvent->process();
867 drainEvent = NULL;
868 }
869 }
870 assert(drainCount <= 5);
871}

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1060
1061 regFile.setIntReg(phys_reg, val);
1062}
1063
1064template <class Impl>
1065void
1066FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1067{
1048 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1068 int idx = reg_idx + TheISA::FP_Base_DepTag;
1069 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1049
1050 regFile.setFloatReg(phys_reg, val);
1051}
1052
1053template <class Impl>
1054void
1055FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1056{
1070
1071 regFile.setFloatReg(phys_reg, val);
1072}
1073
1074template <class Impl>
1075void
1076FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1077{
1057 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1078 int idx = reg_idx + TheISA::FP_Base_DepTag;
1079 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1058
1059 regFile.setFloatReg(phys_reg, val, 64);
1060}
1061
1062template <class Impl>
1063void
1064FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1065{
1080
1081 regFile.setFloatReg(phys_reg, val, 64);
1082}
1083
1084template <class Impl>
1085void
1086FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1087{
1066 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1088 int idx = reg_idx + TheISA::FP_Base_DepTag;
1089 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1067
1068 regFile.setFloatRegBits(phys_reg, val);
1069}
1070
1071template <class Impl>
1072uint64_t
1073FullO3CPU<Impl>::readPC(unsigned tid)
1074{

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1091 regFile.setFloatRegBits(phys_reg, val);
1092}
1093
1094template <class Impl>
1095uint64_t
1096FullO3CPU<Impl>::readPC(unsigned tid)
1097{

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