cpu.cc (2886:2fdb9976b0a3) cpu.cc (2905:62879b0282eb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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436 activityRec.advance();
437
438 if (removeInstsThisCycle) {
439 cleanUpRemovedInsts();
440 }
441
442 if (!tickEvent.scheduled()) {
443 if (_status == SwitchedOut ||
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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436 activityRec.advance();
437
438 if (removeInstsThisCycle) {
439 cleanUpRemovedInsts();
440 }
441
442 if (!tickEvent.scheduled()) {
443 if (_status == SwitchedOut ||
444 getState() == SimObject::DrainedTiming) {
444 getState() == SimObject::Drained) {
445 // increment stat
446 lastRunningCycle = curTick;
447 } else if (!activityRec.active()) {
448 lastRunningCycle = curTick;
449 timesIdled++;
450 } else {
451 tickEvent.schedule(curTick + cycles(1));
452 }

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798 for (int i = 0; i < thread.size(); i++) {
799 temp.copyTC(thread[i]->getTC());
800 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
801 thread[i]->getTC()->copyArchRegs(temp.getTC());
802 }
803}
804
805template <class Impl>
445 // increment stat
446 lastRunningCycle = curTick;
447 } else if (!activityRec.active()) {
448 lastRunningCycle = curTick;
449 timesIdled++;
450 } else {
451 tickEvent.schedule(curTick + cycles(1));
452 }

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798 for (int i = 0; i < thread.size(); i++) {
799 temp.copyTC(thread[i]->getTC());
800 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
801 thread[i]->getTC()->copyArchRegs(temp.getTC());
802 }
803}
804
805template <class Impl>
806bool
806unsigned int
807FullO3CPU<Impl>::drain(Event *drain_event)
808{
809 drainCount = 0;
810 fetch.drain();
811 decode.drain();
812 rename.drain();
813 iew.drain();
814 commit.drain();
815
816 // Wake the CPU and record activity so everything can drain out if
817 // the CPU was not able to immediately drain.
807FullO3CPU<Impl>::drain(Event *drain_event)
808{
809 drainCount = 0;
810 fetch.drain();
811 decode.drain();
812 rename.drain();
813 iew.drain();
814 commit.drain();
815
816 // Wake the CPU and record activity so everything can drain out if
817 // the CPU was not able to immediately drain.
818 if (getState() != SimObject::DrainedTiming) {
818 if (getState() != SimObject::Drained) {
819 // A bit of a hack...set the drainEvent after all the drain()
820 // calls have been made, that way if all of the stages drain
821 // immediately, the signalDrained() function knows not to call
822 // process on the drain event.
823 drainEvent = drain_event;
824
825 wakeCPU();
826 activityRec.activity();
827
819 // A bit of a hack...set the drainEvent after all the drain()
820 // calls have been made, that way if all of the stages drain
821 // immediately, the signalDrained() function knows not to call
822 // process on the drain event.
823 drainEvent = drain_event;
824
825 wakeCPU();
826 activityRec.activity();
827
828 return false;
828 return 1;
829 } else {
829 } else {
830 return true;
830 return 0;
831 }
832}
833
834template <class Impl>
835void
836FullO3CPU<Impl>::resume()
837{
831 }
832}
833
834template <class Impl>
835void
836FullO3CPU<Impl>::resume()
837{
838 assert(system->getMemoryMode() == System::Timing);
838 fetch.resume();
839 decode.resume();
840 rename.resume();
841 iew.resume();
842 commit.resume();
843
839 fetch.resume();
840 decode.resume();
841 rename.resume();
842 iew.resume();
843 commit.resume();
844
845 changeState(SimObject::Running);
846
844 if (_status == SwitchedOut || _status == Idle)
845 return;
846
847 if (!tickEvent.scheduled())
848 tickEvent.schedule(curTick);
849 _status = Running;
847 if (_status == SwitchedOut || _status == Idle)
848 return;
849
850 if (!tickEvent.scheduled())
851 tickEvent.schedule(curTick);
852 _status = Running;
850 changeState(SimObject::Timing);
851}
852
853template <class Impl>
854void
855FullO3CPU<Impl>::signalDrained()
856{
857 if (++drainCount == NumStages) {
858 if (tickEvent.scheduled())
859 tickEvent.squash();
860
853}
854
855template <class Impl>
856void
857FullO3CPU<Impl>::signalDrained()
858{
859 if (++drainCount == NumStages) {
860 if (tickEvent.scheduled())
861 tickEvent.squash();
862
861 changeState(SimObject::DrainedTiming);
863 changeState(SimObject::Drained);
862
863 if (drainEvent) {
864 drainEvent->process();
865 drainEvent = NULL;
866 }
867 }
868 assert(drainCount <= 5);
869}

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865 if (drainEvent) {
866 drainEvent->process();
867 drainEvent = NULL;
868 }
869 }
870 assert(drainCount <= 5);
871}

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