cpu.cc (2849:c285bf8ffb4a) | cpu.cc (2852:7fc1b748dd81) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 144 unchanged lines hidden (view full) --- 153 154 globalSeqNum(1), 155 156#if FULL_SYSTEM 157 system(params->system), 158 physmem(system->physmem), 159#endif // FULL_SYSTEM 160 mem(params->mem), | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 144 unchanged lines hidden (view full) --- 153 154 globalSeqNum(1), 155 156#if FULL_SYSTEM 157 system(params->system), 158 physmem(system->physmem), 159#endif // FULL_SYSTEM 160 mem(params->mem), |
161 switchCount(0), | 161 drainCount(0), |
162 deferRegistration(params->deferRegistration), 163 numThreads(number_of_threads) 164{ 165 _status = Idle; 166 167 checker = NULL; 168 169 if (params->checker) { --- 533 unchanged lines hidden (view full) --- 703 activeThreads.erase(isActive); 704 705 removeThread(tid); 706 } 707*/ 708} 709 710template <class Impl> | 162 deferRegistration(params->deferRegistration), 163 numThreads(number_of_threads) 164{ 165 _status = Idle; 166 167 checker = NULL; 168 169 if (params->checker) { --- 533 unchanged lines hidden (view full) --- 703 activeThreads.erase(isActive); 704 705 removeThread(tid); 706 } 707*/ 708} 709 710template <class Impl> |
711void 712FullO3CPU<Impl>::switchOut() | 711bool 712FullO3CPU<Impl>::drain(Event *drain_event) |
713{ | 713{ |
714 switchCount = 0; 715 fetch.switchOut(); 716 decode.switchOut(); 717 rename.switchOut(); 718 iew.switchOut(); 719 commit.switchOut(); | 714 drainCount = 0; 715 drainEvent = drain_event; 716 fetch.drain(); 717 decode.drain(); 718 rename.drain(); 719 iew.drain(); 720 commit.drain(); |
720 721 // Wake the CPU and record activity so everything can drain out if 722 // the CPU is currently idle. 723 wakeCPU(); 724 activityRec.activity(); | 721 722 // Wake the CPU and record activity so everything can drain out if 723 // the CPU is currently idle. 724 wakeCPU(); 725 activityRec.activity(); |
726 727 return false; |
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725} 726 727template <class Impl> 728void | 728} 729 730template <class Impl> 731void |
729FullO3CPU<Impl>::signalSwitched() | 732FullO3CPU<Impl>::resume() |
730{ | 733{ |
731 if (++switchCount == NumStages) { 732 fetch.doSwitchOut(); 733 rename.doSwitchOut(); 734 commit.doSwitchOut(); 735 instList.clear(); 736 while (!removeList.empty()) { 737 removeList.pop(); 738 } | 734 if (_status == SwitchedOut) 735 return; 736 fetch.resume(); 737 decode.resume(); 738 rename.resume(); 739 iew.resume(); 740 commit.resume(); |
739 | 741 |
740#if USE_CHECKER 741 if (checker) 742 checker->switchOut(); 743#endif | 742 if (!tickEvent.scheduled()) 743 tickEvent.schedule(curTick); 744 _status = Running; 745} |
744 | 746 |
747template <class Impl> 748void 749FullO3CPU<Impl>::signalDrained() 750{ 751 if (++drainCount == NumStages) { |
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745 if (tickEvent.scheduled()) 746 tickEvent.squash(); | 752 if (tickEvent.scheduled()) 753 tickEvent.squash(); |
747 _status = SwitchedOut; | 754 _status = Drained; 755 drainEvent->process(); |
748 } | 756 } |
749 assert(switchCount <= 5); | 757 assert(drainCount <= 5); |
750} 751 752template <class Impl> 753void | 758} 759 760template <class Impl> 761void |
762FullO3CPU<Impl>::switchOut() 763{ 764 fetch.switchOut(); 765 rename.switchOut(); 766 commit.switchOut(); 767 instList.clear(); 768 while (!removeList.empty()) { 769 removeList.pop(); 770 } 771 772 _status = SwitchedOut; 773#if USE_CHECKER 774 if (checker) 775 checker->switchOut(); 776#endif 777} 778 779template <class Impl> 780void |
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754FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 755{ 756 // Flush out any old data from the time buffers. 757 for (int i = 0; i < 10; ++i) { 758 timeBuffer.advance(); 759 fetchQueue.advance(); 760 decodeQueue.advance(); 761 renameQueue.advance(); --- 497 unchanged lines hidden --- | 781FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 782{ 783 // Flush out any old data from the time buffers. 784 for (int i = 0; i < 10; ++i) { 785 timeBuffer.advance(); 786 fetchQueue.advance(); 787 decodeQueue.advance(); 788 renameQueue.advance(); --- 497 unchanged lines hidden --- |