cpu.cc (2843:19c4c6c2b5b1) | cpu.cc (2847:6b19f07d9666) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 144 unchanged lines hidden (view full) --- 153 154 globalSeqNum(1), 155 156#if FULL_SYSTEM 157 system(params->system), 158 physmem(system->physmem), 159#endif // FULL_SYSTEM 160 mem(params->mem), | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 144 unchanged lines hidden (view full) --- 153 154 globalSeqNum(1), 155 156#if FULL_SYSTEM 157 system(params->system), 158 physmem(system->physmem), 159#endif // FULL_SYSTEM 160 mem(params->mem), |
161 drainCount(0), | 161 switchCount(0), |
162 deferRegistration(params->deferRegistration), 163 numThreads(number_of_threads) 164{ 165 _status = Idle; 166 167 checker = NULL; 168 169 if (params->checker) { --- 288 unchanged lines hidden (view full) --- 458 459 commit.setThreads(thread); 460} 461 462template <class Impl> 463void 464FullO3CPU<Impl>::insertThread(unsigned tid) 465{ | 162 deferRegistration(params->deferRegistration), 163 numThreads(number_of_threads) 164{ 165 _status = Idle; 166 167 checker = NULL; 168 169 if (params->checker) { --- 288 unchanged lines hidden (view full) --- 458 459 commit.setThreads(thread); 460} 461 462template <class Impl> 463void 464FullO3CPU<Impl>::insertThread(unsigned tid) 465{ |
466 DPRINTF(O3CPU,"[tid:%i] Initializing thread data"); | 466 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); |
467 // Will change now that the PC and thread state is internal to the CPU 468 // and not in the ThreadContext. | 467 // Will change now that the PC and thread state is internal to the CPU 468 // and not in the ThreadContext. |
469#if 0 | |
470#if FULL_SYSTEM 471 ThreadContext *src_tc = system->threadContexts[tid]; 472#else | 469#if FULL_SYSTEM 470 ThreadContext *src_tc = system->threadContexts[tid]; 471#else |
473 ThreadContext *src_tc = thread[tid]; | 472 ThreadContext *src_tc = tcBase(tid); |
474#endif 475 476 //Bind Int Regs to Rename Map 477 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 478 PhysRegIndex phys_reg = freeList.getIntReg(); 479 480 renameMap[tid].setEntry(ireg,phys_reg); 481 scoreboard.setReg(phys_reg); 482 } 483 484 //Bind Float Regs to Rename Map 485 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 486 PhysRegIndex phys_reg = freeList.getFloatReg(); 487 488 renameMap[tid].setEntry(freg,phys_reg); 489 scoreboard.setReg(phys_reg); 490 } 491 492 //Copy Thread Data Into RegFile | 473#endif 474 475 //Bind Int Regs to Rename Map 476 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 477 PhysRegIndex phys_reg = freeList.getIntReg(); 478 479 renameMap[tid].setEntry(ireg,phys_reg); 480 scoreboard.setReg(phys_reg); 481 } 482 483 //Bind Float Regs to Rename Map 484 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 485 PhysRegIndex phys_reg = freeList.getFloatReg(); 486 487 renameMap[tid].setEntry(freg,phys_reg); 488 scoreboard.setReg(phys_reg); 489 } 490 491 //Copy Thread Data Into RegFile |
493 this->copyFromTC(tid); | 492 //this->copyFromTC(tid); |
494 | 493 |
495 //Set PC/NPC 496 regFile.pc[tid] = src_tc->readPC(); 497 regFile.npc[tid] = src_tc->readNextPC(); | 494 //Set PC/NPC/NNPC 495 setPC(src_tc->readPC(), tid); 496 setNextPC(src_tc->readNextPC(), tid); 497#if THE_ISA != ALPHA_ISA 498 setNextNPC(src_tc->readNextNPC(), tid); 499#endif |
498 499 src_tc->setStatus(ThreadContext::Active); 500 501 activateContext(tid,1); 502 503 //Reset ROB/IQ/LSQ Entries 504 commit.rob->resetEntries(); 505 iew.resetEntries(); | 500 501 src_tc->setStatus(ThreadContext::Active); 502 503 activateContext(tid,1); 504 505 //Reset ROB/IQ/LSQ Entries 506 commit.rob->resetEntries(); 507 iew.resetEntries(); |
506#endif | |
507} 508 509template <class Impl> 510void 511FullO3CPU<Impl>::removeThread(unsigned tid) 512{ | 508} 509 510template <class Impl> 511void 512FullO3CPU<Impl>::removeThread(unsigned tid) 513{ |
513 DPRINTF(O3CPU,"[tid:%i] Removing thread data"); 514#if 0 515 //Unbind Int Regs from Rename Map | 514 DPRINTF(O3CPU,"[tid:%i] Removing thread from CPU."); 515 516 // Copy Thread Data From RegFile 517 // If thread is suspended, it might be re-allocated 518 //this->copyToTC(tid); 519 520 // Unbind Int Regs from Rename Map |
516 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 517 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 518 519 scoreboard.unsetReg(phys_reg); 520 freeList.addReg(phys_reg); 521 } 522 | 521 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 522 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 523 524 scoreboard.unsetReg(phys_reg); 525 freeList.addReg(phys_reg); 526 } 527 |
523 //Unbind Float Regs from Rename Map | 528 // Unbind Float Regs from Rename Map |
524 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 525 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 526 527 scoreboard.unsetReg(phys_reg); 528 freeList.addReg(phys_reg); 529 } 530 | 529 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 530 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 531 532 scoreboard.unsetReg(phys_reg); 533 freeList.addReg(phys_reg); 534 } 535 |
531 //Copy Thread Data From RegFile 532 /* Fix Me: 533 * Do we really need to do this if we are removing a thread 534 * in the sense that it's finished (exiting)? If the thread is just 535 * being suspended we might... 536 */ 537// this->copyToTC(tid); 538 539 //Squash Throughout Pipeline | 536 // Squash Throughout Pipeline |
540 fetch.squash(0,tid); 541 decode.squash(tid); 542 rename.squash(tid); 543 544 assert(iew.ldstQueue.getCount(tid) == 0); 545 | 537 fetch.squash(0,tid); 538 decode.squash(tid); 539 rename.squash(tid); 540 541 assert(iew.ldstQueue.getCount(tid) == 0); 542 |
546 //Reset ROB/IQ/LSQ Entries | 543 // Reset ROB/IQ/LSQ Entries |
547 if (activeThreads.size() >= 1) { 548 commit.rob->resetEntries(); 549 iew.resetEntries(); 550 } | 544 if (activeThreads.size() >= 1) { 545 commit.rob->resetEntries(); 546 iew.resetEntries(); 547 } |
551#endif | |
552} 553 554 555template <class Impl> 556void 557FullO3CPU<Impl>::activateWhenReady(int tid) 558{ 559 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" --- 91 unchanged lines hidden (view full) --- 651 _status = Running; 652 } 653} 654 655template <class Impl> 656void 657FullO3CPU<Impl>::suspendContext(int tid) 658{ | 548} 549 550 551template <class Impl> 552void 553FullO3CPU<Impl>::activateWhenReady(int tid) 554{ 555 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" --- 91 unchanged lines hidden (view full) --- 647 _status = Running; 648 } 649} 650 651template <class Impl> 652void 653FullO3CPU<Impl>::suspendContext(int tid) 654{ |
659 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid); | 655 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); |
660 unscheduleTickEvent(); 661 _status = Idle; 662/* 663 //Remove From Active List, if Active 664 list<unsigned>::iterator isActive = find( 665 activeThreads.begin(), activeThreads.end(), tid); 666 667 if (isActive != activeThreads.end()) { 668 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 669 tid); 670 activeThreads.erase(isActive); 671 } 672*/ 673} 674 675template <class Impl> 676void 677FullO3CPU<Impl>::deallocateContext(int tid) 678{ | 656 unscheduleTickEvent(); 657 _status = Idle; 658/* 659 //Remove From Active List, if Active 660 list<unsigned>::iterator isActive = find( 661 activeThreads.begin(), activeThreads.end(), tid); 662 663 if (isActive != activeThreads.end()) { 664 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 665 tid); 666 activeThreads.erase(isActive); 667 } 668*/ 669} 670 671template <class Impl> 672void 673FullO3CPU<Impl>::deallocateContext(int tid) 674{ |
679 DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid); 680/* | 675 DPRINTF(O3CPU,"[tid:%i]: Deallocating Thread Context", tid); 676 |
681 //Remove From Active List, if Active | 677 //Remove From Active List, if Active |
682 list<unsigned>::iterator isActive = find( 683 activeThreads.begin(), activeThreads.end(), tid); | 678 list<unsigned>::iterator thread_it = 679 find(activeThreads.begin(), activeThreads.end(), tid); |
684 | 680 |
685 if (isActive != activeThreads.end()) { | 681 if (thread_it != activeThreads.end()) { |
686 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 687 tid); | 682 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 683 tid); |
688 activeThreads.erase(isActive); | 684 activeThreads.erase(thread_it); |
689 690 removeThread(tid); 691 } | 685 686 removeThread(tid); 687 } |
692*/ | |
693} 694 695template <class Impl> 696void 697FullO3CPU<Impl>::haltContext(int tid) 698{ | 688} 689 690template <class Impl> 691void 692FullO3CPU<Impl>::haltContext(int tid) 693{ |
699 DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid); | 694 DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid); |
700/* 701 //Remove From Active List, if Active 702 list<unsigned>::iterator isActive = find( 703 activeThreads.begin(), activeThreads.end(), tid); 704 705 if (isActive != activeThreads.end()) { 706 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 707 tid); 708 activeThreads.erase(isActive); 709 710 removeThread(tid); 711 } 712*/ 713} 714 715template <class Impl> | 695/* 696 //Remove From Active List, if Active 697 list<unsigned>::iterator isActive = find( 698 activeThreads.begin(), activeThreads.end(), tid); 699 700 if (isActive != activeThreads.end()) { 701 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 702 tid); 703 activeThreads.erase(isActive); 704 705 removeThread(tid); 706 } 707*/ 708} 709 710template <class Impl> |
716bool 717FullO3CPU<Impl>::drain(Event *drain_event) | 711void 712FullO3CPU<Impl>::switchOut(Sampler *_sampler) |
718{ | 713{ |
719 drainCount = 0; 720 drainEvent = drain_event; 721 fetch.drain(); 722 decode.drain(); 723 rename.drain(); 724 iew.drain(); 725 commit.drain(); | 714 sampler = _sampler; 715 switchCount = 0; 716 fetch.switchOut(); 717 decode.switchOut(); 718 rename.switchOut(); 719 iew.switchOut(); 720 commit.switchOut(); |
726 727 // Wake the CPU and record activity so everything can drain out if 728 // the CPU is currently idle. 729 wakeCPU(); 730 activityRec.activity(); | 721 722 // Wake the CPU and record activity so everything can drain out if 723 // the CPU is currently idle. 724 wakeCPU(); 725 activityRec.activity(); |
731 732 return false; | |
733} 734 735template <class Impl> 736void | 726} 727 728template <class Impl> 729void |
737FullO3CPU<Impl>::resume() | 730FullO3CPU<Impl>::signalSwitched() |
738{ | 731{ |
739 if (_status == SwitchedOut) 740 return; 741 fetch.resume(); 742 decode.resume(); 743 rename.resume(); 744 iew.resume(); 745 commit.resume(); | 732 if (++switchCount == NumStages) { 733 fetch.doSwitchOut(); 734 rename.doSwitchOut(); 735 commit.doSwitchOut(); 736 instList.clear(); 737 while (!removeList.empty()) { 738 removeList.pop(); 739 } |
746 | 740 |
747 if (!tickEvent.scheduled()) 748 tickEvent.schedule(curTick); 749 _status = Running; 750} | 741#if USE_CHECKER 742 if (checker) 743 checker->switchOut(sampler); 744#endif |
751 | 745 |
752template <class Impl> 753void 754FullO3CPU<Impl>::signalDrained() 755{ 756 if (++drainCount == NumStages) { | |
757 if (tickEvent.scheduled()) 758 tickEvent.squash(); | 746 if (tickEvent.scheduled()) 747 tickEvent.squash(); |
759 _status = Drained; 760 drainEvent->process(); | 748 sampler->signalSwitched(); 749 _status = SwitchedOut; |
761 } | 750 } |
762 assert(drainCount <= 5); | 751 assert(switchCount <= 5); |
763} 764 765template <class Impl> 766void | 752} 753 754template <class Impl> 755void |
767FullO3CPU<Impl>::switchOut() 768{ 769 fetch.switchOut(); 770 rename.switchOut(); 771 commit.switchOut(); 772 instList.clear(); 773 while (!removeList.empty()) { 774 removeList.pop(); 775 } 776 777 _status = SwitchedOut; 778#if USE_CHECKER 779 if (checker) 780 checker->switchOut(); 781#endif 782} 783 784template <class Impl> 785void | |
786FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 787{ 788 // Flush out any old data from the time buffers. 789 for (int i = 0; i < 10; ++i) { 790 timeBuffer.advance(); 791 fetchQueue.advance(); 792 decodeQueue.advance(); 793 renameQueue.advance(); --- 497 unchanged lines hidden --- | 756FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 757{ 758 // Flush out any old data from the time buffers. 759 for (int i = 0; i < 10; ++i) { 760 timeBuffer.advance(); 761 fetchQueue.advance(); 762 decodeQueue.advance(); 763 renameQueue.advance(); --- 497 unchanged lines hidden --- |